Laurent Fesquet

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"katell-morin-allory"

	Un projet de microélectronique numérique original : Contrôle autonome d'un micro-drone par caméras externes Laurent Fesquet , Katell Morin-Allory , Robin Rolland-Girod Journal sur l'enseignement des sciences et technologies de l'information et des systèmes, 2015, 14 (2009), pp.9. ⟨10.1051/j3ea/2015021⟩ Article dans une revue hal-01334687v1

	Data-driven Pruning for Bundled-data Circuits Cristiano Merio , Xavier Lesage , Ali Naimi , Sylvain Engels , Katell Morin-Allory 28th International Symposium on Asynchronous Circuits and Systems (ASYNC 2023, Jul 2023, Beijing, China Communication dans un congrès hal-04331929v1
	A Generic CDC Modeling for Data Stability Verification Diana Kalel , Jean-Christophe Brignone , Laurent Fesquet , Katell Morin-Allory IEEE 30th International Conference on Electronics, Circuits and Systems (ICECS 2023), Dec 2023, Istanbul, Turkey Communication dans un congrès hal-04331999v1
	Method for Data-Driven Pruning in Micropipeline Circuits Cristiano Merio , Xavier Lesage , Ali Naimi , Sylvain Engels , Katell Morin-Allory 31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), Oct 2023, Sharjah, United Arab Emirates Communication dans un congrès hal-04331953v1
	A High-Level Design Flow for Locally Body-Biased Asynchronous Circuits Yoan Decoudu , Katell Morin-Allory , Laurent Fesquet 29th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2021), Oct 2021, Singapore, Singapore. ⟨10.1109/VLSI-SoC53125.2021.9606977⟩ Communication dans un congrès hal-03662244v1
	Body-Bias Micro-Generators for Activity-Driven Power Management Laurent Fesquet , Yoan Decoudu , Rodrigo Iga Jadue , Thiago Ferreira de Paiva Leite , O. Rolloff FDSOI workshop at DATE Conference 2020, Mar 2020, Grenoble, France Communication dans un congrès hal-02956260v1
	From High-Level Synthesis to Bundled-Data Circuits Yoan Decoudu , Jean Simatic , Katell Morin-Allory , Laurent Fesquet International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020), Jul 2020, Samos, Greece Communication dans un congrès hal-02956234v1
	Comparison of Synchronous and Asynchronous FIR Filter Architecture Yoan Decoudu , Jean Simatic , Pauline Alexandre , Katell Morin-Allory , Laurent Fesquet 5th International Conference on Event-Based Control, Communication, and Signal Processing, May 2019, Vienna, Austria Communication dans un congrès hal-02157364v1
	A Distributed Body-Biasing Strategy for Asynchronous Circuits Laurent Fesquet , Yoan Decoudu , Rodrigo Iga Jadue , Thiago Ferreira de Paiva Leite , O. Rolloff 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2019), Oct 2019, Cuzco, Peru Communication dans un congrès hal-02170157v1
	Desynchronizing Circuits Synthesized with CatapultC Yoan Decoudu , Jean Simatic , Katell Morin-Allory , Laurent Fesquet IPSoC 2019, Dec 2019, Grenoble, France Communication dans un congrès hal-02956177v1
	Contrôle autonome d'un nano-drone par caméra externe Laurent Fesquet , Katell Morin-Allory , R. Robin Journées pédagogiques du CNFM (JPCNFM), Nov 2014, Saint-Malo, France Communication dans un congrès hal-01166159v1
	Model of a Simple yet effective Operational Amplifier F. Paugnat , Laurent Fesquet , Katell Morin-Allory International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'12), Sep 2012, Seville, Spain. pp.165-168, ⟨10.1109/SMACD.2012.6339443⟩ Communication dans un congrès hal-00746450v1
	Vérification formelle Katell Morin-Allory , Laurent Fesquet 12èmes Journées Pédagogiques de la Coordination Nationale pour la Formation en Micro et nanoélectronique (JPCNFM’12), Nov 2012, Saint-Malo, France Communication dans un congrès hal-01413187v1
	A Performance Comparison Between the SystemC-AMS Models of Computation F. Paugnat , L. Bousquet , Katell Morin-Allory , Laurent Fesquet edaWorkshop, May 2011, Dresden, Germany. pp.13-18 Communication dans un congrès hal-00652944v1
	Formal Verification of C-element Circuits C. Yan , Laurent Fesquet , F. Ouchet , Katell Morin-Allory IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'11), Apr 2011, Ithaca (NY), United States. pp.55 - 64, ⟨10.1109/ASYNC.2011.14⟩ Communication dans un congrès hal-00624249v1
	C-elements for hardened self-timed circuits F. Ouchet , Katell Morin-Allory , Laurent Fesquet 21st International Workshop on Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS'11), Sep 2011, Madrid, Spain. pp.247-256, ⟨10.1007/978-3-642-24154-3_25⟩ Communication dans un congrès hal-00652365v1
	A refinement process for top-down mixed-signal designs thanks to SystemC-AMS F. Paugnat , Katell Morin-Allory , Laurent Fesquet IEEE 9th International New Circuits and Systems Conference (NEWCAS), Jun 2011, Bordeaux, France. pp.378 - 381, ⟨10.1109/NEWCAS.2011.5981249⟩ Communication dans un congrès hal-00646654v1
	Synthesis of Quasi Delay Insensitive Monitors A. Porcher , Katell Morin-Allory , Laurent Fesquet 7th Conference on PhD Research in Microelectronics and Electronics (PRIME'11), Jul 2011, Madonna Di Campiglio (Trento), Italy. pp.225 - 228, ⟨10.1109/PRIME.2011.5966274⟩ Communication dans un congrès hal-00646662v1
	Does Asynchronous technology bring robustness in synchronous circuit monitoring? A. Porcher , Katell Morin-Allory , Laurent Fesquet Forum on specification & Design Languages (FDL'11), Sep 2011, Oldenburg, Germany Communication dans un congrès hal-00646699v1
	Synthesis of asynchronous monitors for critical electronic systems A. Porcher , Katell Morin-Allory , Laurent Fesquet IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'10), Apr 2010, Vienna, Austria. pp.329 - 334, ⟨10.1109/DDECS.2010.5491756⟩ Communication dans un congrès hal-00517676v1
	Delay Insensitivity Does Not Mean Slope Insensitivity! F. Ouchet , Katell Morin-Allory , Laurent Fesquet IEEE Symposium on Asynchronous Circuits and Systems (ASYNC'10), May 2010, Grenoble, France. pp.176 - 184, ⟨10.1109/ASYNC.2010.27⟩ Communication dans un congrès hal-00492923v1
	RAT-based formal verification of QDI asynchronous controllers K. Alsayeg , Katell Morin-Allory , Laurent Fesquet Forum on specifications and Design Languages (FDL'09), Sep 2009, Nice, Sophia Antipolis, France. pp.1-6 Communication dans un congrès hal-00471574v1
	Initiation à la conception de VLSI numériques Lorena Anghel , Laurent Fesquet , Katell Morin-Allory 10èmes journées pédagogiques CNFM, Nov 2008, Saint-Malo, France Communication dans un congrès hal-00385508v1
	Asynchronous online monitoring of logical and temporal assertions Katell Morin-Allory , Laurent Fesquet , D. Borrione 10th Forum on Specification and Design Languages (FDL'07), Sep 2007, Barcelona, Spain Communication dans un congrès hal-00222895v1
	Asynchronous Assertion Monitors for multi-Clock Domain System Verification Katell Morin-Allory , Laurent Fesquet , D. Borrione Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), IEEE, 2006, Chania, Crète, Greece. pp.98- 102, ⟨10.1109/RSP.2006.9⟩ Communication dans un congrès hal-00134475v1
	Asynchronous on-line monitoring of PSL assertions Katell Morin-Allory , Laurent Fesquet , D. Borrione Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), IEEE, 2006, Chania, Crète, Greece. pp.98 102, ⟨10.1109/RSP.2006.9⟩ Communication dans un congrès hal-00130525v1
	On-Line Assertion-Based Verification with Proven Correct Monitors D. Borrione , Z.W. Liu , Katell Morin-Allory , P. Ostier , Laurent Fesquet 3rd IEEE International Conference on Information and Communication Technology (ICICT'05), December 5-6, 2005, 2005, cairo, Egypt. pp.123-143 Communication dans un congrès hal-00078798v1

	Asynchronous on-line monitoring of logical and temporal assertions Katell Morin-Allory , Laurent Fesquet , Benjamin Roustan , Dominique Borrione Villar Eugenio. Embedded Systems Specification and Design Languages: Selected Contributions from FDL'07, 10, Springer, pp.243-253, 2008, Lecture Notes in Electrical Engineering, ⟨10.1007/978-1-4020-8297-9_17⟩ Chapitre d'ouvrage hal-00293779v1

	Logiciel D. Borrione , L. Ferro , Laurent Fesquet , Katell Morin-Allory , Y. Oddos France, Patent n° : FR.001.220016.000.S.P.2009.000.31500. 2009 Brevet hal-00578146v1

Laurent Fesquet

Présentation

Publications

Un projet de microélectronique numérique original : Contrôle autonome d'un micro-drone par caméras externes

Data-driven Pruning for Bundled-data Circuits

A Generic CDC Modeling for Data Stability Verification

Method for Data-Driven Pruning in Micropipeline Circuits

A High-Level Design Flow for Locally Body-Biased Asynchronous Circuits

Body-Bias Micro-Generators for Activity-Driven Power Management

From High-Level Synthesis to Bundled-Data Circuits

Comparison of Synchronous and Asynchronous FIR Filter Architecture

A Distributed Body-Biasing Strategy for Asynchronous Circuits

Desynchronizing Circuits Synthesized with CatapultC

Contrôle autonome d'un nano-drone par caméra externe

Model of a Simple yet effective Operational Amplifier

Vérification formelle

A Performance Comparison Between the SystemC-AMS Models of Computation

Formal Verification of C-element Circuits

C-elements for hardened self-timed circuits

A refinement process for top-down mixed-signal designs thanks to SystemC-AMS

Synthesis of Quasi Delay Insensitive Monitors

Does Asynchronous technology bring robustness in synchronous circuit monitoring?

Synthesis of asynchronous monitors for critical electronic systems

Delay Insensitivity Does Not Mean Slope Insensitivity!

RAT-based formal verification of QDI asynchronous controllers

Initiation à la conception de VLSI numériques

Asynchronous online monitoring of logical and temporal assertions

Asynchronous Assertion Monitors for multi-Clock Domain System Verification

Asynchronous on-line monitoring of PSL assertions

On-Line Assertion-Based Verification with Proven Correct Monitors

Asynchronous on-line monitoring of logical and temporal assertions

Logiciel