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Laurent Fesquet
4
Documents
Présentation
Maître de conférences
[Laboratoire TIMA](tima.imag.fr/ "Laboratoire TIMA")
Equipe [CDSI](http://tima.imag.fr/tima/en/cdsi/cdsioverview.html "équipe CDSI") (Design of Integrated devices, Circuits and Systems)
Associate Professor
[Laboratoire TIMA](tima.imag.fr/ "Laboratoire TIMA")
Team: [CDSI](http://tima.imag.fr/tima/en/cdsi/cdsioverview.html "équipe CDSI") (Design of Integrated devices, Circuits and Systems)
Publications
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Method for Data-Driven Pruning in Micropipeline Circuits31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), Oct 2023, Sharjah, United Arab Emirates
Communication dans un congrès
hal-04331953v1
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Data-driven Pruning for Bundled-data Circuits28th International Symposium on Asynchronous Circuits and Systems (ASYNC 2023, Jul 2023, Beijing, China
Communication dans un congrès
hal-04331929v1
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Body-Bias Micro-Generators for Activity-Driven Power ManagementFDSOI workshop at DATE Conference 2020, Mar 2020, Grenoble, France
Communication dans un congrès
hal-02956260v1
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A Distributed Body-Biasing Strategy for Asynchronous Circuits27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2019), Oct 2019, Cuzco, Peru
Communication dans un congrès
hal-02170157v1
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