Co-auteurs

Nombre de documents

196

Publications de Laurent FESQUET


Maître de conférences

Laboratoire TIMA

Equipe CDSI (Design of Integrated devices, Circuits and Systems)


Article dans une revue17 documents

  • O. Bonnaud, L. Fesquet. Innovation in Higher Education: specificity of the microelectronics field. 2016 31st Symposium On Microelectronics Technology and Devices (sbmicro), 2016. <hal-01479178>
  • O. Rolloff, R. Possamai Bastos, L. Fesquet. Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology. Microelectronics Reliability, Elsevier, 2015, 55 (9-10), pp. 1302-1306. <10.1016/j.microrel.2015.07.028>. <hal-01334697>
  • Sylvain Durand, Hatem Zakaria, Laurent Fesquet, Nicolas Marchand. A Robust and Energy-Efficient DVFS Control Algorithm for GALS-ANoC MPSoC in Advanced Technology under Process Variability Constraints . Advances in Computer Science : an International Journal, Tehran : Hossein Erfani, 2013-, 2014, 3 (1), pp.97-105. <hal-01141136>
  • S.-M. Qaisar, Laurent Fesquet, Marc Renaudin. Adaptive rate filtering a computationally efficient signal processing approach. Signal Processing, Elsevier, 2014, 94, pp.620-630. <10.1016/j.sigpro.2013.07.019>. <hal-01137857>
  • T. Beyrouthy, Laurent Fesquet. An asynchronous FPGA block with its tech-mapping algorithm dedicated to security applications. International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, 2013, 2013 (Article ID 517947), 12 p. <10.1155/2013/517947>. <hal-00819126>
  • H. Zakaria, Laurent Fesquet. Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, IEEE, 2011, 1 (2), pp.160 - 172. <10.1109/JETCAS.2011.2159284>. <hal-00646549>
  • Brigitte Bidégaray-Fesquet, Laurent Fesquet. Non-uniform Filter interpolation in the frequency domain. Sampling Theory in Signal and Image Processing, Sampling publishing, 2011, 10 (1-2), pp.17-35. <hal-00646536>
  • Laurent Fesquet, Brigitte Bidégaray-Fesquet. IIR digital filtering of non-uniformly sampled signals via state representation. International Journal of Signal Processing, World Enformatika Society, 2010, 90 (10), pp.2811-2821. <10.1016/j.sigpro.2010.03.030>. <hal-00493354>
  • S.-M. Qaisar, Laurent Fesquet, Marc Renaudin. Signal Driven Sampling and Filtering : A Promising Approach for Time Varying Signals Processing. International Journal of Signal Processing, World Enformatika Society, 2009, 5 (3), pp.189-197. <hal-00378813>
  • S.-M. Qaisar, Laurent Fesquet, Marc Renaudin. A Signal Driven Adaptive Resolution Short-Time Fourier Transform. International Journal of Signal Processing, World Enformatika Society, 2009, 5 (3), pp.180-188. <hal-00378808>
  • S.-M. Qaisar, Laurent Fesquet, Marc Renaudin. Adaptative Rate Sampling and Filtering based on level crossing sampling. Eurasip Advances in Signal Processing, 2009, Article ID 971656, 12 p. <10.1155/2009/971656>. <hal-00422320>
  • J. Hamon, Laurent Fesquet, B. Miscopein, Marc Renaudin. Constrained Asynchronous Ring Structures for Robust Digital Oscillators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2009, 17 (7), pp.907-919. <10.1109/TVLSI.2008.2011801>. <hal-00422313>
  • L. Fesquet, K. Morin-Allory, R. Robin. Un projet de microélectronique numérique original : Contrôle autonome d'un micro-drone par caméras externes. Journal sur l'enseignement des sciences et technologies de l'information et des systèmes, EDP Sciences, 2009, 14 (2009), pp.9. <10.1051/j3ea/2015021 >. <hal-01334687>
  • S.-M. Qaisar, Laurent Fesquet, Marc Renaudin. An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform. Research Letters in Signal Processing, 2008, 2008 (Article ID 932068), 5pp. <10.1155/2008/932068>. <hal-00288750>
  • E. Allier, Laurent Fesquet, Marc Renaudin, G. Sicard. Asynchronous level crossing analog to digital converters. Measurement, Elsevier, 2005, Volume 37, Issue 4 June, pp.296-309. <10.1016/j.measurement.2005.03.002>. <hal-00012072>
  • E. Allier, G. Sicard, L. Fesquet, M. Renaudin. A new type of Asynchronous Analog to Digital Interface. Measurement: Journal of the International Measurement Confederation, 2004, 35 (2). <hal-01457059>
  • L. Fesquet, M. Es Salhiene, Marc Renaudin. Asynchronous technology for energy reduction in embedded systems. Annals of Telecommunications - annales des télécommunications, Springer, 2004, 59 (7-8), pp.984-997. <hal-01334912>

Communication dans un congrès156 documents

  • Sophie Germain, Sylvain Engels, Laurent Fesquet. Event-Based Design Strategy for Circuit Electromagnetic Compatibility. 3rd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), May 2017, Funchal, Portugal. 2017. <hal-01514356>
  • Ali Skaf, Jean Simatic, Laurent Fesquet. Seeking Low-power Synchronous/Asynchronous Systems: A FIR Implementation Case Study. IEEE International Symposium on Circuits and Systems (ISCAS 2017), May 2017, Baltimore, MD, United States. 2017. <hal-01514224>
  • Amani Darwish, Hassan Abbas, Laurent Fesquet, Gilles Sicard. Event-driven Image Sensor Application: Event-driven Image Segmentation. 3rd International Conference on Event Based Control, Communication and Signal Processing (EBCCSP 2017), May 2017, Funchal, Portugal. <hal-01514221>
  • Saeed Mian Qaisar, Jean Simatic, Laurent Fesquet. High Level Synthesis of an Event-Driven Windowing Process. 3rd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), May 2017, Funchal, Portugal. 2017. <hal-01514220>
  • Jean Simatic, Abdelkarim Cherkaoui, Bertrand François, Rodrigo Possamai Bastos, Laurent Fesquet. A practical framework for specification, verification and design of self-timed pipelines. 23rd IEEE International Symposium on Asynchronous Circuits and Systems (Async 2017), May 2017, San Diego, CA, United States. IEEE, 2017. <hal-01512247>
  • J. Simatic, A. Cherkaoui, Fra. Bertrand, R. Possamai Bastos, L. Fesquet. A practical framework for specification, verification and design of self-timed pipelines. 23rd IEEE International Symposium on Asynchronous Circuits and Systems (Async'17), May 2017, San Diego, Ca, United States. IEEE. <hal-01524094>
  • Laurent Fesquet, Jean Simatic, Amani Darwish, Abdelkarim Cherkaoui. From events to data-driven processing. 3rd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), May 2017, Funchal, Portugal. 2017. <hal-01514219>
  • T. Ferreira de Paiva Leite, R. Possamai Bastos, L. Fesquet. QDI asynchronous circuits for low power applications: a comparative study in technology FD-SOI 28 nm. Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique (JNRDM'16), May 2016, Toulouse, France. <hal-01524092>
  • O. Rolloff, T. Ferreira de Paiva Leite, R. Possamai Bastos, L. Fesquet. Analysis of granularity for automatic biasing control in FDSOI technology with low-voltage supply. Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique (JNRDM'16), May 2016, Toulouse, France. <hal-01524090>
  • A. Ayres, O. Rozeau, B. Borot, L. Fesquet, M. Vinet. Delay partitioning helps reducing variability in 3DVLSI. 42nd European Solid-State Circuits Conference (ESSCIRC'16), Sep 2016, Lausanne, Switzerland. IEEE. <hal-01524088>
  • T. Ferreira de Paiva Leite, R. Possamai Bastos, R. Iga, L. Fesquet. Comparison of Low-Voltage Scaling in Synchronous and Asynchronous FD-SOI Circuits. 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'16), Sep 2016, Bremen, Germany. IEEE. <hal-01524087>
  • L. Acunha Guimaraes, R. Possamai Bastos, T. Ferreira de Paiva Leite, L. Fesquet. Simple Tri-State Logic Trojans Able to Upset Properties of Ring Oscillators. 11th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS'16), Apr 2016, Istanbul, Turkey. IEEE, pp.1-6. <hal-01431177>
  • L. Fesquet, A. Darwish, G. Sicard. Low-power Event-driven Image Sensor. First International Conference on Advances in Signal, Image and Video Processing (SIGNAL'16), Jun 2016, Lisbon, Portugal. Proceedings. <hal-01414772>
  • O. Bonnaud, L. Fesquet. Practice in microelectronics education as a mandatory supplement to the future digital-based pedagogy: strategy of the French national network. 11th European Workshop on Microelectronics Education (EWME'16), May 2016, Southampton, United Kingdom. IEEE, pp.1-6, Proceedings. <hal-01431205>
  • O. Bonnaud, L. Fesquet. MOOC and practices in electrical and information engineering: Complementary approaches. 15th International Conference on Information Technology Based Higher Education and Training, ITHET 2016, Sep 2016, Istanbul, Turkey. Institute of Electrical and Electronics Engineers Inc., 2016, <10.1109/ITHET.2016.7760732>. <hal-01484547>
  • O. Bonnaud, L. Fesquet. Practice in microelectronics education as a mandatory supplement to the future digital-based pedagogy: Strategy of the French national network. 11th European Workshop on Microelectronics Education, EWME 2016, May 2016, Grenoble, France. Institute of Electrical and Electronics Engineers Inc., pp.7496460, 2016, <10.1109/EWME.2016.7496460>. <hal-01368144>
  • Laurent Fesquet, J. Simatic, Amani Darwish, Abdelkarim Cherkaoui. Event-based design for mitigating energy in electronic systems. OAGM & ARW Joint Workshop on "Computer Vision and Robotics" , May 2016, Wels, Austria. 2016. <hal-01345715>
  • Laurent Fesquet, Amani Darwish, G. Sicard. Low-power event-driven image sensor. The First International Conference on Advances in Signal, Image and Video Processing (SIGNAL 2016), Jun 2016, Lisbon, Portugal. 2016. <hal-01345718>
  • J. Simatic, Abdelkarim Cherkaoui, Rodrigo Possamai Bastos, Laurent Fesquet. New asynchronous protocols for enhancing area and throughput in bundle-data pipelines. 29th Symposium on Integrated Circuits and Systems Design (SBCCI 2016), Aug 2016, Belo Horizonte, Brazil. <hal-01345749>
  • J. Simatic, Rodrigo Possamai Bastos, Laurent Fesquet. High-level synthesis for event-based systems. Second International Conference on Event-Based Control, Communications, and Signal Processing (EBCCSP 2016), Jun 2016, Krakow, Poland. <hal-01345745>
  • Taha Beyrouthy, Ahmed Roshdy, Mohammad Salman, Saeed Mian Qaisar, Laurent Fesquet. Asynchronous implementation of an event-driven adaptive filter. Second International Conference on Event-Based Control, Communications, and Signal Processing (EBCCSP 2016), Jun 2016, Krakow, Poland. <hal-01345748>
  • J. Simatic, Rodrigo Possamai Bastos, Laurent Fesquet. AHLS_DESYNC: A Desynchronization Tool For High-Level Synthesis of Asynchronous Circuits. Design, Automation and Test in Europe (DATE 2016), Mar 2016, Dresden, Germany. 2016. <hal-01293842>
  • Brigitte Bidégaray-Fesquet, Laurent Fesquet. Levels, peaks, slopes... which sampling for which purpose?. Second International Conference on Event-Based Control, Communications, and Signal Processing, Jun 2016, Krakow, Poland. IEEE, pp.1-6, 2016, <10.1109/EBCCSP.2016.7605261>. <hal-01324990>
  • A. Cherkaoui, Laurent Fesquet, V. Fischer, A. Aubert. A Self-timed Ring based True Random Number Generator with Monitoring and Entropy Assessment. University Booth at DATE 2015, Mar 2015, Grenoble, France. pp.session UB02.1, Proceedings. <hal-01166869>
  • Ch. Al Khatib, M. Gana, C. Aktouf, Laurent Fesquet. A new methodology for implementing a distributed clock management system for low-power design. Workshop on High Performance Embedded Systems (HiPEAC'15), Jan 2015, Amsterdam, Netherlands. 2015, Proceedings of Workshop on High Performance Embedded Systems (HiPEAC'15). <hal-01165604>
  • L. Acunha Guimaraes, R. Possamai Bastos, L. Fesquet. A New Proposition on Hardware Trojan Activation. Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM'15), May 2015, Bordeaux, France. <hal-01524097>
  • J. Simatic, R. Possamai Bastos, L. Fesquet. Flot de conception pour l'ultra-faible consommation : échantillonage non-uniforme et électronique asynchrone. Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM'15), May 2015, Bordeaux, France. <hal-01524095>
  • A. Ayres, O. Rozeau, B. Borot, L. Fesquet, G. Cibrario, et al.. Guidelines on 3D VLSI design regarding the intermediate BEOL process influence. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2015, Sonoma Valley, CA, United States. IEEE, pp.1-2, Proceedings. <hal-01393435>
  • C. Al Khatib, C. Aupetit, C. Chevalier, C. Aktouf, G. Sicard, et al.. A Generic Clock Controller for Low Power Systems: Experimentation on an AXI Bus. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'15) , Oct 2015, Daejeon, North Korea. IEEE, Proceedings. <hal-01393420>
  • T. Beyrouthy, L. Fesquet, B. Rolland. Data Sampling and Processing: Uniform vs. Non-Uniform Schemes. 1st IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP'15), Jun 2015, Krakow, Poland. IEEE, Proceedings. <hal-01393405>
  • A. Darwish, L. Fesquet, G. Sicard. RTL Simulation of an Asynchronous Reading Architecture for an Event-driven Image Sensor. 1st IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP'15), Jun 2015, Krakow, Poland. IEEE, Proceedings. <hal-01393402>
  • C. Arslan, J. Poujaud, L. Fesquet. A method to automatically determine the Level-Crossing thresholds in non-uniform sampling and Processing. 1st IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP'15), Jun 2015, Krakow, Poland. IEEE, Proceedings. <hal-01393400>
  • O. Rolloff, R. Possamai Bastos, L. Fesquet. Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology. 26th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'15), Oct 2015, Toulouse, France. IEEE, Proceedings. <hal-01393437>
  • L. Fesquet, A. Darwish, G. Sicard. Sampling circuits for 1D and 2D sensors for low-power purpose. 11th International Conference on Sampling Theory and Applications (SampTA'15), May 2015, Washington, DC, United States. IEEE Computer Society, pp.430-434, Proceedings. <hal-01187353>
  • O. Bonnaud, L. Fesquet. Towards multidisciplinarity for microelectronics education: a strategy of the French national network. International Conference on Microelectronic Systems Education (MSE'15) , May 2015, Pittsburgh, PA, United States. IEEE Computer Society, pp.1-4, Proceedings. <hal-01187288>
  • A. Darwish, L. Rocha, L. Fesquet, G. Sicard. Design of a Fully Asynchronous Image Sensor Reading. Conference on Design of Circuits and Integrated Systems (DCIS'15), Nov 2015, Estoril, Portugal. Academic Press, London, UK, Proceedings. <hal-01444993>
  • Amani Darwish, Leandro Rocha, Laurent Fesquet, G. Sicard. Design of a Fully Asynchronous Image Sensor Reading System. Conference on Design of Circuits and Integrated Systems (DCIS), Nov 2015, Estoril, Spain. IEEE, 2015, <10.1109/DCIS.2015.7388583>. <hal-01293867>
  • Amani Darwish, Laurent Fesquet, G. Sicard. RTL Simulation of an Asynchronous Reading Architecture for an Event-driven Image Sensor. 1st IEEE International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP), Jun 2015, Krakow, Poland. IEEE, <10.1109/EBCCSP.2015.7300666>. <hal-01293872>
  • Cansu Arslan, Julien Poujaud, L. Fesquet. A method to automatically determine the Level-Crossing thresholds in non-uniform sampling and Processing. 1st IEEE International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP), Jun 2015, Krakow, Poland. IEEE, 2015, <10.1109/EBCCSP.2015.7300663>. <hal-01293857>
  • Taha Beyrouthy, Laurent Fesquet, Robin Rolland. Data Sampling and Processing: Uniform vs. Non-Uniform Schemes. 1st IEEE International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP), Jun 2015, Krakow, Poland. IEEE, 2015, <10.1109/EBCCSP.2015.7300665>. <hal-01293879>
  • Jean Simatic, Laurent Fesquet, Brigitte Bidégaray-Fesquet. Correctly Sizing FIR Filter Architecture in the Framework of Non-uniform Sampling. 11th International Conference on Sampling Theory and Applications (SampTA'15), May 2015, Washington, DC, United States. IEEE Computer Society, pp.269-273, Proceedings. <10.1109/SAMPTA.2015.7148894>. <hal-01187290>
  • Olivier Bonnaud, Laurent Fesquet. Communicating and Smart Objects: multidisciplinary topics for the innovative education in microelectronics and its applications. ITHET 2015, Jun 2015, Lisbonne, Portugal. <hal-01126653>
  • Laurent Fesquet, K. Morin-Allory, R. Robin. Contrôle autonome d'un nano-drone par caméra externe. Journées pédagogiques du CNFM (JPCNFM), Nov 2014, Saint-Malo, France. Proceedings. <hal-01166159>
  • C. Al Khatib, C. Aupetit, A. Chagoya, C. Chevalier, G. Sicard, et al.. Distributed Asynchronous Controllers for Clock Management in Low Power Systems. 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14), Dec 2014, Marseille, France. IEEE Computer Society, pp.379-382, Proceedings. <hal-01132018>
  • G. Roa, T. Le Pelleter, A. Bonvilain, A. Chagoya, Laurent Fesquet. Designing ultra-low power systems with non-uniform sampling and event-driven logic. 27th Symposium on Integrated Circuits and Systems Design (SBCCI'14), Sep 2014, Aracaju, Sergipe, Brazil. IEEE Computer Society, pp.1-6, Proceedings. <hal-01131860>
  • A. Darwish, Laurent Fesquet, G. Sicard. 1-level Crossing Sampling Scheme for Low Data Rate Image Sensors. 12th IEEE International New Circuits and Systems Conference (NEWCAS'14), Jun 2014, Trois-Rivières, Canada. IEEE Computer Society, pp.289-292, Proceedings. <hal-01130645>
  • Olivier Bonnaud, Anne-Claire Salaun, Laurent Fesquet, A. Bsiesy. Improvement of doctoral studies in Electrical and Information Engineering through the High level courses in Europe. EAEEIE’14, May 2014, Cesmes, Turkey. <hal-01104831>
  • M. Faix, E. Mazer, Laurent Fesquet. An asynchronous CMOS probabilistic computer Idea. 20th International Symposium on Asynchronous Circuits and Systems (ASYNC), Fresh Idea Session, May 2014, Postdam, Germany. IEEE Computer Society, 2014, Proceedings. <hal-01061108>
  • A. Darwish, G. Sicard, Laurent Fesquet. Low data rate architecture for smart image sensor. Image Sensors and Imaging Systems, Feb 2014, San Francisco, California, United States. SPIE Int. Soc. Opt. Eng, pp.9022-5, 2014, Proceedings of IS&T/SPIE Vol. 9022. <hal-01060442>
  • Olivier Bonnaud, Laurent Fesquet. Trends in Nanoelectronic Education: From FDSOI and FinFET Technologies to Circuit Design Specifications. The 10th European Workshop on Microelectronics Education (EWME 2014), May 2014, Tallinn, Estonia. IEEE Computer Society, pp.106 - 111, 2014, Proceedings. <10.1109/EWME.2014.6877406>. <hal-01061123>
  • Laurent Fesquet, Abdelkarim Cherkaoui, Oussama Elissati. Self-timed rings as low-phase noise programmable oscillators. The 12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), Jun 2014, Trois-Rivières, Canada. 4 p., 2014. <ujm-01011287>
  • Laurent Fesquet, Tugdual Le Pelleter, Amani Darwish, Taha Beyrouthy, Brigitte Bidégaray-Fesquet. Mitigating the data-deluge by an adequate sampling for low-power systems. ICCHA5 - 5th International Conference on Computational Harmonic Analysis, May 2014, Nashville, United States. pp.17, Proceedings. <hal-01061132>
  • Olivier Bonnaud, Laurent Fesquet. A prospective on Education of New Generations of Devices in the FDSOI and FinFET Technologies: from the technological process to the Circuit Design Specifications. SBMicro'2014, Sep 2014, Aracaju, Brazil. <10.1109/SBMicro.2014.6940081>. <hal-01094543>
  • Olivier Bonnaud, Laurent Fesquet, Pascal Nouet, Tayeb Mohammed-Brahim. FINMINA: a French national project to promote Innovation in Higher Education in Microelectronics and Nanotechnologies. Information Technology Based Higher Education and Training ITHET 2014, Sep 2014, York, United Kingdom. <hal-01122242>
  • Olivier Bonnaud, Laurent Fesquet. Innovating projects as a pedagogical strategy for the French network for education in microelectronics and nanotechnologies. International Conference on Microelectronic Systems Education (MSE 2013), Jun 2013, Austin, Texas, United States. IEEE Computer Society, pp.5-8, 2013, <10.1109/MSE.2013.6566690>. <hal-00862833>
  • Olivier Bonnaud, Laurent Fesquet. The new strategy based on Innovative Projects in Microelectronics and Nanotechnologies. 28th Symposium on Microelectronics Technology and Devices (SBMicro 2013), Sep 2013, Curitiba, Brazil. 2013. <hal-00919993>
  • P. Sliwinski, L. Berezowski, P. Wachel, G. Sicard, Laurent Fesquet. Empirical recovery of input nonlinearity in distributed element models. 11th IFAC International Workshop on Adaptation and Learning in Control and Signal Processing (ALCOSP), Jul 2013, Caen, France. Paper ThS6T3.5, 2013. <hal-00862807>
  • Abdelkarim Cherkaoui, Viktor Fischer, Laurent Fesquet, Alain Aubert. A Very High Speed True Random Number Generator with Entropy Assessment. Cryptographic Hardware and Embedded Systems -- CHES 2013 15th International Workshop on Cryptographic Hardware and Embedded Systems -- CHES 2013, Aug 2013, Santa Barbara, California, United States. 8086, pp.179-196, 2013, Security and Cryptology. <ujm-00859906>
  • E. Yahya, Laurent Fesquet, Y. Ismail, Marc Renaudin. Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. 19th International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013, Santa Monica, United States. IEEE Computer Society, pp.67-74, 2013. <hal-00842226>
  • T. Le Pelleter, T. Beyrouthy, B. Rolland, A. Bonvilain, Laurent Fesquet. Non-uniform sampling pattern recognition based on atomic decomposition. 10th International Conference on Sampling Theory and Applications (SampTA 2013), Jul 2013, Bremen, Germany. IEEE Computer Society, 2013. <hal-00842215>
  • T. Le Pelleter, T. Beyrouthy, Y. Leroy, A. Bonvilain, R. Rolland, et al.. Low-power signal processing platform based on non-uniform sampling and event-driven circuitry. Design, Automation and Test in Europe (DATE'13), Mar 2013, Grenoble, France. 2013, University Booth. <hal-00841614>
  • Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet. A Self-timed Ring Based True Random Number Generator. International symposium on advanced research in asynchronous circuits and systems - ASYNC 2013, May 2013, Santa Monica - California, United States. pp.99-106, 2013. <ujm-00840593>
  • Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet. True Random Numbers Generation Using Asynchronous Circuits. Journées scientifiques SEmba 2013, May 2013, St Germain au Mont d'Or, France. <ujm-00840445>
  • E. Excoffon, F. Papillon, Laurent Fesquet, Ah. Bsiesy, Olivier Bonnaud. New pedagogical experiment leading to awareness in nanosciences and nanotechnologies for young generations at secondary school. International Conference on Information Technology Based Higher Education and Training (ITHET'12), Jun 2012, Istanbul, Turkey. IEEE Computer Society, pp.1-4, 2012, <10.1109/ITHET.2012.6246049>. <hal-00747415>
  • Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet. Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs. Design Automation and Test in Europe (DATE 2012), Mar 2012, Dresden, Germany. pp.1-6, 2012. <ujm-00667639>
  • E. Yahya, Laurent Fesquet, Marc Renaudin. Asynchronous circuit performance analysis, fundamentals and efficient tools. 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012, Copenhagen, Denmark. IEEE Computer Society, 2012. <hal-00749396>
  • T. Le Pelleter, A. Bonvilain, Laurent Fesquet. Méthode à faible coût de calcul et robuste pour la détection d'un motif dans un signal. 15ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'12), Jun 2012, Marseille, France. pp.Oral 1-04, 2012. <hal-00749388>
  • A. Cherkaoui, V. Fischer, A. Aubert, Laurent Fesquet. Self-Timed Rings as Sources of Entropy. 6ème colloque du GDR SOC-SIP du CNRS, Jun 2012, Paris, France. 2012. <hal-00747474>
  • A. Cherkaoui, Laurent Fesquet, V. Fischer, A. Aubert. Self-Timed Rings as Entropy Sources. 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012, Copenhagen, Denmark. 2012. <hal-00747383>
  • Laurent Fesquet. Controling variability and energy by design. CMOS Emerging Technologies, Jul 2012, Vancouver, BC, Canada. 2012. <hal-00747376>
  • F. Paugnat, Laurent Fesquet, K. Morin-Allory. Model of a Simple yet effective Operational Amplifier. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'12), Sep 2012, Seville, Spain. IEEE Computer Society, Proceedings/Catalog number: CFP1210S-CDR, pp.165-168, 2012, <10.1109/SMACD.2012.6339443>. <hal-00746450>
  • Abdelkarim Cherkaoui, Viktor Fischer, Laurent Fesquet, Alain Aubert. A New Robust True Random Numbers Generator Using Self-Timed Rings. Cryptographic architectures embedded in reconfigurable devices - Cryptarchi 2012, Jun 2012, Saint-Etienne, France. <ujm-00712552>
  • K. Morin-Allory, L. Fesquet. Vérification formelle. 12èmes Journées Pédagogiques de la Coordination Nationale pour la Formation en Micro et nanoélectronique (JPCNFM’12), Nov 2012, Saint-Malo, France. <hal-01413187>
  • Laurent Fesquet. Thinking and Designing Differently: The Asynchronous Alternative. Dresden Microelectronic Academy, Sep 2011, Dresden, Germany. 2011. <hal-00671323>
  • Abdelkarim Cherkaoui, Alain Aubert, Viktor Fischer, Laurent Fesquet. Asynchronous Self-Timed Rings for Randomness Generation. International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2011, bochum, Germany. <ujm-00667827>
  • F. Paugnat, L. Bousquet, K. Morin-Allory, Laurent Fesquet. A Performance Comparison Between the SystemC-AMS Models of Computation. edaWorkshop, May 2011, Dresden, Germany. EDA Publishing Association - CMP, Grenoble, France, pp.13-18, 2011. <hal-00652944>
  • F. Ouchet, Katell Morin-Allory, Laurent Fesquet. C-elements for hardened self-timed circuits. José L. Ayala, Braulio García-Cámara, Manuel Prieto, Martino Ruggiero and Gilles Sicard. 21st International Workshop on Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS'11), Sep 2011, Madrid, Spain. springer, 6951, pp.247-256, 2011, Lecture Notes in Computer Science. <10.1007/978-3-642-24154-3_25>. <hal-00652365>
  • A. Porcher, K. Morin-Allory, Laurent Fesquet. Does Asynchronous technology bring robustness in synchronous circuit monitoring?. Forum on specification & Design Languages (FDL'11), Sep 2011, Oldenburg, Germany. ESCI, 2011. <hal-00646699>
  • N. Leblond, A. Porcher, Laurent Fesquet. Tiempo Asynchronous Design Flow Tutorial - Modeling and Debug. Design Automation Conference (DAC'11), Jun 2011, San Diego, United States. <hal-00646693>
  • A. Porcher, K. Morin-Allory, Laurent Fesquet. Synthesis of Quasi Delay Insensitive Monitors. 7th Conference on PhD Research in Microelectronics and Electronics (PRIME'11), Jul 2011, Madonna Di Campiglio (Trento), Italy. IEEE Computer Society, pp.225 - 228, 2011, <10.1109/PRIME.2011.5966274>. <hal-00646662>
  • F. Paugnat, K. Morin-Allory, Laurent Fesquet. A refinement process for top-down mixed-signal designs thanks to SystemC-AMS. IEEE 9th International New Circuits and Systems Conference (NEWCAS), Jun 2011, Bordeaux, France. IEEE Computer Society, pp.378 - 381, 2011, <10.1109/NEWCAS.2011.5981249>. <hal-00646654>
  • J. Hamon, Laurent Fesquet. Configurable Self-Timed Ring Oscillators. 9th IEEE International NEWCAS Conference, Jun 2011, Bordeaux, France. IEEE Computer Society, pp.249 - 252, 2011, <10.1109/NEWCAS.2011.5981302>. <hal-00646646>
  • K. Alsayeg, Laurent Fesquet, G. Sicard, Marc Renaudin. A modular synthesis method for low-power QDI state machines. 9th IEEE International NEWCAS Conference, Jun 2011, Bordeaux, France. IEEE Computer Society, pp.185 - 188, 2011, <10.1109/NEWCAS.2011.5981286>. <hal-00646564>
  • O. Elissati, S. Rieubon, Laurent Fesquet. Ring Oscillators : The Asynchronous Alternative. 10th Edition of Faible Tension Faible Consommation (FTFC'11), May 2011, Marrakech, Morocco. IEEE Computer Society, pp.34-37, 2011, <10.1109/FTFC.2011.5948910>. <hal-00646552>
  • H. Zakaria, Laurent Fesquet. Process variability robust energy-efficient control for nano-scaled complex SoCs. 10th Edition of Faible Tension Faible Consommation (FTFC'11), May 2011, Marrakech, Morocco. IEEE Computer Society, pp.95 - 98, 2011, <10.1109/FTFC.2011.5948928>. <hal-00646301>
  • T. Beyrouthy, Laurent Fesquet. An event-driven FIR filter: Design and implementation. 22nd IEEE International Symposium on Rapid System Prototyping (RSP'11), May 2011, Karlsruhe, Germany. IEEE Computer Society, pp.59 - 65, 2011, <10.1109/RSP.2011.5929976>. <hal-00646298>
  • F. Paugnat, L. Bousquet, Laurent Fesquet. Analog Design Abstraction Levels and SystemC AMS Models of Computation. SystemC-AMS Day 2011: Industry Adoption of the SystemC AMS Standard, May 2011, Dresden, Germany. 2011. <hal-00646292>
  • M. Greitans, R. Shavelis, Laurent Fesquet, T. Beyrouthy. Combined Peak and Level-Crossing Sampling Scheme. 9th International Conference on Sampling Theory and Applications (SampTA'11), May 2011, Singapore, Singapore. pp.Fr2S12.1 - P0158, 2011. <hal-00646274>
  • T. Beyrouthy, Laurent Fesquet, M. Greitans, R. Shavelis, R. Robin. An Asynchronous FIR Filter Architecture coupled to a Level-Crossing ADC. 9th International Conference on Sampling Theory and Applications (SampTA'11), May 2011, Singapore, Singapore. pp.Fr2S12.2 - P0190, 2011. <hal-00646262>
  • C. Yan, Laurent Fesquet, F. Ouchet, K. Morin-Allory. Formal Verification of C-element Circuits. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'11), Apr 2011, Ithaca (NY), United States. IEEE, pp.55 - 64, 2011, <10.1109/ASYNC.2011.14>. <hal-00624249>
  • Brigitte Bidégaray-Fesquet, Laurent Fesquet. Non-Uniform Filter Design in the Log-Scale. SampTA'11- 9th International Conference on Sampling Theory and Applications, May 2011, Singapore, Singapore. pp.art. 150, 2011. <hal-00646287>
  • O. Elissati, S. Rieubon, E. Yahya, Laurent Fesquet. Self-Timed Rings: A Promising Solution for Generating High-Speed High Resolution Low-Phase Noise Clocks. José L. Ayala; David Atienza Alonso; Ricardo Reis. 18th International Conference on Very Large Scale Integration (VLSISOC), Sep 2010, Madrid, Spain. Springer, IFIP Advances in Information and Communication Technology, AICT-373, pp.22-42, 2012, VLSI-SoC: Forward-Looking Trends in IC and Systems Design. <10.1007/978-3-642-28566-0_2>. <hal-00750195>
  • Vincent Fristot, Sylvain Huet, Laurent Fesquet, Robin Rolland. Conception conjointe logiciel-matériel et microprocesseur embarqué, validation sur plateforme FPGA. 8ème Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes (CETSIS 2010), Mar 2010, Grenoble, France. Actes du 8ème Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes (CETSIS 2010), pp.n.c., 2010. <hal-00505110>
  • O. Elissati, E. Yahya, S. Rieubon, Laurent Fesquet. Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case. International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2010), Sep 2010, Grenoble, France. Springer, 2010. <hal-00569495>
  • F. Ouchet, K. Morin-Allory, Laurent Fesquet. Delay Insensitivity Does Not Mean Slope Insensitivity!. IEEE Symposium on Asynchronous Circuits and Systems (ASYNC'10), May 2010, Grenoble, France. IEEE Computer Society, pp.176 - 184, 2010, <10.1109/ASYNC.2010.27>. <hal-00492923>
  • O. Elissati, E. Yahya, Laurent Fesquet, S. Rieubon. A novel High-Speed Multi-Phase Oscillator on Asynchronous Rings. IEEE International Conference on Microelectronics ICM'2010, Dec 2010, Cairo, Egypt. 2010. <hal-00556662>
  • O. Elissati, E. Yahya, S. Rieubon, Laurent Fesquet. A High-Speed High-Resolution Low-Phase Noise Oscillator Using Self-Timed Rings. 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), Sep 2010, Madrid, Spain. IEEE Computer Society, pp.173-178, 2010. <hal-00547400>
  • A. Porcher, K. Morin-Allory, Laurent Fesquet. Synthesis of asynchronous monitors for critical electronic systems. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'10), Apr 2010, Vienna, Austria. IEEE Computer Society, pp.329 - 334, 2010, <10.1109/DDECS.2010.5491756>. <hal-00517676>
  • Laurent Fesquet, Gilles Sicard, Brigitte Bidégaray-Fesquet. Targeting ultra-low power consumption with non-uniform sampling and filtering. ISCAS'10 - IEEE International Symposium on Circuits and Systems, May 2010, Paris, France. IEEE Computer Society, pp.3585-3588, 2010, <10.1109/ISCAS.2010.5537804>. <hal-00517684>
  • E. Yahya, Laurent Fesquet. Asynchronous Design: A Promising Paradigm for Electronic Circuits and Systems. IEEE International Conference on Electronics and Systems (ICECS'09), Dec 2009, Hammamet, Tunisia. IEEE Computer Society, pp.339 - 342, 2009, Proceedings. <10.1109/ICECS.2009.5411009>. <hal-00472069>
  • S. Guilley, S. Chaudhuri, L. Sauvage, J.-L. Danger, T. Beyrouthy, et al.. Updates on the Potential of Clock-Less Logics to Strengthen Cryptographic Circuits against Side-Channel Attacks. IEEE International Conference on Electronics and Systems (ICECS'09), Dec 2009, Hammamet, Tunisia. IEEE Computer Society, pp.351 - 354, 2009, Proceedings. <10.1109/ICECS.2009.5411008>. <hal-00472064>
  • K. Alsayeg, K. Morin-Allory, Laurent Fesquet. RAT-based formal verification of QDI asynchronous controllers. Forum on specifications and Design Languages (FDL'09), Sep 2009, Nice, Sophia Antipolis, France. IEEE Computer Society, pp.1-6, 2009, Proceedings. <hal-00471574>
  • Laurent Fesquet, H. Zakaria. Controlling Energy and Process Variability in System-on-Chips: needs for control theory. 3rd IEEE Multi-conference on Systems and Control (MSC'09), Jul 2009, Saint Petersburg, Russia. IEEE Computer Society, pp.302-307, 2009, IEEE Catalog Number: CFP09CCA-CDR. <hal-00422305>
  • K. Alsayeg, Laurent Fesquet, G. Sicard, D. Rios, Marc Renaudin. Direct mapping of sequential QDI controllers. DATE 2009, Ph D Forum poster, Apr 2009, Nice, France. <hal-00422286>
  • T. Beyrouthy, Laurent Fesquet. DPA robust S-BOX implementation on a secure asynchronous FPGA. Cryptarchi Conference, Czech republic, June 24-27, Jun 2009, Prague, Czech Republic. <hal-00422280>
  • Laurent Fesquet, T. Beyrouthy. A secure asynchronous FPGA for an embedded system. PhD Forum DATE, Apr 2009, Nice, France. <hal-00416804>
  • K. Alsayeg, Laurent Fesquet, G. Sicard, D. Rios, Marc Renaudin. Optimizing speed and consumption of QDI controllers using direct mapping synthesis. Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA'09), Jun 2009, Toulouse, France. IEEE Computer Society, pp.151-154, 2009, Proceedings IEEE Catalog Number: CFP09NEW-USB. <hal-00421682>
  • O. Elissati, E. Yahya, Laurent Fesquet, S. Rieubon. Oscillation Period and Power Consumption in Configurable Self-Timed Rings Oscillators. Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA ConferenceIEEE NEWCAS-TAISA Conference, Jun 2009, Toulouse, France. IEEE Computer Society, pp.131-134, 2009, <10.1109/NEWCAS.2009.5290439>. <hal-00418905>
  • E. Yahya, O. Elissati, H. Zakaria, Laurent Fesquet, Marc Renaudin. Programmable/Stoppable Oscillator Based on Self-Timed Rings. 15th IEEE Symposium on Asynchronous Circuits and Systems (ASYNC '09), May 2009, UNC Chapel Hill, United States. IEEE Computer Society, pp.3-12, 2009, <10.1109/ASYNC.2009.12>. <hal-00417834>
  • Brigitte Bidégaray-Fesquet, Laurent Fesquet. A fully nonuniform approach to FIR filtering. Laurent Fesquet and Bruno Torrésani. SAMPTA'09 - International Conference on Sampling Theory and Applications, May 2009, Marseille, France. pp.129: 1-4, 2009. <hal-00453350>
  • Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin. Effective Resolution of an Adaptive Rate ADC. Laurent Fesquet and Bruno Torrésani. SAMPTA'09, May 2009, Marseille, France. Special session on sampling and industrial applications, 2009. <hal-00451847>
  • H. Zakaria, Laurent Fesquet, S. Durand, Carolina Albea, Y. Thonnard, et al.. Integrated Asynchronous Regulation for Nanometric Technologies: Application to an Embedded Parallel System. MINATEC CROSSROADS'08, Jun 2008, Grenoble, France. <hal-00561636>
  • L. Anghel, Laurent Fesquet, K. Morin-Allory. Initiation à la conception de VLSI numériques. 10èmes journées pédagogiques CNFM, Nov 2008, Saint-Malo, France. <hal-00385508>
  • Laurent Fesquet, T. Beyrouthy. A secure asynchronous configurable cell: an embedded programmable logic for smartcards. Workshop on Cryptographic Architectures embedded in reconfigurable devices (CryptArchi'08), Jun 2008, Tregastel, France. <hal-00293681>
  • J. Hamon, B. Miscopein, J. Schwoerer, Laurent Fesquet, Marc Renaudin. Implémentation en logique asynchrone d'un algorithme de synchronisation de signaux radio impulsionnelle. 7ème journées d'études Faible Tension Faible Consommation, (FTFC'08), May 2008, Louvain, Belgique. <hal-00291826>
  • J. Hamon, Laurent Fesquet, B. Miscopein, Marc Renaudin. High-level time-accurate model for the design of self-timed ring oscillators. 14th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'08), Apr 2008, Newcastle upon Tyne, United Kingdom. IEEE Computer Society, pp.29-38, 2008. <hal-00288379>
  • J. Hamon, B. Miscopein, J. Schwoerer, Laurent Fesquet, Marc Renaudin. Self-Timed Implementation of an Impulse Radio Synchronisation Acquisition Algorithm. Conference on Design and Architectures for Signal and Image Processing (DASIP'08), Nov 2008, Bruxelles, Belgium. 2008. <hal-00354345>
  • K. Alsayeg, Laurent Fesquet, G. Sicard, D. Rios, Marc Renaudin. Synthesis of asynchronous QDI FSM based on optimized sequencers. 34th European Conference on Solid-States Circuits (ESSCIRC'08), ESS Fringe Poster Session, Sep 2008, Edinburgh, United Kingdom. IEEE Computer Society, 2008, ESS Fringe Poster Session. <hal-00354513>
  • T. Beyrouthy, Laurent Fesquet, Alin Razafindraibe, S. Chaudhuri, S. Guilley, et al.. A Secure Programmable Architecture with a Dedicated Tech-mapping Algorithm: Application to a Crypto-Processor. 23rd International Conference on Design of Circuits and Integrated Systems (DCIS'08), Nov 2008, Grenoble, France. pp.session 3b3, 2008. <hal-00346734>
  • S.-M. Qaisar, Laurent Fesquet, Marc Renaudin. Computationally Efficient Adaptive Rate Sampling and Adaptive Resolution Analysis. Computer Vision, Image and Signal Processing (CVISP'08), Jul 2008, Prague, Czech Republic. WORLD ACADEMY OF SCIENCE, ENGINEERING AND TECHNOLOGY, VOLUME 31, JULY (ISSN: 2070-3740), pp.85-90, 2008. <hal-00323944>
  • S.-M. Qaisar, Laurent Fesquet, Marc Renaudin. An Improved Quality Adaptative Rate Filtering Technique Based on the Level Crossing Sampling. Computer Vision, Image and Signal Processing (CVISP'08), Jul 2008, Prague, Czech Republic. WORLD ACADEMY OF SCIENCE, ENGINEERING AND TECHNOLOGY, VOLUME 31, JULY, pp.79-84, 2008, ISSN: 2070-3740. <10.1109/ICSES.2008.4673436>. <hal-00323939>
  • S.-M. Qaisar, Laurent Fesquet, Marc Renaudin. An improved quality filtering technique for time varying signals based on the level crossing sampling. International Conference of Signals and Electronic Systems 2008 (ICSES'08), Sep 2008, Krakow, Poland. IEEE Ciurcuits and Systems, pp.355-358, 2008. <hal-00327665>
  • S.-M. Qaisar, Laurent Fesquet, Marc Renaudin. Computationally Efficient Adaptive Rate Sampling and Filtering. 15th European Signal Processing Conference (EUSIPCO'07), Sep 2007, Poznan, Poland. EURASIP, pp.2139-2143, 2007. <hal-00178982>
  • T. Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin. Secure Asynchronous FPGA for Embedded Systems (SAFE). Colloque Journées GDR SOC-SIP'07, Paris, France, June 13-15, Jun 2007, Paris, France. 2007. <hal-00178955>
  • S.-M. Qaisar, Laurent Fesquet, Marc Renaudin. Adaptive Rate Sampling and Filtering for Low Power Embedded Systems. International Workshop on Sampling Theory and Applications (SampTA'07), Jun 2007, Thessaloniki, Greece. 2007. <hal-00174475>
  • S.-M. Qaisar, Laurent Fesquet, Marc Renaudin. Adaptive Rate Filtering for a Signal Driven Sampling Scheme. 32nd IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP'07), Apr 2007, Honolulu, Hawaï, United States. IEEE Computer Society, Vol. III, pp.1465 - 1468, 2007, ISBN : 1-4244-0728-1. <10.1109/ICASSP.2007.367124>. <hal-00174460>
  • K. Morin-Allory, Laurent Fesquet, D. Borrione. Asynchronous online monitoring of logical and temporal assertions. 10th Forum on Specification and Design Languages (FDL'07), Sep 2007, Barcelona, Spain. ESCI, 2007. <hal-00222895>
  • Philippe Hoogvorst, Sylvain Guilley, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet. A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. RecoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jun 2007, Montpellier, France. Univ. Montpellier II, France, 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007, pp.15-22, 2007, ISBN : 2-9517461-3-X. <hal-00222887>
  • T. Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin. A novel asynchronous e-FPGA architecture for security applications. Hideharu Amano, Takeshi Ikenaga. International Conference on Field-Programmable Technology (ICFPT'07), Dec 2007, Kokurakita, Kitakyushu, Japan. Library of congress :2007930580, pp.369-372, 2007. <hal-00222875>
  • K. Morin-Allory, Laurent Fesquet, D. Borrione. Asynchronous Assertion Monitors for multi-Clock Domain System Verification. 2006, IEEE Computer Society, pp.98- 102, 2006, <10.1109/RSP.2006.9>. <hal-00134475>
  • S.-M. Qaisar, Laurent Fesquet, Marc Renaudin. Spectral analysis of a signal driven sampling scheme. 2006, EURASIP, 5 p., 2006. <hal-00130550>
  • K. Morin-Allory, Laurent Fesquet, D. Borrione. Asynchronous on-line monitoring of PSL assertions. 2006, IEEE Computer Society, pp.98 102, 2006, <10.1109/RSP.2006.9>. <hal-00130525>
  • Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin. State-holding in Look-Up Tables: application to asynchronous logic. 2006, IFIP, pp.12-18, 2006. <hal-00130402>
  • D. Borrione, Z.W. Liu, K. Morin-Allory, P. Ostier, Laurent Fesquet. On-Line Assertion-Based Verification with Proven Correct Monitors. 3rd IEEE International Conference on Information and Communication Technology (ICICT'05), December 5-6, 2005, 2005, cairo, Egypt. IEEE, pp.123-143, 2005. <hal-00078798>
  • N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin. FPGA Architecture for Multi-Style Asynchronous Logic. EDAA - European design and Automation Association. DATE'05, Mar 2005, Munich, Germany. 1, pp.32-33, 2005. <hal-00181491>
  • Marc Renaudin, Ghislain Bouesse, Y. Monnet, Laurent Fesquet. Secure asynchronous circuits design and prototyping. 3rd International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi'05), Jun 2005, Saint-Etienne, France. <hal-00540339>
  • Laurent Fesquet, J. Quartana, Marc Renaudin, S. Renane, A. Baixas. Gals systems prototyping using multiclock fpgas and asynchronous network-on-chips. Field Programmable Logic and Applications, 2005. International Conference on, 2005, Tampere, Finland. IEEE, pp.299-304, 2005. <hal-00012722>
  • Laurent Fesquet, J. Quartana, Marc Renaudin. Asynchronous Systems on Programmable Logic. 2005, LIRMM & TU Darmstadt, pp.105-112, 2005. <hal-00105236>
  • Laurent Fesquet, Marc Renaudin. A programmable logic architecture for prototyping clockless circuits. 2005, IEEE, pp.293- 298, 2005, <10.1109/FPL.2005.1515737>. <hal-00104360>
  • J. Quartana, Laurent Fesquet, Marc Renaudin. Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. 2005, IFIP, pp.397-402, 2005. <hal-00104233>
  • D. Borrione, M. Liu, P. Ostier, Laurent Fesquet. PSL-based online monitoring of digital systems. 2005, EPFL, Lausanne, pp.465-478, 2005. <hal-00103450>
  • Bertrand Folco, V. Bregier, Laurent Fesquet, Marc Renaudin. Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. 15th IFIP Int. Conf. on Very Large Scale Integration Systems (VLSI-SoC'05), October 17-19, 2005, Perth, France. IFIP, pp.146-151, 2005. <hal-00101464>
  • N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin. FPGA architecture for multi-style asynchronous logic [full-adder example]. Design, Automation and Test in Europe, 2005. Proceedings, 2005, Los Alamitos, CA, United States. IEEE, pp.32 - 33 Vol. 1, 2005, <10.1109/DATE.2005.15>. <hal-00009568>
  • F. Aeschlimann, E. Allier, L. Fesquet, M. Renaudin. Spectral analysis of level crossing sampling scheme. International Workshop on Sampling theory and application (SAMPTA'05), Jul 2005, Samsun, Turkey. <hal-01393272>
  • F. Aeschlimann, E. Allier, Laurent Fesquet, Marc Renaudin. Asynchronous FIR filters: towards a new digital processing chain. Asynchronous Circuits and Systems, 2004. Proceedings. 10th International Symposium on, 2004, Crete, Greece. IEEE, pp.198-206, 2004, BOOK NUMBER: 0769521339. <10.1109/ASYNC.2004.1299302>. <hal-00009570>
  • V. Bregier, Bertrand Folco, L. Fesquet, M. Renaudin. Modeling and synthesis of multi-rail multi-protocol QDI circuits. Thirteenth International Workshop on Logic and Synthesis, Temecula Creek (IWLS'04), Jun 2004, Temecula, California, États-Unis. Proceedings. <hal-01384270>
  • E. Allier, G. Sicard, Laurent Fesquet, Marc Renaudin. A new class of asynchronous A/D converters based on time quantization. Proceedings-Ninth-International-Symposium-on-Asynchronous-Circuits-and-Systems, 2003, Vancouver, BC, Canada. IEEE, pp.196-205, 2003, BOOK NUMBER: 0769518982. <10.1109/ASYNC.2003.1199179>. <hal-00009583>
  • G. Sicard, M. Renaudin, E. Allier, L. Fesquet. Asynchronous ADCs: Design Methodology and Case study. 8th International Workshop on ADC modelling and testing (IWADC'03), Sep 2003, Perugia, Italie. pp.29-32. <hal-01391655>
  • K. Slimani, A. Sirianni, L. Fesquet, Y. Remond, G. Sicard, et al.. Estimation et optimisation de la consommation d'énergie des circuits asynchrones. 4èmes journées d'études Faible Tension, Faible Consommation (FTFC'03), May 2003, Paris, France. pp.59-64, Proceedings. <hal-01377243>
  • G. Sicard, Marc Renaudin, E. Allier, L. Fesquet. Conversion analogique-numérique faible consommation : conception asynchrone et echantillonnage irrégulier. 4ème Colloque sur le Traitement Analogique de l'Information, du Signal, et ses Applications (TAISA'03), Sep 2003, Louvain-La-Neuve, Belgique. pp.53-56. <hal-01376269>
  • Jean-Baptiste Rigaud, J. Quartana, Laurent Fesquet, Marc Renaudin. High-level modeling and design of asynchronous arbiters for on-chip communication systems. Proceedings-2002-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition., 2002, Paris, France. IEEE, pp.1090, 2002, <10.1109/DATE.2002.998447>. <hal-00009606>
  • E. Allier, Laurent Fesquet, Marc Renaudin, G. Sicard. Low-power asynchronous A/D conversion. Integrated-Circuit-Design.-Power-and-Timing-Modeling,-Optimization-and-Simulation.-12th-International-Workshop,-PATMOS-2002.-Proceedings-Lecture-Notes-in-Computer-Science, 2002, Séville, Spain. Springer Verlag, pp.81-91, 2002, Vol.2451. <hal-00009604>
  • M.E. Salhiene, Laurent Fesquet, Marc Renaudin. Dynamic voltage scheduling for real time asynchronous systems. Integrated-Circuit-Design.-Power-and-Timing-Modeling,-Optimization-and-Simulation.-12th-International-Workshop,-PATMOS-2002.-Proceedings-Lecture-Notes-in-Computer-Science-, 2002, Séville, Spain. Springer Verlag, pp.390-9, 2002, Vol.2451. <hal-00009603>
  • Quoc Thai-Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, R. Rolland. Implementing asynchronous circuits on LUT based FPGAs. Field-Programmable-Logic-and-Applications.-Reconfigurable-Computing-Is-Going-Mainstream.-12th-International-Conference,-FPL-2002.-Proceedings-Lecture-Notes-in-Computer-Science-Vol.2438., 2002, Montpellier, France. Springer Verlag, pp.36-46, 2002. <hal-00009602>
  • L. Fesquet, Anh Vu Dinh Duc, M. Renaudin. Synthesis of QDI asynchronous circuits from DTL-style petri-net. 11th IEEE/ACM International Workshop on Logic & Synthesis (IWLS'02), Jun 2002, New Orleans, Louisiana, États-Unis. IEEE. <hal-01391638>
  • L. Fesquet, Marc Renaudin, Jean-Baptiste Rigaud, J. Quartana. Modeling and design of asynchronous priority arbiters for on-chip communication systems. IFIP International Conference On Very Large Scale Integration (VLSI-SOC'01), Dec 2001, Montpellier, France. Kluwer Academic Publishers, pp.313-324, Procedings No. 7426634. <hal-00009605>

Poster1 document

  • Olivier Bonnaud, Laurent Fesquet. Les technologies du futur: FDSOI et FinFET. Conseil d'orientation 2013 du GIP-CNFM, Jan 2014, Paris, France. <hal-01094646>

Ouvrage (y compris édition critique et traduction)2 documents

  • Laurent Fesquet, B. Torrésani. Sampling Theory in Signal and Image Processing. Sampling Publishing ISSN: 1530-6429, pp.Vol. 10, N°1-2, 2011, Special Issue on 8th International Conference on Sampling Theory and Applications (SampTA'09, May 18-22, 2009 in Marseille). <hal-00688417>
  • Laurent Fesquet, Bruno Torrésani. SAMPTA'09, International Conference on SAMPling Theory and Applications. Laurent Fesquet and Bruno Torrésani. pp.384, 2010. <hal-00495456>

Chapitre d'ouvrage12 documents

  • L. Fesquet, B. Bidegaray-Fesquet. Digital Filtering with non-uniformly sampled data: from the algorithm to the implementation. Event-Based Control and Signal Processing, crc press, 2015, 9781482256550. <hal-01469207>
  • Laurent Fesquet, Brigitte Bidégaray-Fesquet. Digital Filtering with Nonuniformly Sampled Data: From the Algorithm to the Implementation. Marek Miskowicz. Event-Based Control and Signal Processing, CRC Press, 2015, 9781482256550. <https://www.crcpress.com/Event-Based-Control-and-Signal-Processing/Miskowicz/9781482256550>. <hal-01228969>
  • H. Zakaria, E. Yahya, Laurent Fesquet. Self Adaption in SoCs. Phan Cong-Vinh. Autonomic Networking-on-Chip (Bio-inspired Specification, Development, and Verification), c, 287 p., 2011, Series: Embedded Multi-Core Systems. <hal-00653931>
  • O. Elissati, E. Yahya, Laurent Fesquet, S. Rieubon. Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case. Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Springer, pp.137-149, 2010, Lecture Notes in Computer Science, Vol. 6448. <hal-00564558>
  • S. Chaudhuri, S. Guilley, P. Hoogvorst, J.-L. Danger, T. Beyrouthy, et al.. Physical Design of FPGA Interconnect to Prevent Information Leakage. Woods, R.; Compton, K.; Bourganis, C.; Diniz, P.C. Reconfigurable Computing: Architecture, Tools, and Applications, Springer, pp.87-98, 2008, Lecture Notes in Computer Science Vol. 4943, <10.1007/978-3-540-78610-8>. <hal-00299487>
  • K. Morin-Allory, Laurent Fesquet, B. Roustan, D. Borrione. Asynchronous online monitoring of logical and temporal assertions. Villar Eugenio. Embedded Systems Specification and Design Languages: Selected Contributions from FDL'07, Springer, 278p, 2008, Lecture Notes in Electrical Engineering, Vol. 10. <hal-00293779>
  • J. Quartana, Laurent Fesquet, Marc Renaudin. Modular asynchronous Network-on-Chip: application to GALS systems rapid prototyping. VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005), Springer, pp.195-207, 2007, IFIP International Federation for Information Processing, <10.1007/978-0-387-73661-7_13>. <hal-00192008>
  • Bertrand Folco, V. Brégier, Laurent Fesquet, Marc Renaudin. Technology mapping for area optimized quasi delay insensitive circuits. Reis, Ricardo; Osseiran, Adam; Pfleiderer, Hans-Joerg. VLSI-SOC: From Systems to Silicon, Springer, pp.55-69, Vol. 240, 2007, Collection :: IFIP International Federation for Information Processing, <10.1007/978-0-387-73661-7_5>. <hal-00185940>
  • Jérôme Quartana, Laurent Fesquet, Marc Renaudin. VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005). VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005), Springer, pp.195-207, 2007. <emse-00429856>
  • D. Borrione, M. Liu, P. Ostier, Laurent Fesquet. PSL-based online monitoring of digital systems. Vachoux A. in Advances in Design and Specification Languages for SoCs, Springer Verlag, Berlin, Germany, pp.5-22, 2006, CHDL series. <hal-00147582>
  • K. Slimani, J. Fragoso, Laurent Fesquet, Marc Renaudin. Low Power Asynchronous Processors. Low-Power Electronics Design, CRC Press, 912p., Chapter 22; Volume: 1, 2004, Series: Computer Engineering. <hal-00016113>
  • Jean-Baptiste Rigaud, J. Quartana, Laurent Fesquet, Marc Renaudin. Modeling and design of asynchronous priority arbiters for on-chip. SOC Design Methodologies Series: IFIP International Federation for Information Processing, Kluwer Academic Publishers, 496 p., pp.313-324, 2002, Vol. 90;. <hal-00016196>

Brevet4 documents

  • Laurent Fesquet, J. Hamon, A. Cherkaoui. Générateurs de nombres aléatoires vrais. France, N° de brevet: FR 12 51079. 2012. <hal-00750215>
  • D. Borrione, L. Ferro, Laurent Fesquet, K. Morin-Allory, Y. Oddos, et al.. Logiciel. France, Patent n° : FR.001.220016.000.S.P.2009.000.31500. 2009. <hal-00578146>
  • Marc Renaudin, G. Sicard, Laurent Fesquet, E. Allier. Method and device for analog-digital conversion, comprises a comparator delivering a pair of control signals to an increment-decrement block for computing new digital value. France, Patent n° : FR2835365. http://v3.espacenet.com/textdoc?DB=EPODOC&IDX=FR2835365&F=0. 2005. <hal-00008382>
  • Marc Renaudin, G. Sicard, Laurent Fesquet, E. Allier. Procédé et dispositif de conversion analogique-numérique. France, N° de brevet: FR2835365. http://v3.espacenet.com/results?sf=a&FIRST=1&CY=ep&LG=fr&DB=EPODOC&TI=&AB=&PN=+FR2835365&AP=&PR=&PD=&PA=&IN=&EC=&IC=&=&=&=&=&=. 2003. <hal-00008383>

Autre publication1 document

  • Brigitte Bidégaray-Fesquet, Laurent Fesquet. A new synthesis approach for non-uniform filters in the log-scale: proof of concept. soumis à publication. 2012, 12 p. <hal-00750061>

Pré-publication, Document de travail1 document

  • Brigitte Bidégaray-Fesquet, Laurent Fesquet. Non-uniform filter design. 2015. <hal-01187269>

Rapport1 document

  • Sylvain Durand, H. Zakaria, Laurent Fesquet, Nicolas Marchand. An Energy-Efficient Architecture for Nanometric Technologies with Strong Robustness to Process Variability : Design of a GALS node based on a MIPS R2000 processor. [Research Report] GIPSA-lab. 2013. <hal-00675609>

HDR1 document

  • Laurent Fesquet. Systèmes intégrés asynchrones et de traitement des signaux non uniformément échantillonnés. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2008. <tel-00280679>