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Vianney Lapôtre
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Documents
Identifiants chercheurs
- vianney-lapotre
- 0000-0002-8091-0703
- Google Scholar : https://scholar.google.fr/citations?user=w0aSCHcAAAAJ&hl=fr
- IdRef : 176951911
Présentation
I received my M.Sc. and my Ph.D. in Electrical and Computer Engineering from the University Bretagne Sud, France, in 2010 and 2013 respectively. In 2012 I spent six months as an invited researcher at the Ruhr-University of Bochum, Germany. From 2013 to 2014, I was a Postdoctoral at LIRMM, Montpellier, France. I was involved in the European Mont-Blanc project. I am currently associate professor at University Bretagne Sud, France. My research interests include hardware security, embedded processors and reconfigurable hardware architectures.
I received my M.Sc. and my Ph.D. in Electrical and Computer Engineering from the University Bretagne Sud, France, in 2010 and 2013 respectively. In 2012 I spent six months as an invited researcher at the Ruhr-University of Bochum, Germany. From 2013 to 2014, I was a Postdoctoral at LIRMM, Montpellier, France. I was involved in the European Mont-Blanc project. I am currently associate professor at University Bretagne Sud, France. My research interests include hardware security, embedded processors and reconfigurable hardware architectures.
Publications
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Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decodingEURASIP Journal on Advances in Signal Processing, 2017, 2017 (1), ⟨10.1186/s13634-017-0468-x⟩
Article dans une revue
hal-01595772v1
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A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo DecodingIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24 (1), pp.383 - 387. ⟨10.1109/TVLSI.2015.2396941⟩
Article dans une revue
hal-01121754v1
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An analytical approach for sizing of heterogeneous multiprocessor flexible platform for iterative demapping and channel decodingInternational Conference on ReConFigurable Computing and FPGAs (Reconfig), Dec 2012, Cancun, Mexico. ⟨10.1109/ReConFig.2012.6416728⟩
Communication dans un congrès
hal-00747714v1
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Efficient dynamic configuration of a multi-ASIP turbo decoderGDR SoC-SiP 2013 : Colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2013, Lyon, France
Poster de conférence
hal-00876017v1
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