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	Logical Effort Model Extension to Propagation Delay Representation Benoit Lasbouygues , Sylvain Engels , Robin P. Wilson , Philippe Maurine , Nadine Azemard IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25 (9), pp.1677-1684. ⟨10.1109/TCAD.2005.857400⟩ Article dans une revue lirmm-00104315v1
	Delay Bounds Based Constraint Distribution Method Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne IEE Proceedings - Computers and Digital Techniques (1994-2006), 2005, 152 (6), pp.765-770. ⟨10.1049/ip-cdt:20050026⟩ Article dans une revue lirmm-00105370v1
	General Representation of CMOS Structure Transition time for Timing Library Representation Philippe Maurine , Nadine Azemard , Daniel Auvergne Electronics Letters, 2002, 38 (4), pp.175-177. ⟨10.1049/el:20020103⟩ Article dans une revue lirmm-00239318v1
	Transition Time Modeling in Deep Submicron CMOS Philippe Maurine , Mustapha Rezzoug , Nadine Azemard , Daniel Auvergne IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, 21 (11), pp.1352-1363. ⟨10.1109/TCAD.2002.804088⟩ Article dans une revue lirmm-00239324v1

	Temperature Dependency in UDSM Process Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.693-703, ⟨10.1007/11556930_71⟩ Communication dans un congrès lirmm-00106077v1
	Low Power Oriented CMOS Circuit Optimization Protocol Alexandre Verle , Xavier Michel , Nadine Azemard , Philippe Maurine , Daniel Auvergne DATE 2005 - 8th Design, Automation and Test in Europe Conference and Exhibition, Mar 2005, Munich, Germany. pp.640-645, ⟨10.1109/DATE.2005.202⟩ Communication dans un congrès lirmm-00106452v1
	Temperature Dependence in Low Power CMOS UDSM Process Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.111-118, ⟨10.1007/978-3-540-30205-6_13⟩ Communication dans un congrès lirmm-00108893v1
	Design Optimization with Automated Cell Generation Alexis Landrault , Nadine Azemard , Philippe Maurine , Michel Robert , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.722-731, ⟨10.1007/978-3-540-30205-6_74⟩ Communication dans un congrès lirmm-00108894v1
	Automatic Layout Synthesis Based Performance Optimization Alexis Landrault , Nadine Azemard , Philippe Maurine , Michel Robert , Daniel Auvergne IWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85 Communication dans un congrès lirmm-00108654v1
	Optimization Protocol Based on Performance Metric Xavier Michel , Alexandre Verle , Nadine Azemard , Philippe Maurine , Daniel Auvergne DCIS 2004 - 19th International Conference on Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.964-968 Communication dans un congrès lirmm-00108935v1
	Delay Bound Based CMOS Gate Sizing Technique Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne ISCAS: International Symposium on Circuits and Systems, May 2004, Vancouver, BC, Canada. pp.189-192, ⟨10.1109/ISCAS.2004.1329494⟩ Communication dans un congrès lirmm-00108856v1
	Definition of P/N Width Ratio for CMOS Standard Cell Library Alexandre Verle , Philippe Maurine , Nadine Azemard , Daniel Auvergne DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.769-773 Communication dans un congrès lirmm-00108933v1
	RC on-chip interconnect Performance revisited Philippe Maurine , Nadine Azemard , Daniel Auvergne DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.809-814 Communication dans un congrès lirmm-00108934v1
	Physical Extension of the Logical Effort Model Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.838-848, ⟨10.1007/978-3-540-30205-6_86⟩ Communication dans un congrès lirmm-00108895v1
	Performance Metric Based Optimization Protocol Xavier Michel , Alexandre Verle , Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.100-109, ⟨10.1007/978-3-540-30205-6_12⟩ Communication dans un congrès lirmm-00108892v1
	Timing Performance Representation of a CMOS Standard Cell Library Benoit Lasbouygues , J. Schindler , Sylvain Engels , Philippe Maurine , Xavier Michel DCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. pp.83-88 Communication dans un congrès lirmm-00239460v1
	Metric Definition for Circuit Speed Optimization Xavier Michel , Alexandre Verle , Nadine Azemard , Philippe Maurine , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. pp.451-460 Communication dans un congrès lirmm-00269568v1
	Metric Definition for Circuit Speed Optimization Xavier Michel , Alexandre Verle , Philippe Maurine , Nadine Azemard , Daniel Auvergne IWLS: International Workshop on Logic Synthesis, May 2003, Laguna Beach, CA, United States Communication dans un congrès lirmm-00269689v1
	CMOS Gate Sizing under Delay Constraint Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Torino, Italy. pp.60-69, ⟨10.1007/978-3-540-39762-5_8⟩ Communication dans un congrès lirmm-00244021v1
	Dimensionnement de Portes CMOS Sous Contrainte de Délai Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.111-117 Communication dans un congrès lirmm-00269522v1
	Représentation Unifiée des Performances Temporelles d'une Bibliothèque de Cellules Standards Benoit Lasbouygues , J. Schindler , Sylvain Engels , Philippe Maurine , Nadine Azemard FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.119-124 Communication dans un congrès lirmm-00269519v1
	Définition d'une Métrique d'Insertion de Buffers Xavier Michel , Alexandre Verle , Nadine Azemard , Philippe Maurine , Daniel Auvergne FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.131-136 Communication dans un congrès lirmm-00269520v1
	Continuous Representation of the Performance of a CMOS Library Benoit Lasbouygues , J. Schindler , Sylvain Engels , Philippe Maurine , Xavier Michel ESSCIRC: European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal. pp.595-598, ⟨10.1109/ESSCIRC.2003.1257205⟩ Communication dans un congrès lirmm-00239459v1
	Gate Speed Improvement at Minimal Power Dissipation Philippe Maurine , Xavier Michel , Nadine Azemard , Daniel Auvergne APPCAS: Asia-Pacific Conference on Circuits and Systems, Oct 2002, Denpasar, Bali, pp.278-282 Communication dans un congrès lirmm-00239453v1
	Defining the Maximum Speed of CMOS Gate Library Philippe Maurine , Nadine Azemard , Daniel Auvergne DCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.81-86 Communication dans un congrès lirmm-00239455v1
	Structure Independent Representation of Output Transition Time for CMOS Library Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2002, Seville, Spain. pp.247-257, ⟨10.1007/3-540-45716-X_25⟩ Communication dans un congrès lirmm-00244012v1
	Metric Definition for Buffer Insertion Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne DCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.307-312 Communication dans un congrès lirmm-00239458v1
	Evaluation et Optimisation de Chemins Combinatoires Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne Colloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.173-176 Communication dans un congrès lirmm-00269329v1
	Technological Assignment for a Minimal Power Consumption Philippe Maurine , Nadine Azemard , Daniel Auvergne VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.236-241 Communication dans un congrès lirmm-00239450v1
	Timing Closure Management based on Delay Bound Determination Nadine Azemard , Michel Aline , Philippe Maurine , Daniel Auvergne VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.430-434 Communication dans un congrès lirmm-00239452v1
	Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2001, Yverdon-Les-Bains, Switzerland. pp.5.3.1-5.3.10 Communication dans un congrès lirmm-00244010v1
	Delay Bound Determination for Timing Closure on CMOS Circuits Nadine Azemard , Michel Aline , Philippe Maurine , Daniel Auvergne IWLS: International Workshop on Logic and Synthesis, Jun 2001, Granlibakken Conference Center, United States. pp.96-100 Communication dans un congrès lirmm-00244007v1
	Performance Indicators for Designing CMOS Logic Philippe Maurine , Nadine Azemard , Daniel Auvergne ICM: International Conference on Microelectronics, Oct 2001, Rabat, Morocco. pp.99-102, ⟨10.1109/ICM.2001.997497⟩ Communication dans un congrès lirmm-00239446v1
	Full Analyttical Model for delay Performance Estimation in Submicron CMOS Philippe Maurine , Nadine Azemard , Daniel Auvergne MIXDES: Mixed Design of Integrated Circuits and Systems, Jun 2001, Zakopane, Poland. pp.355-359 Communication dans un congrès lirmm-00239444v1
	Switching Current Modeling in CMOS Inverter for Speed and Power Estimation Philippe Maurine , Régis Poirier , Nadine Azemard , Daniel Auvergne DCIS: Design of Circuits and Integrated Systems, Nov 2001, Porto, Portugal. pp.618-622 Communication dans un congrès lirmm-00239448v1

	Modeling for Designing in Deep Sub-Micron Technologies Daniel Auvergne , Philippe Maurine , Nadine Azemard PIGUET C. Low-Power Electronics Design, CPR Press, 2004, 0-8493-1941-2 Chapitre d'ouvrage lirmm-00109162v1
	Feasible delay Bound Definition Nadine Azemard , Michel Aline , Philippe Maurine , Daniel Auvergne SOC Design Methodologies, 90, Kluwer Academic Publishers, pp.325-335, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_40⟩ Chapitre d'ouvrage lirmm-00239363v1
	Gate Sizing for Low Power Design Philippe Maurine , Nadine Azemard , Daniel Auvergne SOC Design Methodologies, 90, Kluwer Academic Publishers, pp.301-312, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_26⟩ Chapitre d'ouvrage lirmm-00239359v1

Philippe Maurine

Présentation

Publications

Logical Effort Model Extension to Propagation Delay Representation

Delay Bounds Based Constraint Distribution Method

General Representation of CMOS Structure Transition time for Timing Library Representation

Transition Time Modeling in Deep Submicron CMOS

Temperature Dependency in UDSM Process

Low Power Oriented CMOS Circuit Optimization Protocol

Temperature Dependence in Low Power CMOS UDSM Process

Design Optimization with Automated Cell Generation

Automatic Layout Synthesis Based Performance Optimization

Optimization Protocol Based on Performance Metric

Delay Bound Based CMOS Gate Sizing Technique

Definition of P/N Width Ratio for CMOS Standard Cell Library

RC on-chip interconnect Performance revisited

Physical Extension of the Logical Effort Model

Performance Metric Based Optimization Protocol

Timing Performance Representation of a CMOS Standard Cell Library

Metric Definition for Circuit Speed Optimization

Metric Definition for Circuit Speed Optimization

CMOS Gate Sizing under Delay Constraint

Dimensionnement de Portes CMOS Sous Contrainte de Délai

Représentation Unifiée des Performances Temporelles d'une Bibliothèque de Cellules Standards

Définition d'une Métrique d'Insertion de Buffers

Continuous Representation of the Performance of a CMOS Library

Gate Speed Improvement at Minimal Power Dissipation

Defining the Maximum Speed of CMOS Gate Library

Structure Independent Representation of Output Transition Time for CMOS Library

Metric Definition for Buffer Insertion

Evaluation et Optimisation de Chemins Combinatoires

Technological Assignment for a Minimal Power Consumption

Timing Closure Management based on Delay Bound Determination

Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination

Delay Bound Determination for Timing Closure on CMOS Circuits

Performance Indicators for Designing CMOS Logic

Full Analyttical Model for delay Performance Estimation in Submicron CMOS

Switching Current Modeling in CMOS Inverter for Speed and Power Estimation

Modeling for Designing in Deep Sub-Micron Technologies

Feasible delay Bound Definition

Gate Sizing for Low Power Design