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Philippe Maurine

223
Documents
Identifiants chercheurs
  • IdHAL philippe-maurine
  • Google Scholar : https://scholar.google.fr/citations?hl=fr&user=VduRIsgAAAAJ&view_op=list_works&sortby=pubdate
  • IdRef : 144880717
  • ORCID 0000-0002-9706-5710
  • Google Scholar : https://scholar.google.fr/citations?user=VduRIsgAAAAJ&hl=fr

Présentation

Publications

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(Adversarial) Electromagnetic Disturbance in the Industry

Arthur Beckers , Sylvain Guilley , Philippe Maurine , Colin O'Flynn , Stjepan Picek
IEEE Transactions on Computers, 2023, 72 (2), pp.414-422. ⟨10.1109/TC.2022.3224373⟩
Article dans une revue hal-03874307v1
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Revisiting Mutual Information Analysis: Multidimensionality, Neural Estimation and Optimality Proofs

Valence Cristiani , Maxime Lecomte , Philippe Maurine
Journal of Cryptology, 2023, 36, pp.38. ⟨10.1007/s00145-023-09476-0⟩
Article dans une revue lirmm-03628255v1
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Fit the Joint Moments: How to Attack Any Masking Scheme

Valence Cristiani , Maxime Lecomte , Thomas Hiscock , Philippe Maurine
IEEE Access, 2022, 10, pp.127412-127427. ⟨10.1109/ACCESS.2022.3222760⟩
Article dans une revue lirmm-03895675v1

Checking Robustness Against EM Side-Channel Attacks Prior to Manufacturing

Davide Poggi , Thomas Ordas , Alexandre Sarafianos , Philippe Maurine
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 41 (5), pp.1264-1275. ⟨10.1109/TCAD.2021.3092297⟩
Article dans une revue lirmm-03278781v1
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Spatial dependency analysis to extract information from side-channel mixtures: extended version

Aurélien Vasselle , Hugues Thiebeauld , Philippe Maurine
Journal of Cryptographic Engineering, 2022, ⟨10.1007/s13389-022-00307-9⟩
Article dans une revue lirmm-04230173v1

Modeling and Simulating Electromagnetic Fault Injection

Mathieu Lisart , Philippe Maurine , Mathieu Dumont
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, 40 (4), pp.680-693. ⟨10.1109/TCAD.2020.3003287⟩
Article dans une revue lirmm-02938004v1
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Simulation and Experimental Demonstration of the Importance of IR-Drops During Laser Fault-Injection

Raphael Andreoni Camponogara-Viera , Philippe Maurine , Jean-Max Dutertre , Rodrigo Possamai Bastos
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39 (6), pp.1231-1244. ⟨10.1109/TCAD.2019.2928972⟩
Article dans une revue hal-02299068v1

From theory to practice: horizontal attacks on protected implementations of modular exponentiations

Ibrahima Diop , Yanis Linge , Thomas Ordas , Pierre-Yvan Liardet , Philippe Maurine
Journal of Cryptographic Engineering, 2019, 9 (1), pp.37-52. ⟨10.1007/s13389-018-0181-1⟩
Article dans une revue lirmm-01713147v1
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Estimating the Signal-to-Noise ratio under repeated sampling of the same centered signal: applications to side-channel attacks on a cryptoprocessor

Gilles R. Ducharme , Philippe Maurine
IEEE Transactions on Information Theory, 2018, 64 (9), pp.6333-6339. ⟨10.1109/TIT.2018.2851217⟩
Article dans une revue hal-01830075v1

Method for evaluation of transient-fault detection techniques

Raphael Viera , Rodrigo Possamai Bastos , Jean-Max Dutertre , Philippe Maurine , Rodrigo Iga Jadue
Microelectronics Reliability, 2017, 76-77, pp.68-74. ⟨10.1016/j.microrel.2017.07.007⟩
Article dans une revue lirmm-01690185v1
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Electromagnetic fault injection: the curse of flip-flops

Sébastien Ordas , Ludovic Guillaume-Sage , Philippe Maurine
Journal of Cryptographic Engineering, 2017, 7 (3), pp.183-197. ⟨10.1007/s13389-016-0128-3⟩
Article dans une revue lirmm-01430913v1
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An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit Identification

Maxime Lecomte , Jacques Jean-Alain Fournier , Philippe Maurine
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 25 (12), pp.3317-3330. ⟨10.1109/TVLSI.2016.2627525⟩
Article dans une revue lirmm-01430925v1
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Mutual information analysis: higher-order statistical moments, efficiency and efficacy

Mathieu Carbone , Yannick Teglia , Gilles R. Ducharme , Philippe Maurine
Journal of Cryptographic Engineering, 2017, 7 (1), pp.1-17. ⟨10.1007/s13389-016-0123-8⟩
Article dans une revue lirmm-01285152v1
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Vertical and horizontal correlation attacks on RNS-based exponentiations

Guilherme Perin , Laurent Imbert , Philippe Maurine , Lionel Torres
Journal of Cryptographic Engineering, 2015, 5 (3), pp.171-185. ⟨10.1007/s13389-015-0095-0⟩
Article dans une revue lirmm-01269799v1

A model of the leakage in the frequency domain and its application to CPA and DPA

Sébastien Tiran , Sébastien Ordas , Yannick Teglia , Michel Agoyan , Philippe Maurine
Journal of Cryptographic Engineering, 2014, 4 (3), pp.197-212. ⟨10.1007/s13389-014-0074-x⟩
Article dans une revue lirmm-01096000v1

Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures

Lionel Vincent , Edith Beigné , Suzanne Lesecq , Julien Mottin , David Coriat
IEEE Transactions on Circuits and Systems Part 1 Fundamental Theory and Applications, 2014, Part I: Regular Papers, 61 (6), pp.1741-1754. ⟨10.1109/TCSI.2013.2290850⟩
Article dans une revue lirmm-01096015v1

Secure D Flip-Flop Against Side ChannelL Attacks

Bruno Vaquie , Sébastien Tiran , Philippe Maurine
IET Circuits, Devices & Systems, 2012, 6 (5), pp.347-354. ⟨10.1049/iet-cds.2011.0345⟩
Article dans une revue lirmm-00762016v1

Delay-correlation-aware SSTA based on conditional moments

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
Microelectronics Journal, 2012, 43 (4), pp.263-273. ⟨10.1016/j.mejo.2012.01.003⟩
Article dans une revue lirmm-00761821v1
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Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence

Philippe Maurine , Amine Dehbaoui , Victor Lomné , Thomas Ordas , Lionel Torres
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012, 20 (3), pp.573-577. ⟨10.1109/TVLSI.2011.2104984⟩
Article dans une revue lirmm-00761786v1
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A GALS Pipeline DES Architecture to Increase Robustness Against CPA and CEMA Attacks

Rafael Iankowski Soares , Ney Laert Vilar Calazans , Victor Lomné , Amine Dehbaoui , Philippe Maurine
Journal of Integrated Circuits and Systems, 2011, Special Section on Best SBCCI2010 Papers, 6 (1), pp.25-34. ⟨10.29292/jics.v6i1.335⟩
Article dans une revue lirmm-00607871v1

A Robust Architectural Approach for Cryptographic Algorithms using GALS Pipelines

Rafael A. Soares , Ney Calazans , Fernando Gehm Moraes , Philippe Maurine , Lionel Torres
IEEE Design & Test, 2011, 28 (5), pp.62-71. ⟨10.1109/MDT.2011.69⟩
Article dans une revue lirmm-00596741v1
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Timing Slack Monitoring under Process and Environmental Variations: Application to a DSP Performance Optimization

Philippe Maurine , Bettina Rebaud , Marc Belleville , Edith Beigné , Christian Bernard
Microelectronics Journal, 2011, 42 (5), pp.718-732. ⟨10.1016/j.mejo.2011.02.005⟩
Article dans une revue lirmm-00607877v1

On-Chip Process Variability Monitoring Flow

Nabila Moubdi , Philippe Maurine , Robin M. Wilson , Nadine Azemard , Sylvain Engels
Journal of Low Power Electronics, 2010, 6 (4), pp.601-606. ⟨10.1166/jolpe.2010.1109⟩
Article dans une revue lirmm-00546368v1
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Secure Triple Track Logic Robustness Against Differential Power and Electromagnetic Analyses

Victor Lomné , Amine Dehbaoui , Thomas Ordas , Philippe Maurine , Lionel Torres
Journal of Integrated Circuits and Systems, 2009, 4 (1), pp.20-28. ⟨10.29292/jics.v4i1.293⟩
Article dans une revue lirmm-03613238v1

Magnitude Squared Incoherence EM Analysis for Integrated Cryptographic modules Localization

Amine Dehbaoui , Victor Lomné , Philippe Maurine , Lionel Torres
Electronics Letters, 2009, 45 (15), pp.778-780. ⟨10.1049/el.2009.0342⟩
Article dans une revue lirmm-00402776v1

Timing Margin Evaluation with a Simple Statistical Timing Analysis Flow

Sylvain Engels , Robin M. Wilson , Nadine Azemard , Philippe Maurine , Vincent Migairou
Journal of Embedded Computing, 2009, 3 (3), pp.221-229. ⟨10.3233/JEC-2009-0094⟩
Article dans une revue lirmm-00371162v1
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Temperature and Voltage Aware Timing Analysis

Benoit Lasbouygues , Robin P. Wilson , Nadine Azemard , Philippe Maurine
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26 (4), pp.801-815. ⟨10.1109/TCAD.2006.884860⟩
Article dans une revue lirmm-00178921v1

A Comprehensive Performance Macro-Modeling of on-Chip RC Interconnects Considering Line Shielding Effects

Sylvain Engels , Robin Wilson , Nadine Azemard , Philippe Maurine
Integration, the VLSI Journal, 2006, 39 (4), pp.433-456. ⟨10.1016/j.vlsi.2005.08.007⟩
Article dans une revue lirmm-00106854v1

Logical Effort Model Extension to Propagation Delay Representation

Benoit Lasbouygues , Sylvain Engels , Robin P. Wilson , Philippe Maurine , Nadine Azemard
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25 (9), pp.1677-1684. ⟨10.1109/TCAD.2005.857400⟩
Article dans une revue lirmm-00104315v1

Delay Bounds Based Constraint Distribution Method

Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne
IEE Proceedings - Computers and Digital Techniques (1994-2006), 2005, 152 (6), pp.765-770. ⟨10.1049/ip-cdt:20050026⟩
Article dans une revue lirmm-00105370v1

Compact and Secured Primitives for the Design of Asynchronous Circuits

Alin Razafindraibe , Michel Robert , Philippe Maurine
Journal of Low Power Electronics, 2005, 1 (1), pp.20-26. ⟨10.1166/jolpe.2005.009⟩
Article dans une revue lirmm-00105365v1

General Representation of CMOS Structure Transition time for Timing Library Representation

Philippe Maurine , Nadine Azemard , Daniel Auvergne
Electronics Letters, 2002, 38 (4), pp.175-177. ⟨10.1049/el:20020103⟩
Article dans une revue lirmm-00239318v1

Transition Time Modeling in Deep Submicron CMOS

Philippe Maurine , Mustapha Rezzoug , Nadine Azemard , Daniel Auvergne
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, 21 (11), pp.1352-1363. ⟨10.1109/TCAD.2002.804088⟩
Article dans une revue lirmm-00239324v1
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The EVIL Machine: Encode, Visualize and Interpret the Leakage

Valence Cristiani , Maxime Lecomte , Philippe Maurine
SAC 2023 - 38th ACM/SIGAPP Symposium on Applied Computing, Mar 2023, Tallinn, Estonia. pp.1566-1575, ⟨10.1145/3555776.3577688⟩
Communication dans un congrès lirmm-04230167v1
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Iterative Method for Performance Prediction Improvement of Integrated Circuits

Gwenael Chaillou , Philippe Maurine , Jean-Marc J.-M. Galliere , Nadine Azemard
DCIS 2021 - 36th Conference on Design of Circuits and Integrated Systems, Nov 2021, Vila do Conde, Portugal. pp.1-5, ⟨10.1109/DCIS53048.2021.9666182⟩
Communication dans un congrès lirmm-03710383v1
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Spatial Dependency Analysis to Extract Information from Side-Channel Mixtures

Aurélien Vasselle , Hugues Thiebeauld , Philippe Maurine
ASHES 2021 - 5th Workshop on Attacks and Solutions in Hardware Security @CCS 2021, Nov 2021, Virtual Event, South Korea. pp.73-84, ⟨10.1145/3474376.3487280⟩
Communication dans un congrès lirmm-03476806v1
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On the scaling of EMFI probes

Julien Toulemont , Geoffrey Chancel , Jean-Marc J.-M. Galliere , Frédérick Mailly , Pascal Nouet
FDTC 2021 - Workshop on Fault Detection and Tolerance in Cryptography, Sep 2021, Milan, Italy. pp.67-73, ⟨10.1109/FDTC53659.2021.00019⟩
Communication dans un congrès lirmm-03476820v1

Exploring flexible and 3D printing technologies for the design of high spatial resolution EM probes

Julien Toulemont , Frédérick Mailly , Philippe Maurine , Pascal Nouet
NEWCAS 2021 - 19th IEEE International New Circuits and Systems Conference, Jun 2021, Toulon, France. pp.1-4, ⟨10.1109/NEWCAS50681.2021.9462763⟩
Communication dans un congrès lirmm-03278789v1
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Leakage Assessment through Neural Estimation of the Mutual Information

Valence Cristiani , Maxime Lecomte , Philippe Maurine
ACNS 2020 - International Conference on Applied Cryptography and Network Security, Oct 2020, Rome, Italy. pp.144-162, ⟨10.1007/978-3-030-61638-0_9⟩
Communication dans un congrès hal-02980501v1
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Breaking Mobile Firmware Encryption through Near-Field Side-Channel Analysis

Aurélien Vasselle , Philippe Maurine , Maxime Cozzi
ASHES 2019 - 3rd Attacks and Solutions in Hardware Security Workshop, Nov 2019, London, United Kingdom. pp.23-32, ⟨10.1145/3338508.3359571⟩
Communication dans un congrès lirmm-03660638v1
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Electromagnetic Fault Injection : How Faults Occur

Mathieu Dumont , Mathieu Lisart , Philippe Maurine
FDTC 2019 - Workshop on Fault Diagnosis and Tolerance in Cryptography, Aug 2019, Atlanta, GA, United States. pp.9-16, ⟨10.1109/FDTC.2019.00010⟩
Communication dans un congrès lirmm-02328109v1

Electromagnetic Activity vs. Logical Activity: Near Field Scans for Reverse Engineering

Marc Lacruche , Philippe Maurine
CARDIS 2018 - 17th International Conference on Smart Card Research and Advanced Applications, Nov 2018, Montpellier, France. pp.140-155, ⟨10.1007/978-3-030-15462-2_10⟩
Communication dans un congrès lirmm-01943151v1
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Thermal Scans for Detecting Hardware Trojans

Maxime Cozzi , Philippe Maurine , Jean-Marc J.-M. Galliere
COSADE 2018 - 9th International Workshop on Constructive Side-Channel Analysis and Secure Design, Apr 2018, Singapour, Singapore. pp.117-132, ⟨10.1007/978-3-319-89641-0_7⟩
Communication dans un congrès lirmm-01823444v1
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Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits

Raphael Andreoni Camponogara-Viera , Jean-Max Dutertre , Philippe Maurine , Rodrigo Possamai Bastos
ISPD 2018 - International Symposium on Physical Design, Mar 2018, Monterey, CA, United States. pp.160-167, ⟨10.1145/3177540.3178243⟩
Communication dans un congrès lirmm-01743368v1

The impact of pulsed electromagnetic fault injection on true random number generators

Maxime Madau , Michel Agoyan , Josep Balash , Milos Grujic , Patrick Haddad
FDTC 2018 - Workshop on Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. pp.43-48, ⟨10.1109/FDTC.2018.00015⟩
Communication dans un congrès lirmm-01943112v1
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Exploiting Phase Information in Thermal Scans for Stealthy Trojan Detection

Maxime Cozzi , Jean-Marc J.-M. Galliere , Philippe Maurine
DSD 2018 - 21st Euromicro Conference on Digital System Design, Aug 2018, Prague, Slovakia. pp.573-576, ⟨10.1109/DSD.2018.00100⟩
Communication dans un congrès lirmm-01872499v1

Method for evaluation of transient-fault detection techniques

Raphael Andreoni Camponogara-Viera , Rodrigo Possamai Bastos , Jean-Max Dutertre , Philippe Maurine
ESREF: European Symposium on Reliability of Electron devices, Failure physics and analysis, Sep 2017, Bordeaux, France
Communication dans un congrès hal-01721081v1
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Role of Laser-Induced IR Drops in the Occurrence of Faults: Assessment and Simulation

Raphael Andreoni Camponogara-Viera , Jean-Max Dutertre , Rodrigo Possamai Bastos , Philippe Maurine
DSD 2017 - Euromicro Symposium on Digital System Design, Aug 2017, Vienna, Austria. pp.252-259, ⟨10.1109/DSD.2017.43⟩
Communication dans un congrès lirmm-01699776v1
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Impacts of Technology Trends on Physical Attacks?

Philippe Maurine , Sylvain Guilley
COSADE 2017 - 8th International Workshop on Constructive Side-Channel Analysis and Secure Design, Apr 2017, Paris, France. pp.190-206, ⟨10.1007/978-3-319-64647-3_12⟩
Communication dans un congrès lirmm-01690188v1
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Importance of IR Drops on the Modeling of Laser-Induced Transient Faults

Raphael Viera , Philippe Maurine , Jean-Max Dutertre , Rodrigo Possamai Bastos
SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Jun 2017, Giardini Naxos, Italy. ⟨10.1109/SMACD.2017.7981593⟩
Communication dans un congrès hal-01721087v1

An {EM} Fault Injection Susceptibility Criterion and Its Application to the Localization of Hotspots

Maxime Madau , Michel Agoyan , Philippe Maurine
CARDIS 2017 - 16th International Conference on Smart Card Research and Advanced Applications, Nov 2017, Lugano, Switzerland. pp.180-195, ⟨10.1007/978-3-319-75208-2_11⟩
Communication dans un congrès lirmm-02100194v1
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A Fully-Digital Em Pulse Detector

David El-Baze , Jean-Baptiste Rigaud , Philippe Maurine
DATE 2016 - 19th Design, Automation and Test in Europe Conference and Exhibition, Mar 2016, Dresden, Germany. pp.439-444
Communication dans un congrès lirmm-01269860v1

Body Biasing Injection Attacks in Practice

Noemie Beringuier-Boher , Marc Lacruche , David El-Baze , Jean-Max Dutertre , Jean-Baptiste Rigaud
CS2: Cryptography and Security in Computing Systems, Jan 2016, Prague, Czech Republic. pp.49-54, ⟨10.1145/2858930.2858940⟩
Communication dans un congrès lirmm-01434143v1
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On-Chip Fingerprinting of IC Topology for Integrity Verification

Maxime Lecomte , Jacques Jean-Alain Fournier , Philippe Maurine
DATE 2016 - 19th Design, Automation and Test in Europe Conference and Exhibition, Mar 2016, Dresden, Germany. pp.133-138, ⟨10.3850/9783981537079_0169⟩
Communication dans un congrès lirmm-01269856v1

Granularity and detection capability of an adaptive embedded Hardware Trojan detection system

Maxime Lecomte , Jacques Jean-Alain Fournier , Philippe Maurine
HOST: Hardware Oriented Security and Trust, May 2016, McLean, VA, United States. pp.135-138, ⟨10.1109/HST.2016.7495571⟩
Communication dans un congrès lirmm-01434150v1

Electromagnetic Analysis Perturbation using Chaos Generator

Thomas Sarno , Romain Wacquez , Edith Kussener , Philippe Maurine , Khalil Jradi
Truedevice 2016, Nov 2016, Barcelona, Spain
Communication dans un congrès hal-01455446v1

An Embedded Digital Sensor against EM and BB Fault Injection

David El-Baze , Jean-Baptiste Rigaud , Philippe Maurine
FDTC: Fault Diagnosis and Tolerance in Cryptography, Aug 2016, Santa Barbara, CA, United States. pp.78-86, ⟨10.1109/FDTC.2016.14⟩
Communication dans un congrès lirmm-01434028v1
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EM Injection: Fault Model and Locality

Sébastien Ordas , Ludovic Guillaume-Sage , Philippe Maurine
FDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2015, Saint Malo, France. pp.3-13, ⟨10.1109/FDTC.2015.9⟩
Communication dans un congrès lirmm-01319078v1
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Thoroughly analyzing the use of ring oscillators for on-chip hardware trojan detection

Maxime Lecomte , Philippe Maurine , Jacques Jean-Alain Fournier
ReConFig: ReConFigurable Computing and FPGAs, Dec 2015, Mexico, Mexico. pp.1-6, ⟨10.1109/ReConFig.2015.7393363⟩
Communication dans un congrès lirmm-01354318v1
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Collision for Estimating SCA Measurement Quality and Related Applications

Ibrahima Diop , Mathieu Carbone , Sébastien Ordas , Yanis Linge , Pierre Yvan Liardet
CARDIS: Smart Card Research and Advanced Applications, Nov 2015, Bochum, Germany. pp.143-157, ⟨10.1007/978-3-319-31271-2_9⟩
Communication dans un congrès lirmm-01319093v1
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Collision Based Attacks in Practice

Ibrahima Diop , Pierre-Yvan Liardet , Yanis Linge , Philippe Maurine
DSD: Digital System Design, Aug 2015, Madeire, Portugal. pp.367-374, ⟨10.1109/DSD.2015.24⟩
Communication dans un congrès lirmm-01269809v1

Interest of MIA in frequency domain?

Mathieu Carbone , Yannick Teglia , Philippe Maurine , Gilles R. Ducharme
CS2: Cryptography and Security in Computing Systems, Jan 2015, Amtersdam, Netherlands. pp.35-38, ⟨10.1145/2694805.2694812⟩
Communication dans un congrès lirmm-01111693v1

A frequency leakage model for SCA

Sébastien Tiran , Sébastien Ordas , Yannick Teglia , Michel Agoyan , Philippe Maurine
HOST 2014 - IEEE International Symposium on Hardware-Oriented Security and Trust, May 2014, Arlington, VA, United States. pp.97-100, ⟨10.1109/HST.2014.6855577⟩
Communication dans un congrès lirmm-01096058v1
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Attacking Randomized Exponentiations Using Unsupervised Learning

Guilherme Perin , Laurent Imbert , Lionel Torres , Philippe Maurine
COSADE: Constructive Side-Channel Analysis and Secure Design, Apr 2014, Paris, France. pp.144-160, ⟨10.1007/978-3-319-10175-0_11⟩
Communication dans un congrès lirmm-01096039v1

Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI)

Laurent Chusseau , Rachid Omarouayache , Jérémy Raoult , Sylvie Jarrix , Philippe Maurine
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2014, Playa del Carmen, Mexico. pp.1-6, ⟨10.1109/VLSI-SoC.2014.7004189⟩
Communication dans un congrès lirmm-01434592v1

On Adaptive Bandwidth Selection for Efficient MIA

Mathieu Carbone , Sébastien Tiran , Sébastien Ordas , Michel Agoyan , Yannick Teglia
COSADE: Constructive Side-Channel Analysis and Secure Design, Apr 2014, Paris, France. pp.82-97, ⟨10.1007/978-3-319-10175-0_7⟩
Communication dans un congrès lirmm-01096033v1
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ElectroMagnetic Analysis and Fault Injection onto Secure Circuits

Paolo Maistri , Régis Leveugle , Lilian Bossuet , Alain Aubert , Viktor Fischer
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2014, Mexico, Mexico. ⟨10.1109/VLSI-SoC.2014.7004182⟩
Communication dans un congrès emse-01099025v1
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Evidence of a larger EM-induced fault model

Sébastien Ordas , Ludovic Guillaume-Sage , Karim Tobich , Jean-Max Dutertre , Philippe Maurine
CARDIS: Smart Card Research and Advanced Applications, Nov 2014, Paris, France. pp.245-259, ⟨10.1007/978-3-319-16763-3_15⟩
Communication dans un congrès emse-01099037v1
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Efficiency of a glitch detector against electromagnetic fault injection

Loic Zussa , Amine Dehbaoui , Karim Tobich , Jean-Max Dutertre , Philippe Maurine
DATE 2014 - 17th Design, Automation and Test in Europe Conference and Exhibition, Mar 2014, Dresden, Germany. ⟨10.7873/DATE.2014.216⟩
Communication dans un congrès lirmm-01096047v1

Electromagnetic Analysis on RSA Algorithm Based on RNS

Guilherme Perin , Laurent Imbert , Lionel Torres , Philippe Maurine
DSD: Digital System Design, Sep 2013, Santander, Spain. pp.345-352, ⟨10.1109/DSD.2013.44⟩
Communication dans un congrès lirmm-00861215v1
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Magnetic Microprobe design for EM fault attack

Rachid Omarouayache , Jérémy Raoult , Sylvie Jarrix , Laurent Chusseau , Philippe Maurine
EMC EUROPE: Electromagnetic Compatibility, Sep 2013, Bruges, Belgium
Communication dans un congrès hal-01893856v1

Countermeasures against EM analysis for a secured FPGA-based AES implementation

Paolo Maistri , Sébastien Tiran , Philippe Maurine , Israel Koren , Régis Leveugle
ReConFig'13: International Conference on ReConFigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1-6, ⟨10.1109/ReConFig.2013.6732274⟩
Communication dans un congrès hal-00963133v1
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Practical Analysis of RSA Countermeasures Against Side-Channel Electromagnetic Attacks

Guilherme Perin , Laurent Imbert , Lionel Torres , Philippe Maurine
CARDIS: Smart Card Research and Advanced Applications, Nov 2013, Berlin, Germany. pp.200-215, ⟨10.1007/978-3-319-08302-5_14⟩
Communication dans un congrès lirmm-01096070v1

An evaluation of an AES implementation protected against EM analysis

Paolo Maistri , Sébastien Tiran , Philippe Maurine , Israel Koren , Régis Leveugle
GLSVLSI: Great Lakes Symposium on VLSI, May 2013, Paris, France. pp.317-318, ⟨10.1145/2483028.2483120⟩
Communication dans un congrès hal-00862787v1
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Temperature and Fast Voltage On-Chip Monitoring using Low-Cost Digital Sensors

Lionel Vincent , Philippe Maurine , Edith Beigné , Suzanne Lesecq , Julien Mottin
VARI: Workshop on CMOS Variability, Sep 2013, Karlsruhe, Germany
Communication dans un congrès hal-01067982v1

Voltage Spikes on the Substrate to Obtain Timing Faults

Karim Tobich , Philippe Maurine , Pierre-Yvan Liardet , Mathieu Lisart , Thomas Ordas
DSD: Digital System Design, Sep 2013, Santander, Spain. pp.483-486, ⟨10.1109/DSD.2013.146⟩
Communication dans un congrès lirmm-01096076v1

Electromagnetic Attacks on Ring Oscillator-Based True Random Number Generator

Pierre Bayon , Lilian Bossuet , Alain Aubert , Viktor Fischer , François Poucheret
CryptArchi: Cryptographic Architectures, Jun 2012, Saint-Etienne, France
Communication dans un congrès ujm-00712545v1
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Yet Another Fault Injection Technique : by Forward Body Biasing Injection

Philippe Maurine , Karim Tobich , Thomas Ordas , Pierre Yvan Liardet
YACC'2012: Yet Another Conference on Cryptography, Sep 2012, Porquerolles Island, France
Communication dans un congrès lirmm-00762035v1
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Amplitude Demodulation-Based EM Analysis of Different RSA Implementations

Philippe Maurine , Guilherme Perin , Lionel Torres , Pascal Benoit
DATE: Design, Automation and Test in Europe, Mar 2012, Dresden, Germany. pp.1167-1172, ⟨10.1109/DATE.2012.6176670⟩
Communication dans un congrès lirmm-00762023v1

Statistical Cells Timing Metrics Characterization

Nadine Azemard , Zeqin Wu , Philippe Maurine , Gilles R. Ducharme
FTFC: Faible Tension - Faible Consommation, Jun 2012, Paris, France
Communication dans un congrès lirmm-00762131v1

On the use of the EM medium as a fault injection means

Philippe Maurine , Amine Dehbaoui , François Poucheret , Jean-Max Dutertre , Bruno Robisson
CryptArchi: Cryptographic Architectures, Jun 2012, St-Etienne, France
Communication dans un congrès emse-00742707v1
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Techniques for EM Fault Injection: Equipments and Experimental Results

Philippe Maurine
FDTC'2012: Fault Diagnosis and Tolerance in Cryptography, Sep 2012, Lewen, Belgium. pp.003-004
Communication dans un congrès lirmm-00761778v1

Countermeasures against EM Analysis

Paolo Maistri , Sébastien Tiran , Amine Dehbaoui , Philippe Maurine , Jean-Max Dutertre
10th CryptArchi Workshop - St-Etienne Goutelas 2012, Jun 2012, Saint-Etienne, France
Communication dans un congrès emse-01130646v1

Local Condition Monitoring in Integrated Circuits Using a Set of Kolmogorov-Smirnov Tests

Philippe Maurine , Lionel Vincent , Suzanne Lesecq , Edith Beigné
MSC'2012: Multi-conference on Systems and Control, Oct 2012, Dubrovnik, Croatia. pp.001-010
Communication dans un congrès lirmm-00762045v1

Embedding Statistical Tests for On-Chip Dynamic Voltage and Temperature Monitoring

Philippe Maurine , Lionel Vincent , Suzanne Lesecq , Edith Beigné
DAC: Design Automation Conference, Jun 2012, San Francisco, CA, United States. pp.994-999
Communication dans un congrès lirmm-00762020v1
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SECNUM: an Open Characterizing Platform for Integrated Circuits

Morgan Bourrée , Florent Bruguier , Lyonel Barthe , Pascal Benoit , Philippe Maurine
European Workshop on Microelectronics Education (EWME), May 2012, Grenoble, France
Communication dans un congrès hal-01139176v1
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SCA with Magnitude Squared Coherence

Philippe Maurine , Sébastien Tiran
CARDIS: Smart Card Research and Advanced Applications, Nov 2012, Graz, Austria. pp.234-247, ⟨10.1007/978-3-642-37288-9_16⟩
Communication dans un congrès lirmm-00762038v1
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Contactless Electromagnetic Active Attack on Ring Oscillator Based True Random Number Generator

Pierre Bayon , Lilian Bossuet , Alain Aubert , Viktor Fischer , François Poucheret
COSADE: Constructive Side-Channel Analysis and Secure Design, May 2012, Darmstadt, Germany. pp.151-166, ⟨10.1007/978-3-642-29912-4_12⟩
Communication dans un congrès ujm-00699618v1

Characterizing Statistical Cells Timing Metrics with Semi-Monte-Carlo Method

Nadine Azemard , Zeqin Wu , Philippe Maurine , Gilles R. Ducharme
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2011, Hong-Kong, China
Communication dans un congrès lirmm-00617606v1

Local ElectroMagnetic Coupling with CMOS Integrated Circuits

François Poucheret , Laurent Chusseau , Bruno Robisson , Philippe Maurine
8th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC COMPO), 2011, Dubrovnik, Croatia. pp.137-141
Communication dans un congrès hal-01904161v1

Local EM perturbations into CMOS ring oscillator

François Poucheret , Karim Tobich , Mathieu Lisart , Laurent Chusseau , Philippe Maurine
5th International Conference on Electromagnetic Near-Field Characterization and Imaging (ICONIC), Nov 2011, Rouen, France
Communication dans un congrès hal-01904164v1

Local and Direct Power Injection on CMOS Integrated Circuits

Philippe Maurine , François Poucheret , Karim Tobich , Mathieu Lisart , Bruno Robisson
FDTC'2011: Fault Diagnosis and Tolerance in Cryptography, Sep 2011, Nara, Japan. pp.100-104, ⟨10.1109/FDTC.2011.18⟩
Communication dans un congrès lirmm-00607868v1
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A Fully Integrated 32 nm MultiProbe for Dynamic PVT Measurements within Complex Digital SoC

Lionel Vincent , Edith Beigné , Laurent Alacoque , Suzanne Lesecq , Catherine Bour
VARI: International Workshop on CMOS Variability, May 2011, Grenoble, France
Communication dans un congrès hal-01067989v1

Sondes de champ proche pour l'injection de fautes

Rachid Omarouayache , Jérémy Raoult , Sylvie Jarrix , Philippe Maurine , Laurent Chusseau
Journée "Antenne de Champ Proche'' du GDR Ondes, 2011, Paris, France
Communication dans un congrès hal-01904165v1
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A Secure D Flip-Flop against Side Channel Attacks

Bruno Vaquie , Sébastien Tiran , Philippe Maurine
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2011, Madrid, Spain. pp.331-340, ⟨10.1007/978-3-642-24154-3_33⟩
Communication dans un congrès lirmm-00762027v1

Statistical Timing Characterization of Standard Cells with Semi-Monte-Carlo Method

Nadine Azemard , Zeqin Wu , Philippe Maurine , Gilles R. Ducharme
VARI: Workshop on CMOS Variaility, May 2011, Grenoble, France
Communication dans un congrès lirmm-00617593v1

Computing Delay Correlations in SSTA

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
ICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.130-133, ⟨10.1109/ICICDT.2010.5510277⟩
Communication dans un congrès lirmm-00546301v1
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Spatial EM Jamming: a Countermeasure Against EM Analysis ?

François Poucheret , Lyonel Barthe , Pascal Benoit , Lionel Torres , Philippe Maurine
VLSI-SoC'10: 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, Madrid, Spain. pp.105-110
Communication dans un congrès lirmm-00544358v1

On-Chip Process Variability Monitoring

Nabila Moubdi , Philippe Maurine , Robin M. Wilson , Nadine Azemard , Vincent Dumettier
VARI: Workshop on CMOS Variability, May 2010, Montpellier, France
Communication dans un congrès lirmm-00546337v1

SSTA with Cell-to-Cell Delay Correlations

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
VARI: Workshop on CMOS Variability, May 2010, Montpellier, France
Communication dans un congrès lirmm-00546322v1

SSTA with Delay Correlations

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
NEWCAS: New Circuits and Systems, Jun 2010, Montreal, QC, Canada. pp.261-266, ⟨10.1109/NEWCAS.2010.5603930⟩
Communication dans un congrès lirmm-00504882v1
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Differential Power Analysis Enhancement with Statistical Preprocessing

Victor Lomné , Amine Dehbaoui , Philippe Maurine , Lionel Torres , Michel Robert
DATE: Design, Automation and Test in Europe, 2010, Dresden, Germany. pp.1301-1304, ⟨10.1109/DATE.2010.5457007⟩
Communication dans un congrès lirmm-00548738v1
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Modeling Time Domain Magnetic Emissions of ICs

Victor Lomné , Philippe Maurine , Lionel Torres , Thomas Ordas , Mathieu Lisart
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2010, Grenoble, France. pp.238-249, ⟨10.1007/978-3-642-17752-1_24⟩
Communication dans un congrès lirmm-00762033v1

Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPC

Nabila Moubdi , Philippe Maurine , Nadine Azemard , Robin M. Wilson , Sylvain Engels
ICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.82-85, ⟨10.1109/ICICDT.2010.5510289⟩
Communication dans un congrès lirmm-00546316v1
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Incoherence Analysis and its Application to Time Domain EM Analysis of Secure Circuits

Philippe Maurine , Amine Dehbaoui , Thomas Ordas , Victor Lomné , Lionel Torres
APEMC 2010 - Asia-Pacific Symposium on Electromagnetic Compatibility, Apr 2010, Beijing, China. pp.1039-1042, ⟨10.1109/APEMC.2010.5475481⟩
Communication dans un congrès lirmm-00607894v1
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Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variations

Bettina Rebaud , Marc Belleville , Edith Beigné , Michel Robert , Philippe Maurine
FTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Suisse
Communication dans un congrès lirmm-00404810v1
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Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of Variabilities

Bettina Rebaud , Marc Belleville , Edith Beigné , Christian Bernard , Michel Robert
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.266-275, ⟨10.1007/978-3-642-11802-9_31⟩
Communication dans un congrès lirmm-00433462v1

Technological countermeasures for IC protection against EM Analysis

Thomas Ordas , M. Lisart , Lionel Torres , Philippe Maurine
PAca Security Trends In embedded Security, Gardanne, France
Communication dans un congrès lirmm-00407011v1

Electromagnetic analyses of secure circuits: Results on FPGA & ASIC

Philippe Maurine
MARITE : Centre d'ELectronique de l'Armement (CELAR), France
Communication dans un congrès lirmm-00407014v1

On-Chip Process Variability Monitoring

Nabila Moubdi , Robin M. Wilson , Sylvain Engels , Nadine Azemard , Philippe Maurine
DATE: Design, Automation and Test in Europe, Apr 2009, Nice, France
Communication dans un congrès lirmm-00374368v1
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Assessment of the Immunity of Unshielded Multicore Integrated Circuits to Near Field Injection

Ali Alaeldine , Thomas Ordas , Richard Perdriau , Philippe Maurine , Mohamed Ramdani
International Zurich Symposium on Electromagnetic Compatibility, France. pp.361-364
Communication dans un congrès lirmm-00394411v1

An Innovative Timing Slack Monitor for Variation Tolerant Circuits

Bettina Rebaud , Marc Belleville , Edith Beigné , Michel Robert , Philippe Maurine
ICICDT: International Conference on IC Design & Technology, May 2009, Austin, TX, United States. pp.215-218, ⟨10.1109/ICICDT.2009.5166299⟩
Communication dans un congrès lirmm-00371174v1

Interpretation of SSTA Results

Zeqin Wu , Nadine Azemard , Philippe Maurine , Gilles R. Ducharme
FTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Switzerland
Communication dans un congrès lirmm-00374060v1

Evaluation of Countermeasures against Electromagnetic Analysis

Thomas Ordas , Ali Alaeldine , Philippe Maurine , Richard Perdriau , Lionel Torres
EMC Europe: Electromagnetic Compatibility, Jun 2009, Athens, Greece. ⟨10.1109/EMCEUROPE.2009.5189724⟩
Communication dans un congrès hal-01271857v1

On-Chip Timing Slack Monitoring

Bettina Rebaud , Marc Belleville , Edith Beigné , Michel Robert , Philippe Maurine
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2009, Florianopolis, Brazil. pp.89-94, ⟨10.1109/VLSISOC.2009.6041336⟩
Communication dans un congrès lirmm-00429350v1

Fingerprinting Hardware Security Module Using ICs Radiations

Lionel Torres , Victor Lomné , Philippe Maurine , Amine Dehbaoui
EMC Compo 2009 - 7th International Workshop on Electromagnetic Compatibility of Integrated Circuits, Nov 2009, Toulouse, France
Communication dans un congrès lirmm-00433331v1
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Product On-Chip Process Compensation for Low Power and Yield Enhancement

Nabila Moubdi , Philippe Maurine , Robin M. Wilson , Nadine Azemard , Vincent Dumettier
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.247-255, ⟨10.1007/978-3-642-11802-9_29⟩
Communication dans un congrès lirmm-00433504v1

Etude de l'effet du boîtier sur l'immunité en champ proche des circuits intégrés

Ali Alaeldine , Thomas Ordas , Richard Perdriau , Philippe Maurine , Mohamed Ramdani
Telecom 2009 & 6èmes JFMMA, Mar 2009, Agadir, Maroc. 4 p
Communication dans un congrès hal-00522766v1
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Interpreting SSTA Results with Correlation

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.16-25, ⟨10.1007/978-3-642-11802-9_6⟩
Communication dans un congrès lirmm-00433505v1

Evaluation on FPGA of Triple Rail Logic Robustness Against DPA and DEMA

Victor Lomné , Philippe Maurine , Lionel Torres , Michel Robert , Rafael Soares
DATE: Design, Automation and Test in Europe, 2009, Nice, France. pp.634-639, ⟨10.1109/DATE.2009.5090744⟩
Communication dans un congrès lirmm-00372847v1
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Enhancing Electromagnetic Attacks using Spectral Coherence based Cartography

Amine Dehbaoui , Victor Lomné , Philippe Maurine , Lionel Torres , Michel Robert
VLSI-SoC 2009 - 17th IFIP International Conference on Very Large Scale Integration, Oct 2009, Florianopolis, Brazil. pp.11-16, ⟨10.1109/VLSISOC.2009.6041323⟩
Communication dans un congrès lirmm-00429342v1
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Triple Rail Logic Robustness against DPA

Victor Lomné , Thomas Ordas , Philippe Maurine , Lionel Torres , Michel Robert
ReConFig 2008 - International Conference on Reconfigurable Computing and FPGAs, Dec 2008, Cancun, Mexico. pp.415-420, ⟨10.1109/ReConFig.2008.75⟩
Communication dans un congrès lirmm-00350573v1

Prototyping Secure Triple Track Logic (STTL) Robustness Against DPA & DEMA on FPGA

Victor Lomné , Rafael A. Soares , Thomas Ordas , Philippe Maurine , Lionel Torres
CryptArchi: Cryptographic Architectures, Jun 2008, Tregastel, France
Communication dans un congrès lirmm-00373539v1

SSTA with Correlations Considering input Slope and Output Load Variations

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2008, Rhodes Island, Greece. pp.164-167
Communication dans un congrès lirmm-00332757v1

SSTA with Structure Correlations Considering input Slope and Output Load Variations

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
GDR SOC-SIP, Jun 2008, Paris, France. pp.3
Communication dans un congrès lirmm-00340231v1

SSTA Considering Switching Process Induced Correlations

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
APCCAS: Asia Pacific Conference on Circuits and System, Nov 2008, Macao, China. pp.562-565, ⟨10.1109/APCCAS.2008.4746085⟩
Communication dans un congrès lirmm-00340564v1

Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier

Bettina Rebaud , Marc Belleville , Christian Bernard , Zeqin Wu , Michel Robert
ISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩
Communication dans un congrès lirmm-00280809v1

Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects

Michael Yap San Min , Philippe Maurine , Magali Bastian Hage-Hassan , Michel Robert
ISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, pp.310-315
Communication dans un congrès lirmm-00280716v1
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Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétique

Bettina Rebaud , Zeqin Wu , Marc Belleville , Christian Bernard , Michel Robert
JNRDM 2008 - 11e Journées Nationales du Réseau Doctoral de Microélectronique, May 2008, Bordeaux, France
Communication dans un congrès lirmm-00281175v2
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Evaluating the Robustness of Secure Triple Track Logic Through Prototyping

Rafael A. Soares , Ney Calazans , Victor Lomné , Philippe Maurine , Lionel Torres
SBCCI'08: Symposium on Integrated Circuits and Systems Design, Sep 2008, Gramado, Brazil, France. pp.193-198, ⟨10.1145/1404371.1404425⟩
Communication dans un congrès lirmm-00373516v1
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Near-field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits

Thomas Ordas , Mathieu Lisart , Etienne Sicard , Philippe Maurine , Lionel Torres
PATMOS: Power and Timing Modeling Optimization and Simulation, Sep 2008, Lisbon, Portugal. pp.229-236, ⟨10.1007/978-3-540-95948-9_23⟩
Communication dans un congrès lirmm-00394395v1
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A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM

Michael Yap San Min , Philippe Maurine , Magali Bastian Hage-Hassan , Michel Robert
DELTA 2008 - 4th IEEE International Symposium on Electronic Design, Test and Applications, Jan 2008, Hong Kong, China. pp.107-110, ⟨10.1109/DELTA.2008.72⟩
Communication dans un congrès lirmm-00243966v1

Conditional Moments based SSTA Considering Switching Process Induced Correlations

Zeqin Wu , Philippe Maurine , Gilles R. Ducharme , Nadine Azemard
DCIS: Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. pp.70-77
Communication dans un congrès lirmm-00340221v1
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Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numérique

Bettina Rebaud , Marc Belleville , Christian Bernard , Zeqin Wu , Michel Robert
FTFC: Faible Tension - Faible Consommation, May 2008, Louvain-La-Neuve, Belgique
Communication dans un congrès lirmm-00283731v1

SSTA Considering Effects of Structure Correlations, Input Slope and Output Load Variations

Zeqin Wu , Philippe Maurine , Gilles R. Ducharme , Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2008, Louvain-la-Neuve, Belgium. pp.39-43
Communication dans un congrès lirmm-00288537v1

Une Famille d'Additionneurs Asynchrones CMOS Bundled Data à Temps de Calcul Dépendant aux Données

Robin Perrot , Nadine Azemard , Philippe Maurine
FTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.75-80
Communication dans un congrès lirmm-00178466v1
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Process Variability Considerations in the Design of an eSRAM

Michael Yap San Min , Philippe Maurine , Michel Robert , Magali Bastian Hage-Hassan
MTDT 2007 - IEEE International Workshop on Memory Technology, Design and Testing, Dec 2007, Taipei, Taiwan. pp.23-26, ⟨10.1109/MTDT.2007.4547609⟩
Communication dans un congrès lirmm-00275258v1
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A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates

Alin Razafindraibe , Philippe Maurine
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.394-403, ⟨10.1007/978-3-540-74442-9_38⟩
Communication dans un congrès lirmm-00175108v1
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Méthodologie d'estimation de l'influence de la variabilité sur un opérateur numérique

Bettina Rebaud , Marc Belleville , Christian Bernard , Michel Robert , Philippe Maurine
FTFC 2007 - 6e journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France
Communication dans un congrès lirmm-00204621v1

Process Variabilities and Performances in a 90nm embedded SRAM

Michael Yap San Min , Philippe Maurine , Magali Bastian Hage-Hassan , Michel Robert
IEEE International Integrated Reliability Workshop, Oct 2007, pp.050-055
Communication dans un congrès lirmm-00198373v1

Variabilité de Process et Performances des Mémoires SRAM Embarquées

Michael Yap San Min , Philippe Maurine , Magali Bastian Hage-Hassan , Michel Robert
FTFC'07: 6èmes Journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France, pp.7-11
Communication dans un congrès lirmm-00178319v1

A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation

Vincent Migairou , Robin Wilson , Sylvain Engels , Zeqin Wu , Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.19-25
Communication dans un congrès lirmm-00178454v1

Improvement of Dual Rail Logic as a Countermeasure Against DPA

Hanitriniaina Razafindraibe , Michel Robert , Philippe Maurine
VLSI-SoC 2007 - IFIP International Conference on Very Large Scale Integration, Oct 2007, Atlanta, GA, United States. pp.270-275, ⟨10.1109/VLSISOC.2007.4402510⟩
Communication dans un congrès lirmm-00186174v1

A Simple Statistical Timing Analysis Flow and its Application to Timing Margin Evaluation

Vincent Migairou , Robin Wilson , Sylvain Engels , Zeqin Wu , Nadine Azemard
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.138-147, ⟨10.1007/978-3-540-74442-9_14⟩
Communication dans un congrès lirmm-00175076v1

Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops

Benoit Lasbouygues , Robin M. Wilson , Nadine Azemard , Philippe Maurine
DATE: Design, Automation and Test in Europe, Mar 2007, Nice, France. ⟨10.1109/DATE.2007.364426⟩
Communication dans un congrès lirmm-00178525v1
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Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA

Alin Razafindraibe , Michel Robert , Philippe Maurine
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.340-351, ⟨10.1007/978-3-540-74442-9_33⟩
Communication dans un congrès lirmm-00175100v1

Circuit Performance Optimization under Delay Constraints

Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard
DCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain
Communication dans un congrès lirmm-00117119v1

Exploration of the Area-Latency Tradeoff of Asynchronous CMOS data Dependent Adders

Robin Perrot , Philippe Maurine , Nadine Azemard
DCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain
Communication dans un congrès lirmm-00117102v1

Timing Analysis in Presence of Voltage Drops and Temperature Gradients

Benoit Lasbouygues , Robin M. Wilson , Nadine Azemard , Philippe Maurine
TAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. pp.28-34
Communication dans un congrès lirmm-00106705v1

Timing Analysis in Presence of Supply Voltage and Temperature Variations

Benoit Lasbouygues , Robin M. Wilson , Nadine Azemard , Philippe Maurine
ISPD: International Symposium on Physical Design, Apr 2006, San Jose, CA, United States. pp.10-16, ⟨10.1145/1123008.1123012⟩
Communication dans un congrès lirmm-00102760v1
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Une Famille d'Additionneur Asynchrones CMOS à Temps de Calcul Dépendant de Données

Robin Perrot , Nadine Azemard , Philippe Maurine
JNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. pp.469-472
Communication dans un congrès lirmm-00102842v1
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Statistical Characterization of Library Timing Performance

Vincent Migairou , Robin P. Wilson , Sylvain Engels , Nadine Azemard , Philippe Maurine
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2006, Montpellier, France. pp.468-476, ⟨10.1007/11847083_45⟩
Communication dans un congrès lirmm-00093233v1

Request-Skip Adders: CMOS Standard Cell Data Dependent Adders

Robin Perrot , Nadine Azemard , Philippe Maurine
ICECS: International Conference on Electronics, Circuits and Systems, Dec 2006, Nice, France. pp.510-513, ⟨10.1109/ICECS.2006.379837⟩
Communication dans un congrès lirmm-00130195v1
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Security Evaluation of Dual Rail Logic Against DPA Attacks

Hanitriniaina Razafindraibe , Philippe Maurine , Michel Robert , Marc Renaudin
VLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration, Oct 2006, Nice, France. pp.181-186, ⟨10.1109/VLSISOC.2006.313230⟩
Communication dans un congrès lirmm-00109692v1

Circuit Sizing Method under Delay Constraint

Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard
ISCAS: International Symposium on Circuits and Systems, May 2006, Island of Kos, Greece. pp.5123-5126, ⟨10.1109/ISCAS.2006.1693785⟩
Communication dans un congrès lirmm-00106911v1

Additionneurs RCA Data Dependent Micropipelines

Robin Perrot , Nadine Azemard , Philippe Maurine
FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.183-188
Communication dans un congrès lirmm-00106005v1
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Low Power Oriented CMOS Circuit Optimization Protocol

Alexandre Verle , Xavier Michel , Nadine Azemard , Philippe Maurine , Daniel Auvergne
DATE 2005 - 8th Design, Automation and Test in Europe Conference and Exhibition, Mar 2005, Munich, Germany. pp.640-645, ⟨10.1109/DATE.2005.202⟩
Communication dans un congrès lirmm-00106452v1
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Speed Indicators for Circuit Optimization

Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.618-628, ⟨10.1007/11556930_63⟩
Communication dans un congrès lirmm-00106076v1

Protocole d'Optimisation de Circuit CMOS Orienté Basse Puissance

Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.17-22
Communication dans un congrès lirmm-00106002v1

Méthode de Conception de Primitives Asynchrones Double Rail

Alin Razafindraibe , Michel Robert , Philippe Maurine
FTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.23-27
Communication dans un congrès lirmm-00106003v1

Optimization Protocol Based on Low Power Metrics

Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard
IWLS: International Workshop on Logic Synthesis, Jun 2005, Lake Arrowhead Resort, CA, United States. pp.288-293
Communication dans un congrès lirmm-00106018v1

Path Optimization Protocol Based on Speed Low Power Metrics

Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard
EUROCON: International Conference on "Computer as a Tool", Nov 2005, Belgrade, Serbia. pp.523-526, ⟨10.1109/EURCON.2005.1629980⟩
Communication dans un congrès lirmm-00106428v1

Asynchronous Dual rail Cells to Secure Cryptosystem Against Side Channel Attacks

Alin Razafindraibe , Michel Robert , Marc Renaudin , Philippe Maurine
SAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia-Antipolis
Communication dans un congrès lirmm-00106539v1
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Temperature Dependency in UDSM Process

Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.693-703, ⟨10.1007/11556930_71⟩
Communication dans un congrès lirmm-00106077v1

Synthèse Physique et Optimisation des Performances au Niveau Transistor

Alexis Landrault , Alexandre Verle , Philippe Maurine , Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.91-95
Communication dans un congrès lirmm-00106004v1

Design of Compact Dual Rail Asynchronous Primitives

Alin Razafindraibe , Michel Robert , Philippe Maurine
DCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, 2005, Lisbonne, Portugal
Communication dans un congrès lirmm-00106434v1

Circuit Optimization Based on Speed Indicators

Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard
ICECS: International Conference on Electronics, Circuits and Systems, Dec 2005, Gammarth, Tunisia. pp.167-170, ⟨10.1109/icecs.2005.4633585⟩
Communication dans un congrès lirmm-00106439v1
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A Method to Design Compact Dual-rail Asynchronous Primitives

Alin Razafindraibe , Michel Robert , Marc Renaudin , Philippe Maurine
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.571-580, ⟨10.1007/11556930_58⟩
Communication dans un congrès hal-00105846v1

La Technologie Asynchrone QDI pour la Sécurité des Cryptosystèmes

Alin Razafindraibe , Philippe Maurine , Michel Robert
JNRDM 2005 - 8e Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France. pp.461-463
Communication dans un congrès lirmm-00106530v1

Ripple Carry Adder for Micropipeline Circuits

Robin Perrot , Nadine Azemard , Philippe Maurine
DCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal
Communication dans un congrès lirmm-00106075v1
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Definition of P/N Width Ratio for CMOS Standard Cell Library

Alexandre Verle , Philippe Maurine , Nadine Azemard , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.769-773
Communication dans un congrès lirmm-00108933v1
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RC on-chip interconnect Performance revisited

Philippe Maurine , Nadine Azemard , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.809-814
Communication dans un congrès lirmm-00108934v1
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Physical Extension of the Logical Effort Model

Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.838-848, ⟨10.1007/978-3-540-30205-6_86⟩
Communication dans un congrès lirmm-00108895v1
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Temperature Dependence in Low Power CMOS UDSM Process

Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.111-118, ⟨10.1007/978-3-540-30205-6_13⟩
Communication dans un congrès lirmm-00108893v1
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Design Optimization with Automated Cell Generation

Alexis Landrault , Nadine Azemard , Philippe Maurine , Michel Robert , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.722-731, ⟨10.1007/978-3-540-30205-6_74⟩
Communication dans un congrès lirmm-00108894v1

Automatic Layout Synthesis Based Performance Optimization

Alexis Landrault , Nadine Azemard , Philippe Maurine , Michel Robert , Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85
Communication dans un congrès lirmm-00108654v1
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Optimization Protocol Based on Performance Metric

Xavier Michel , Alexandre Verle , Nadine Azemard , Philippe Maurine , Daniel Auvergne
DCIS 2004 - 19th International Conference on Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.964-968
Communication dans un congrès lirmm-00108935v1
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Delay Bound Based CMOS Gate Sizing Technique

Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne
ISCAS: International Symposium on Circuits and Systems, May 2004, Vancouver, BC, Canada. pp.189-192, ⟨10.1109/ISCAS.2004.1329494⟩
Communication dans un congrès lirmm-00108856v1
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Performance Metric Based Optimization Protocol

Xavier Michel , Alexandre Verle , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.100-109, ⟨10.1007/978-3-540-30205-6_12⟩
Communication dans un congrès lirmm-00108892v1

Conception et Modélisation de Briques Elémentaires CMOS

Guy Cathébras , S. Dussausay , Michel Robert , Philippe Maurine
CNFM'04 : 8ème Journées Pédagogiques du Comité National de Formation en Microélectronique, 2004, Saint-Malo, France. pp.35-37
Communication dans un congrès lirmm-00108672v1

Secured Structures for Secured Asynchronous QDI Circuits

Alin Razafindraibe , Michel Robert , Bertrand Folco , Philippe Maurine , Ghislain Fraidy Bouesse
DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France
Communication dans un congrès hal-01393250v1
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CMOS Gate Sizing under Delay Constraint

Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Torino, Italy. pp.60-69, ⟨10.1007/978-3-540-39762-5_8⟩
Communication dans un congrès lirmm-00244021v1

TAL : Une Bibliothèque de Cellules pour le Design de Circuits Asynchrones QDI

Philippe Maurine , Jean-Baptiste Rigaud , Ghislain Fraidy Bouesse , Gilles Sicard , Marc Renaudin
FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.41-49
Communication dans un congrès lirmm-00269521v1
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Dimensionnement de Portes CMOS Sous Contrainte de Délai

Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne
FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.111-117
Communication dans un congrès lirmm-00269522v1
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Static Implementation of QDI Asynchronous Primitives

Philippe Maurine , Jean-Baptiste Rigaud , Ghislain Fraidy Bouesse , Gilles Sicard , Marc Renaudin
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. pp.181-191, ⟨10.1007/978-3-540-39762-5_20⟩
Communication dans un congrès lirmm-00269567v1
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Représentation Unifiée des Performances Temporelles d'une Bibliothèque de Cellules Standards

Benoit Lasbouygues , J. Schindler , Sylvain Engels , Philippe Maurine , Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.119-124
Communication dans un congrès lirmm-00269519v1
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Définition d'une Métrique d'Insertion de Buffers

Xavier Michel , Alexandre Verle , Nadine Azemard , Philippe Maurine , Daniel Auvergne
FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.131-136
Communication dans un congrès lirmm-00269520v1
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Continuous Representation of the Performance of a CMOS Library

Benoit Lasbouygues , J. Schindler , Sylvain Engels , Philippe Maurine , Xavier Michel
ESSCIRC: European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal. pp.595-598, ⟨10.1109/ESSCIRC.2003.1257205⟩
Communication dans un congrès lirmm-00239459v1

Timing Performance Representation of a CMOS Standard Cell Library

Benoit Lasbouygues , J. Schindler , Sylvain Engels , Philippe Maurine , Xavier Michel
DCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. pp.83-88
Communication dans un congrès lirmm-00239460v1

Metric Definition for Circuit Speed Optimization

Xavier Michel , Alexandre Verle , Nadine Azemard , Philippe Maurine , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. pp.451-460
Communication dans un congrès lirmm-00269568v1

Metric Definition for Circuit Speed Optimization

Xavier Michel , Alexandre Verle , Philippe Maurine , Nadine Azemard , Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, May 2003, Laguna Beach, CA, United States
Communication dans un congrès lirmm-00269689v1

Gate Speed Improvement at Minimal Power Dissipation

Philippe Maurine , Xavier Michel , Nadine Azemard , Daniel Auvergne
APPCAS: Asia-Pacific Conference on Circuits and Systems, Oct 2002, Denpasar, Bali, pp.278-282
Communication dans un congrès lirmm-00239453v1

Defining the Maximum Speed of CMOS Gate Library

Philippe Maurine , Nadine Azemard , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.81-86
Communication dans un congrès lirmm-00239455v1
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Structure Independent Representation of Output Transition Time for CMOS Library

Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2002, Seville, Spain. pp.247-257, ⟨10.1007/3-540-45716-X_25⟩
Communication dans un congrès lirmm-00244012v1

Metric Definition for Buffer Insertion

Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.307-312
Communication dans un congrès lirmm-00239458v1
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Evaluation et Optimisation de Chemins Combinatoires

Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne
Colloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.173-176
Communication dans un congrès lirmm-00269329v1

Performance Indicators for Designing CMOS Logic

Philippe Maurine , Nadine Azemard , Daniel Auvergne
ICM: International Conference on Microelectronics, Oct 2001, Rabat, Morocco. pp.99-102, ⟨10.1109/ICM.2001.997497⟩
Communication dans un congrès lirmm-00239446v1

Technological Assignment for a Minimal Power Consumption

Philippe Maurine , Nadine Azemard , Daniel Auvergne
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.236-241
Communication dans un congrès lirmm-00239450v1

Timing Closure Management based on Delay Bound Determination

Nadine Azemard , Michel Aline , Philippe Maurine , Daniel Auvergne
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.430-434
Communication dans un congrès lirmm-00239452v1
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Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination

Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2001, Yverdon-Les-Bains, Switzerland. pp.5.3.1-5.3.10
Communication dans un congrès lirmm-00244010v1

Delay Bound Determination for Timing Closure on CMOS Circuits

Nadine Azemard , Michel Aline , Philippe Maurine , Daniel Auvergne
IWLS: International Workshop on Logic and Synthesis, Jun 2001, Granlibakken Conference Center, United States. pp.96-100
Communication dans un congrès lirmm-00244007v1

Full Analyttical Model for delay Performance Estimation in Submicron CMOS

Philippe Maurine , Nadine Azemard , Daniel Auvergne
MIXDES: Mixed Design of Integrated Circuits and Systems, Jun 2001, Zakopane, Poland. pp.355-359
Communication dans un congrès lirmm-00239444v1

Switching Current Modeling in CMOS Inverter for Speed and Power Estimation

Philippe Maurine , Régis Poirier , Nadine Azemard , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2001, Porto, Portugal. pp.618-622
Communication dans un congrès lirmm-00239448v1
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Méthode Itérative pour l’Amélioration de la Prédiction des Performances des Circuits Intégrés

Gwenael Chaillou , Philippe Maurine , Jean-Marc J.-M. Galliere , Nadine Azemard
15e Colloque National du GDR SoC², Jun 2021, Rennes, France
Poster de conférence lirmm-03358670v1

Statistical Timing Characterization

Nadine Azemard , Zeqin Wu , Philippe Maurine , Gilles R. Ducharme
SoC: System on Chip, Oct 2012, Tampere, Finland. International Symposium on System on Chip, 2012, ⟨10.1109/ISSoC.2012.6376360⟩
Poster de conférence lirmm-00762107v1

A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis

Florent Bruguier , Pascal Benoit , Philippe Maurine , Lionel Torres
FPL: Field Programmable Logic and Applications, Sep 2011, Crête, Greece. 21st International Conference on Field Programmable Logic and Applications, 2011
Poster de conférence lirmm-00616954v1
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Towards Autonomous Scalable Integrated Systems

Pascal Benoit , Gilles Sassatelli , Philippe Maurine , Lionel Torres , Nadine Azemard
Design Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. ⟨10.1007/978-94-007-1125-9_4⟩
Chapitre d'ouvrage lirmm-01399454v1
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Side Channel Attacks

Victor Lomné , Amine Dehbaoui , Philippe Maurine , Michel Robert , Lionel Torres
Security Trends for FPGAS
From Secured to Secure Reconfigurable Systems
, Springer, pp.47-72, 2011, 978-94-007-1337-6. ⟨10.1007/978-94-007-1338-3_3⟩
Chapitre d'ouvrage lirmm-00809329v1
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Security FPGA Analysis

Eduardo Wanderley , Romain Vaslin , Jérémie Crenne , Pascal Cotret , Jean-Philippe Diguet
Security Trends for FPGAS
From Secured to Secure Reconfigurable Systems
, pp.7-46, 2011, ⟨10.1007/978-94-007-1338-3_2⟩
Chapitre d'ouvrage lirmm-00809327v1

Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks

Hanitriniaina Razafindraibe , Michel Robert , Philippe Maurine
Nadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.634-644, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. ⟨10.1007/11847083_44⟩
Chapitre d'ouvrage lirmm-00109844v1

Modeling for Designing in Deep Sub-Micron Technologies

Daniel Auvergne , Philippe Maurine , Nadine Azemard
PIGUET C. Low-Power Electronics Design, CPR Press, 2004, 0-8493-1941-2
Chapitre d'ouvrage lirmm-00109162v1
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Gate Sizing for Low Power Design

Philippe Maurine , Nadine Azemard , Daniel Auvergne
SOC Design Methodologies, 90, Kluwer Academic Publishers, pp.301-312, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_26⟩
Chapitre d'ouvrage lirmm-00239359v1
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Feasible delay Bound Definition

Nadine Azemard , Michel Aline , Philippe Maurine , Daniel Auvergne
SOC Design Methodologies, 90, Kluwer Academic Publishers, pp.325-335, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_40⟩
Chapitre d'ouvrage lirmm-00239363v1