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216

Publications of Philippe Maurine


Article dans une revue28 documents

  • Gilles Ducharme, Philippe Maurine. Estimating the Signal-to-Noise ratio under repeated sampling of the same centered signal: applications to side-channel attacks on a cryptoprocessor. IEEE Transactions on Information Theory, Institute of Electrical and Electronics Engineers, In press, 〈10.1109/TIT.2018.2851217〉. 〈hal-01830075〉
  • Ibrahima Diop, Yanis Linge, Thomas Ordas, Pierre-Yvan Liardet, Philippe Maurine. From theory to practice: horizontal attacks on protected implementations of modular exponentiations. Journal of Cryptographic Engineering, Springer, In press, 〈10.1007/s13389-018-0181-1〉. 〈lirmm-01713147〉
  • Maxime Lecomte, Jacques Jean-Alain Fournier, Philippe Maurine. An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit Identification. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2017, 25 (12), pp.3317-3330. 〈10.1109/TVLSI.2016.2627525〉. 〈lirmm-01430925〉
  • Sébastien Ordas, Ludovic Guillaume-Sage, Philippe Maurine. Electromagnetic fault injection: the curse of flip-flops. Journal of Cryptographic Engineering, Springer, 2017, 7 (3), pp.183-197. 〈10.1007/s13389-016-0128-3〉. 〈lirmm-01430913〉
  • Raphael Andreoni Camponogara-Viera, Rodrigo Possamai Bastos, Jean-Max Dutertre, Philippe Maurine, Rodrigo Iga Jadue. Method for evaluation of transient-fault detection techniques. Microelectronics Reliability, Elsevier, 2017, 76-77, pp.68-74. 〈10.1016/j.microrel.2017.07.007〉. 〈lirmm-01690185〉
  • Mathieu Carbone, Yannick Teglia, Gilles R. Ducharme, Philippe Maurine. Mutual information analysis: higher-order statistical moments, efficiency and efficacy. Journal of Cryptographic Engineering, Springer, 2016, Journal of Cryptographic Engineering, 5 (20), 〈http://link.springer.com/journal/13389〉. 〈10.1007/s13389-016-0123-8〉. 〈lirmm-01285152〉
  • Guilherme Perin, Laurent Imbert, Philippe Maurine, Lionel Torres. Vertical and horizontal correlation attacks on RNS-based exponentiations. Journal of Cryptographic Engineering, Springer, 2015, 5 (3), pp.171-185. 〈10.1007/s13389-015-0095-0〉. 〈lirmm-01269799〉
  • Lionel Vincent, Edith Beigné, Suzanne Lesecq, Julien Mottin, David Coriat, et al.. Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures. IEEE Transactions on Circuits and Systems Part 1 Fundamental Theory and Applications, Institute of Electrical and Electronics Engineers (IEEE), 2014, Part I: Regular Papers, 61 (6), pp.1741-1754. 〈10.1109/TCSI.2013.2290850〉. 〈lirmm-01096015〉
  • Sébastien Tiran, Sébastien Ordas, Yannick Teglia, Michel Agoyan, Philippe Maurine. A model of the leakage in the frequency domain and its application to CPA and DPA. Journal of Cryptographic Engineering, Springer, 2014, 4 (3), pp.197-212. 〈10.1007/s13389-014-0074-x〉. 〈lirmm-01096000〉
  • Philippe Maurine, Amine Dehbaoui, Victor Lomné, Thomas Ordas, Lionel Torres, et al.. Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2012, 20 (3), pp.573-577. 〈http://ieeexplore.ieee.org/xpl/tocresult.jsp?reload=true&isnumber=6151946〉. 〈10.1109/TVLSI.2011.2104984〉. 〈lirmm-00761786〉
  • Zeqin Wu, Nadine Azemard, Gilles R. Ducharme, Philippe Maurine. Delay-correlation-aware SSTA based on conditional moments. Microelectronics Journal, Elsevier, 2012, 43 (4), pp.263-273. 〈10.1016/j.mejo.2012.01.003〉. 〈lirmm-00761821〉
  • Bruno Vaquie, Sébastien Tiran, Philippe Maurine. Secure D Flip-Flop Against Side ChannelL Attacks. IET Circuits, Devices & Systems, Institution of Engineering and Technology, 2012, 6 (5), pp.347-354. 〈10.1049/iet-cds.2011.0345〉. 〈lirmm-00762016〉
  • Philippe Maurine, Rafael I. Soares, Ney L. V. Calazans, Victor Lomné, Amine Dehbaoui, et al.. A GALS Pipeline DES Architecture to Increase Robustness Against CPA and CEMA Attacks. Journal of Integrated Circuits and Systems, Brazilian Microelectronics Society, 2011, 5, pp.001-010. 〈lirmm-00607871〉
  • Philippe Maurine, Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, et al.. Timing Slack Monitoring under Process and Environmental Variations: Application to a DSP Performance Optimization. Microelectronics Journal, Elsevier, 2011, 42 (5), pp.718-732. 〈lirmm-00607877〉
  • Rafael Soares, Ney Calazans, Fernando Moraes, Philippe Maurine, Lionel Torres. A Robust Architectural Approach for Cryptographic Algorithms using GALS Pipelines. IEEE Design & Test, IEEE, 2011, 28 (5), pp.62-71. 〈10.1109/MDT.2011.69〉. 〈lirmm-00596741〉
  • Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Sylvain Engels, et al.. On-Chip Process Variability Monitoring Flow. Journal of Low Power Electronics, American Scientific Publishers, 2010, 6 (4), pp.601-606. 〈10.1166/jolpe.2010.1109〉. 〈lirmm-00546368〉
  • Amine Debhaoui, Victor Lomné, Philippe Maurine, Lionel Torres. Magnitude Squared Incoherence EM Analysis for Integrated Cryptographic modules Localization. Electronics Letters, IET, 2009, N/A, pp.N/A. 〈lirmm-00402776〉
  • Victor Lomné, Amine Dehbaoui, Thomas Ordas, Philippe Maurine, Lionel Torres, et al.. Secure Triple Track Logic Robustness Against Differential Power and EM Analyses. Journal of Integrated Circuits and Systems, Brazilian Microelectronics Society, 2009, 4, pp.20-28. 〈lirmm-00595001〉
  • Sylvain Engels, Robin Wilson, Nadine Azemard, Philippe Maurine, Vincent Migairou. Timing Margin Evaluation with a Simple Statistical Timing Analysis Flow. Journal of Embedded Computing, IOS Press, 2009, 3 (3), pp.221-229. 〈lirmm-00371162〉
  • Benoit Lasbouygues, R. Wilson, Nadine Azemard, Philippe Maurine. Temperature and Voltage Aware Timing Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2007, 26 (4), pp.801-815. 〈lirmm-00178921〉
  • Benoit Lasbouygues, S. Engels, R. Wilson, Philippe Maurine, Nadine Azemard, et al.. Logical Effort Model Extension to Propagation Delay Representation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2006, 25 (9), pp.1677-1684. 〈lirmm-00104315〉
  • S. Engels, R. Wilson, Nadine Azemard, Philippe Maurine. A Comprehensive Performance Macro-Modeling of on-Chip RC Interconnects Considering Line Shielding Effects. Integration, the VLSI Journal, Elsevier, 2006, 39, pp.433-456. 〈lirmm-00106854〉
  • Alin Razafindraibe, Michel Robert, Philippe Maurine. Compact and Secured Primitives for the Design of Asynchronous Circuits. Journal of Low Power Electronics, American Scientific Publishers, 2005, 1 (1), pp.20-26. 〈lirmm-00105365〉
  • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Delay Bounds Based Constraint Distribution Method. IEE Proceedings - Computers and Digital Techniques (1994-2006), Institution of Engineering and Technology, 2005, 152 (6), pp.765-770. 〈10.1049/ip-cdt:20050026〉. 〈lirmm-00105370〉
  • Philippe Maurine, Mustapha Rezzoug, Nadine Azemard, Daniel Auvergne. Transition Time Modeling in Deep Submicron CMOS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2002, 21 (11), pp.1352-1363. 〈lirmm-00268437〉
  • Philippe Maurine, Mustapha Rezzoug, Nadine Azemard, Daniel Auvergne. Transition Time Modeling in Deep Submicron CMOS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2002, 21 (11), pp.1352- 1363. 〈lirmm-00239324〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. General Representation of CMOS Structure Transition time for Timing Library Representation. Electronics Letters, IET, 2002, 38 (4), pp.175-177. 〈lirmm-00239318〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. General Representation of CMOS Structure Transition Time for Timing Library Representation. Electronics Letters, IET, 2002, 38 (4), pp.175-177. 〈lirmm-00268588〉

Communication dans un congrès170 documents

  • Raphael Andreoni Camponogara-Viera, Jean-Max Dutertre, Philippe Maurine, Rodrigo Possamai Bastos. Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits. ISPD: International Symposium on Physical Design, Mar 2018, Monterey, CA, United States. ACM Press, International Symposium on Physical Design, pp.160-167, 2018, 〈http://www.ispd.cc〉. 〈10.1145/3177540.3178243〉. 〈lirmm-01743368〉
  • Maxime Cozzi, Jean-Marc Galliere, Philippe Maurine. Exploiting Phase Information in Thermal Scans for Stealthy Trojan Detection. DSD: Digital System Design, Aug 2018, Prague, Slovakia. Euromicro Conference on Digital System Design, 2018, 〈http://dsd-seaa2018.fit.cvut.cz/dsd/〉. 〈lirmm-01872499〉
  • Maxime Cozzi, Philippe Maurine, Jean-Marc Galliere. Thermal Scans for Detecting Hardware Trojans. COSADE: Constructive Side-Channel Analysis and Secure Design, Apr 2018, Singapour, Singapore. 9th International Workshop on Constructive Side-Channel Analysis and Secure Design, LNCS (10815), pp.117-132, 2018, COSADE 2018. 〈10.1007/978-3-319-89641-0_7〉. 〈lirmm-01823444〉
  • Raphael Andreoni Camponogara-Viera, Rodrigo Possamai Bastos, Jean-Max Dutertre, Philippe Maurine. Method for evaluation of transient-fault detection techniques. ESREF: European Symposium on Reliability of Electron devices, Failure physics and analysis, Sep 2017, Bordeaux, France. 2017. 〈hal-01721081〉
  • Raphael Andreoni Camponogara-Viera, Philippe Maurine, Jean-Max Dutertre, Rodrigo Possamai Bastos. Importance of IR Drops on the Modeling of Laser-Induced Transient Faults. SMACD: Synthesis, Modeling, Analysis and simulation methods and applications to Circuit Design, Jun 2017, Giardini Naxos, Taormina, Italy. IEEE, 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, 2017, 〈10.1109/SMACD.2017.7981593〉. 〈hal-01721087〉
  • Philippe Maurine, Sylvain Guilley. Impacts of Technology Trends on Physical Attacks?. COSADE: Constructive Side-Channel Analysis and Secure Design, Apr 2017, Paris, France. International Workshop on Constructive Side-Channel Analysis and Secure Design, LNCS (10348), pp.190-206, 2017, 〈10.1007/978-3-319-64647-3_12〉. 〈lirmm-01690188〉
  • Raphael Andreoni Camponogara-Viera, Jean-Max Dutertre, Rodrigo Possamai Bastos, Philippe Maurine. Role of Laser-Induced IR Drops in the Occurrence of Faults: Assessment and Simulation. DSD: Digital System Design, Aug 2017, Vienna, Austria. IEEE, Euromicro Conference on Digital System Design, 2017, 〈http://dsd-seaa2017.ocg.at/dsd2017.html〉. 〈10.1109/DSD.2017.43〉. 〈lirmm-01699776〉
  • Noemie Beringuier-Boher, Marc Lacruche, David El-Baze, Jean-Max Dutertre, Jean-Baptiste Rigaud, et al.. Body Biasing Injection Attacks in Practice . CS2: Cryptography and Security in Computing Systems, Jan 2016, Prague, Czech Republic. ACM, 3rd Workshop on Cryptography and Security in Computing Systems (CS2) in conjonction with 11th High Performance and Embedded Architecture and Compilation (HiPEAC) Conference., pp.49-54, 2016, 〈http://www.cs2.deib.polimi.it/main2016.html〉. 〈10.1145/2858930.2858940〉. 〈lirmm-01434143〉
  • David El-Baze, Jean-Baptiste Rigaud, Philippe Maurine. An Embedded Digital Sensor against EM and BB Fault Injection. FDTC: Fault Diagnosis and Tolerance in Cryptography, Aug 2016, Santa Barbara, CA, United States. IEEE, Workshop on Fault Diagnosis and Tolerance in Cryptography, pp.78-86, 2016, 〈http://conferenze.dei.polimi.it/FDTC16/〉. 〈10.1109/FDTC.2016.14〉. 〈lirmm-01434028〉
  • El-Baze David, Jean-Baptiste Rigaud, Philippe Maurine. A Fully-Digital Em Pulse Detector. DATE: Design, Automation and Test in Europe, Mar 2016, Dresden, Germany. 2016, 〈http://www.date-conference.com/conference/session/5.3〉. 〈lirmm-01269860〉
  • Maxime Lecomte, Jacques Jean-Alain Fournier, Philippe Maurine. Granularity and detection capability of an adaptive embedded Hardware Trojan detection system . HOST: Hardware Oriented Security and Trust, May 2016, McLean, VA, United States. IEEE, IEEE International Symposium on Hardware Oriented Security and Trust, pp.135-138, 2016, 〈10.1109/HST.2016.7495571〉. 〈lirmm-01434150〉
  • Maxime Lecomte, Jacques Jean-Alain Fournier, Philippe Maurine. On-Chip Fingerprinting of IC Topology for Integrity Verification. DATE: Design, Automation and Test in Europe, Mar 2016, Dresden, Germany. 2016, 〈http://www.date-conference.com/conference/session/3.3〉. 〈lirmm-01269856〉
  • Ibrahima Diop, Mathieu Carbone, Sébastien Ordas, Yanis Linge, Pierre Yvan Liardet, et al.. Collision for Estimating SCA Measurement Quality and Related Applications. CARDIS: Smart Card Research and Advanced Applications, Nov 2015, Bochum, Germany. 14th International Conference, CARDIS 2015, Bochum, Germany, November 4-6, 2015. Revised Selected Papers, LNCS (9514), pp.143-157, 2016, Smart Card Research and Advanced Applications. 〈10.1007/978-3-319-31271-2_9〉. 〈lirmm-01319093〉
  • Sébastien Ordas, Ludovic Guillaume-Sage, Philippe Maurine. EM Injection: Fault Model and Locality. FDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2015, Saint Malo, France. 2015 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), pp.3-13, 2015, 〈10.1109/FDTC.2015.9〉. 〈lirmm-01319078〉
  • Mathieu Carbone, Michel Agoyan, Yannick Teglia, Gilles Ducharme, Philippe Maurine. Interest of MIA in frequency domain?. CS2'2015: 2nd Workshop on Cryptography and Security in Computing Systems, Jan 2015, Amtersdam, Netherlands. Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, Proceedings of the Second Workshop on Cryptography and Security in Computing Systems. 〈10.1145/2694805.2694812〉. 〈lirmm-01111693〉
  • Diop Ibrahima, Pierre-Yvan Liardet, Yanis Linge, Philippe Maurine. Collision Based Attacks in Practice. DSD: Euromicro Conference on Digital System Design, Aug 2015, Madeire, Portugal. IEEE, Digital System Design (DSD), 2015 Euromicro Conference on, pp.367-374, 2015, 〈10.1109/DSD.2015.24〉. 〈lirmm-01269809〉
  • Maxime Lecomte, Philippe Maurine, Jacques Jean-Alain Fournier. Thoroughly analyzing the use of ring oscillators for on-chip hardware trojan detection. ReConFig: ReConFigurable Computing and FPGAs, Dec 2015, Mexico, Mexico. International Conference on ReConFigurable Computing and FPGAs, pp.1-6, 2015, 〈10.1109/ReConFig.2015.7393363〉. 〈lirmm-01354318〉
  • Laurent Chusseau, Rachid Omarouayache, Jérémy Raoult, Sylvie Jarrix, Philippe Maurine, et al.. Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI). VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2014, Playa del Carmen, Mexico. 22nd International Conference on Very Large Scale Integration, pp.1-6, 2014, 〈10.1109/VLSI-SoC.2014.7004189〉. 〈lirmm-01434592〉
  • Paolo Maistri, Regis Leveugle, Lilian Bossuet, Alain Aubert, Viktor Fischer, et al.. ElectroMagnetic Analysis and Fault Injection onto Secure Circuits. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2014, Mexico, Mexico. 22nd International Conference on Very Large Scale Integration, 2014, 〈10.1109/VLSI-SoC.2014.7004182〉. 〈emse-01099025〉
  • Loic Zussa, Amine Dehbaoui, Karim Tobich, Jean-Max Dutertre, Philippe Maurine, et al.. Efficiency of a glitch detector against electromagnetic fault injection. DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. IEEE, pp.1-6, 2014, Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. 〈10.7873/DATE.2014.216〉. 〈lirmm-01096047〉
  • Sébastien Tiran, Sébastien Ordas, Yannick Teglia, Michel Agoyan, Philippe Maurine. A frequency leakage model for SCA. HOST'2014: International Symposium on Hardware-Oriented Security and Trust, May 2014, Arlington, VA, United States. IEEE, Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp.97-100, Hardware-Oriented Security and Trust. 〈10.1109/HST.2014.6855577〉. 〈lirmm-01096058〉
  • Guilherme Perin, Laurent Imbert, Lionel Torres, Philippe Maurine. Attacking Randomized Exponentiations Using Unsupervised Learning. COSADE: Constructive Side-Channel Analysis and Secure Design, Apr 2014, Paris, France. COSADE'2014: 5th International Workshop on Constructive Side-Channel Analysis and Secure Design, LNCS (8622), pp.144-160, 2014, Constructive Side-Channel Analysis and Secure Design. 〈10.1007/978-3-319-10175-0_11〉. 〈lirmm-01096039〉
  • Sébastien Ordas, Ludovic Guillaume-Sage, Karim Tobich, Jean-Max Dutertre, Philippe Maurine. Evidence of a larger EM-induced fault model. CARDIS: Smart Card Research and Advanced Application, Nov 2014, Paris, France. 13th Smart Card Research and Advanced Application Conference, LNCS (8968), pp.245-259, 2015, Smart Card Research and Advanced Applications. 〈http://cedric.cnam.fr/events/cardis/〉. 〈10.1007/978-3-319-16763-3_15〉. 〈emse-01099037〉
  • Mathieu Carbone, Sébastien Tiran, Sébastien Ordas, Michel Agoyan, Yannick Teglia, et al.. On Adaptive Bandwidth Selection for Efficient MIA. COSADE'2014: 5th International Workshop on Constructive Side-Channel Analysis and Secure Design, Apr 2014, Paris, France. Constructive Side-Channel Analysis and Secure Design, pp.82-97, 2014, Lecture Notes in Computer Science. 〈lirmm-01096033〉
  • Rachid Omarouayache, Jérémy Raoult, Sylvie Jarrix, Laurent Chusseau, Philippe Maurine. Magnetic Microprobe design for EM fault attack. EMC EUROPE: Electromagnetic Compatibility, Sep 2013, Bruges, Belgium. IEEE International Symposium on Electromagnetic Compatibility, 2013, EMC EUROPE. 〈hal-01893856〉
  • Lionel Vincent, Philippe Maurine, Edith Beigne, Suzanne Lesecq, Julien Mottin. Temperature and Fast Voltage On-Chip Monitoring using Low-Cost Digital Sensors. VARI: Workshop on CMOS Variability, Sep 2013, Karlsruhe, Germany. 2013, 4th International Workshop on CMOS Variability. 〈hal-01067982〉
  • Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle. An evaluation of an AES implementation protected against EM analysis. GLSVLSI: Great Lakes Symposium on VLSI, May 2013, Paris, France. ACM New York, NY, USA, 23rd ACM International Conference on Great Lakes Symposium on VLSI, pp.317-318, 2013, 〈10.1145/2483028.2483120〉. 〈hal-00862787〉
  • Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle. Countermeasures against EM analysis for a secured FPGA-based AES implementation. ReConFig'13: International Conference on ReConFigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. IEEE Computer Society, pp.1-6, 2013, 〈10.1109/ReConFig.2013.6732274〉. 〈hal-00963133〉
  • Guilherme Perin, Laurent Imbert, Lionel Torres, Philippe Maurine. Electromagnetic Analysis on RSA Algorithm Based on RNS. DSD: Digital System Design, Sep 2013, Santander, Spain. IEEE, 16th Euromicro Conference on Digital System Design, pp.345-352, 2013, Digital System Design. 〈10.1109/DSD.2013.44〉. 〈lirmm-00861215〉
  • Karim Tobich, Philippe Maurine, Pierre-Yvan Liardet, Mathieu Lisart, Thomas Ordas. Voltage Spikes on the Substrate to Obtain Timing Faults. DSD: Digital System Design, Sep 2013, Santander, Spain. 16th Euromicro Conference Series on Digital System Design, pp.483-486, 2013, Digital System Design (DSD). 〈10.1109/DSD.2013.146〉. 〈lirmm-01096076〉
  • Guilherme Perin, Laurent Imbert, Lionel Torres, Philippe Maurine. Practical Analysis of RSA Countermeasures Against Side-Channel Electromagnetic Attacks. CARDIS: Smart Card Research and Advanced Application, Nov 2013, Berlin, Germany. Springer, 12th Smart Card Research and Advanced Application Conference, LNCS (8419), pp.200-215, 2013, 〈10.1007/978-3-319-08302-5_14〉. 〈lirmm-01096070〉
  • Morgan Bourrée, Florent Bruguier, Lyonel Barthe, Pascal Benoit, Philippe Maurine, et al.. SECNUM: an Open Characterizing Platform for Integrated Circuits. European Workshop on Microelectronics Education (EWME), May 2012, Grenoble, France. 2012. 〈hal-01139176〉
  • Philippe Maurine, Amine Dehbaoui, François Poucheret, Jean-Max Dutertre, Bruno Robisson, et al.. On the use of the EM medium as a fault injection means. CryptArch: Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2012, Fréjus, France. 10th International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices (CrypArchi 2012), 2012. 〈emse-00742707〉
  • Nadine Azemard, Zeqin Wu, Philippe Maurine, Gille Ducharme. Statistical Cells Timing Metrics Characterization. FTFC'12: IEEE Faible Tension Faible Consommation, Jun 2012, Paris, France. session4-paper3, 2012. 〈lirmm-00762131〉
  • Philippe Maurine, Lionel Vincent, Suzanne Lesecq, Edith Beigné. Local Condition Monitoring in Integrated Circuits Using a Set of Kolmogorov-Smirnov Tests. MSC'2012: Multi-conference on Systems and Control, Oct 2012, Dubrovnik, Croatia. IEEE, pp.001-010, 2012, 〈http://www.msc2012.org/〉. 〈lirmm-00762045〉
  • Paolo Maistri, Sébastien Tiran, Amine Dehbaoui, Philippe Maurine, Jean-Max Dutertre. Countermeasures against EM Analysis. 10th CryptArchi Workshop - St-Etienne Goutelas 2012, Jun 2012, Saint-Etienne, France. 〈emse-01130646〉
  • Pierre Bayon, Lilian Bossuet, Alain Aubert, Viktor Fischer, François Poucheret, et al.. Contactless Electromagnetic Active Attack on Ring Oscillator Based True Random Number Generator. W. Schindler; S. A. Huss. COSADE: Constructive Side-Channel Analysis and Secure Design, May 2012, Darmstadt, Germany. Third International Workshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings, LNCS (7275), pp.151-166, 2012, Constructive Side-Channel Analysis and Secure Design. 〈10.1007/978-3-642-29912-4_12〉. 〈ujm-00699618〉
  • Philippe Maurine, Lionel Vincent, Suzanne Lesecq, Edith Beigné. Embedding Statistical Tests for On-Chip Dynamic Voltage and Temperature Monitoring. DAC: Design Automation Conference, Jun 2012, San Francisco, CA, United States. 49th Design Automation Conference, pp.994-999, 2012, 〈https://dac.com/content/49th-dac〉. 〈lirmm-00762020〉
  • Philippe Maurine, Karim Tobich, Thomas Ordas, Pierre Yvan Liardet. Yet Another Fault Injection Technique : by Forward Body Biasing Injection. YACC'2012: Yet Another Conference on Cryptography, Sep 2012, Porquerolles Island, France. 2012, 〈http://yacc.univ-tln.fr/〉. 〈lirmm-00762035〉
  • Philippe Maurine, Guilherme Perin, Lionel Torres, Pascal Benoit. Amplitude Demodulation-Based EM Analysis of Different RSA Implementations. DATE: Design, Automation and Test in Europe, Mar 2012, Dresden, Germany. pp.1167-1172, 2012, 〈http://www.date-conference.com/〉. 〈lirmm-00762023〉
  • Pierre Bayon, Lilian Bossuet, Alain Aubert, Viktor Fischer, François Poucheret, et al.. Electromagnetic Attacks on Ring Oscillator-Based True Random Number Generator. CryptArchi: Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2012, Saint-Etienne, France. 2012. 〈ujm-00712545〉
  • Philippe Maurine. Techniques for EM Fault Injection: Equipments and Experimental Results. FDTC'2012: Fault Diagnosis and Tolerance in Cryptography, Sep 2012, Lewen, Belgium. pp.003-004, 2012, 〈www.fdtc-workshop.eu/〉. 〈lirmm-00761778〉
  • Philippe Maurine, Sébastien Tiran. SCA with Magnitude Squared Coherence. CARDIS'12: Eleventh Smart Card Research and Advanced Application Conference, Nov 2012, Austria. pp.001-010, 2012, 〈http://cardis.iaik.tugraz.at〉. 〈lirmm-00762038〉
  • Rachid Omarouayache, Jérémy Raoult, Sylvie Jarrix, Philippe Maurine, Laurent Chusseau. Sondes de champ proche pour l'injection de fautes. GDR Ondes, Mar 2011, Paris, France. 2011. 〈hal-01894317〉
  • Philippe Maurine, François Poucheret, Karim Tobich, Mathieu Lisart, Bruno Robisson, et al.. Local and Direct Power Injection on CMOS Integrated Circuits. FDTC'2011: Fault Diagnosis and Tolerance in Cryptography, Sep 2011, Nara, Japan. pp.100-104, 2011, 〈10.1109/FDTC.2011.18〉. 〈lirmm-00607868〉
  • Philippe Maurine, Bruno Vaquie, Sébastien Tiran. A Secure D Flip-Flop against Side Channel Attacks. PATMOS'11: Power and Timing Modeling Optimization and Simulation, Sep 2011, Portugal. pp.331-340, 2011, 〈http://patmos.dacya.ucm.es/〉. 〈lirmm-00762027〉
  • Nadine Azemard, Zeqin Wu, Philippe Maurine, Gille Ducharme. Statistical Timing Characterization of Standard Cells with Semi-Monte-Carlo Method. VARI: Workshop on CMOS Variaility, May 2011, Grenoble, France. 2011, 2nd European Workshop on CMOS Variaility. 〈lirmm-00617593〉
  • Lionel Vincent, Edith Beigne, Laurent Alacoque, Suzanne Lesecq, Catherine Bour, et al.. A Fully Integrated 32 nm MultiProbe for Dynamic PVT Measurements within Complex Digital SoC. VARI: International Workshop on CMOS Variability, May 2011, Grenoble, France. 2011, 2nd International Workshop on CMOS Variability. 〈hal-01067989〉
  • Philippe Maurine, Amine Dehbaoui, Thomas Ordas, Victor Lomné, Lionel Torres, et al.. Incoherence Analysis and its Application to Time Domain EM Analysis of Secure Circuits. Asia-Pacific Symposium on Electromagnetic Compatibility, May 2011, Jeju Island, South Korea. pp.1039-1042, 2011. 〈lirmm-00607894〉
  • Philippe Maurine, Pierre Bayon, Lilian Bossuet, Alain Aubert, Viktor Fischer, et al.. Contactless Electromagnetic Active Attack on Ring Oscillator Based True Random Number Generator. COSADE'2011: Constructive Side-Channel and Secure Design, Feb 2011, Darmstadt, Germany. pp.151-156, 2011, 〈http://cosade2011.cased.de/〉. 〈lirmm-00761824〉
  • Nadine Azemard, Zeqin Wu, Philippe Maurine, Gille Ducharme. Characterizing Statistical Cells Timing Metrics with Semi-Monte-Carlo Method. VLSI-Soc'11 : IFIP/IEEE International Conference on Very Large Scale Integration, Oct 2011, Hong-Kong, China. pp.6, 2011. 〈lirmm-00617606〉
  • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. SSTA with Cell-to-Cell Delay Correlations. VARI: Workshop on CMOS Variability, May 2010, Montpellier, France. 2010, 1st European Workshop on CMOS Variability. 〈lirmm-00546322〉
  • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. Computing Delay Correlations in SSTA. ICICDT'10: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.N/A, 2010. 〈lirmm-00546301〉
  • François Poucheret, Lyonel Barthe, Pascal Benoit, Lionel Torres, Philippe Maurine, et al.. Spatial EM Jamming: a Countermeasure Against EM Analysis ?. VLSI-SoC'10: 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, Madrid, Spain. pp.105-110, 2010. 〈lirmm-00544358〉
  • Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres, Michel Robert. Differential Power Analysis Enhancement with Statistical Preprocessing. DATE: Design, Automation and Test in Europe, 2010, Dresden, Germany. pp.1301-1304, 2010, 〈10.1109/DATE.2010.5457007〉. 〈lirmm-00548738〉
  • Philippe Maurine, Victor Lomné, Lionel Torres, Thomas Ordas, Mathieu Lisart, et al.. Modeling Time Domain Magnetic Emissions of ICs. PATMOS'10: Power and Timing Modeling Optimization and Simulation, Sep 2010, France. pp.238-249, 2010, 〈http://patmos2010.imag.fr/〉. 〈lirmm-00762033〉
  • Nabila Moubdi, Philippe Maurine, Nadine Azemard, Robin Wilson, Sylvain Engels. Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPC. ICICDT'10: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.N/A, 2010. 〈lirmm-00546316〉
  • Philippe Maurine, Victor Lomné, Lionel Torres, Thomas Ordas, Mathieu Lisart, et al.. A Simulation Flow for Time Domain Magnetic Radiations of ICs. PATMOS'2010: Power and Timing Modeling, Optimization, and Simulation, Sep 2010, Grenoble, France. 6448/2011 (6448), pp.238-249, 2010, Lecture Notes in Computer Science. 〈10.1007/978-3-642-17752-1_24〉. 〈lirmm-00607884〉
  • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. SSTA with Delay Correlations. NEWCAS: International New Circuits and Systems Conference, Jun 2010, Montreal, Canada. 8th IEEE International NEWCAS Conference, pp.261-266, 2010, 〈http://newcas.grm.polymtl.ca/keynotes.html〉. 〈lirmm-00504882〉
  • Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Vincent Dumettier, et al.. On-Chip Process Variability Monitoring. VARI: Workshop on CMOS Variability, May 2010, Montpellier, France. 2010, 1st European Workshop on CMOS Variability. 〈lirmm-00546337〉
  • Ali Alaeldine, Thomas Ordas, Richard Perdriau, Philippe Maurine, Mohamed Ramdani, et al.. Assessment of the Immunity of Unshielded Multicore Integrated Circuits to Near Field Injection. International Zurich Symposium on Electromagnetic Compatibility, France. pp.361-364, 2009. 〈lirmm-00394411〉
  • Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Vincent Dumettier, et al.. Product On-Chip Process Compensation for Low Power and Yield Enhancement. Patmos'09: 19th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2009, Delft, Netherlands. Springer, pp.247-255, 2009. 〈lirmm-00433504〉
  • Nabila Moubdi, Robin Wilson, Sylvain Engels, Nadine Azemard, Philippe Maurine. On-Chip Process Variability Monitoring. DATE: Design, Automation and Test in Europe, Apr 2009, Nice, France. 2009, W2. 〈lirmm-00374368〉
  • Ali Alaeldine, Thomas Ordas, Richard Perdriau, Philippe Maurine, Mohamed Ramdani, et al.. Etude de l'effet du boîtier sur l'immunité en champ proche des circuits intégrés. Telecom 2009 & 6èmes JFMMA, Mar 2009, Agadir, Maroc. 4 p., 2009. 〈hal-00522766〉
  • Bettina Rebaud, Marc Belleville, Edith Beigne, Michel Robert, Philippe Maurine, et al.. An Innovative Timing Slack Monitor for Variation Tolerant Circuits. ICICDT'09: International Conference on IC Design & Technology, May 2009, Austin, Texas, USA, pp.215-218, 2009. 〈lirmm-00371174〉
  • Zeqin Wu, Nadine Azemard, Philippe Maurine, Gille Ducharme. Interpretation of SSTA Results. FTFC'09 : 8èmes Journées Faible Tension Faible Consommation, Jun 2009, Neuchâtel, Switzerland. pp.N/A, 2009. 〈lirmm-00374060〉
  • Amine Dehbaoui, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert. Enhancing Electromagnetic Attacks using Spectral Coherence based Cartography. Jürgen Becker; Marcelo Johann; Ricardo Reis. 17th International Conference on Very Large Scale Integration (VLSISOC), Oct 2009, Florianopolis, Brazil. Springer, IFIP Advances in Information and Communication Technology, AICT-360, pp.11-16, 2009, VLSI-SoC: Technologies for Systems Integration. 〈10.1109/VLSISOC.2009.6041323〉. 〈lirmm-00429342〉
  • Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, et al.. Evaluation on FPGA of Triple Rail Logic Robustness Against DPA and DEMA. DATE: Design, Automation and Test in Europe, 2009, Nice, France. pp.634-639, 2009, 〈10.1109/DATE.2009.5090744〉. 〈lirmm-00372847〉
  • Lionel Torres, Victor Lomné, Philippe Maurine, Amine Dehbaoui. Fingerprinting Hardware Security Module Using ICs Radiations. 7th International Workshop on Electromagnetic Compatibility of Integrated Circuits, pp.6, 2009. 〈lirmm-00433331〉
  • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. Interpreting SSTA Results with Correlation. Springer. PATMOS'09: 19th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.16-25, 2009. 〈lirmm-00433505〉
  • Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, et al.. Triple Rail Logic Robustness Against DPA. ReConFig'08: International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp.415-420, 2008. 〈lirmm-00350573〉
  • Bettina Rebaud, Marc Belleville, Edith Beigne, Michel Robert, Philippe Maurine, et al.. Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variations. FTFC'09 : 8èmes Journées d'Etudes Faible Tension Faible Consommation, Jun 2009, Neuchâtel, Suisse, pp.N/A, 2009, 〈http://www.isep.fr/ftfc/public/index.php〉. 〈lirmm-00404810〉
  • Thomas Ordas, M. Lisart, Lionel Torres, Philippe Maurine. Technological countermeasures for IC protection against EM Analysis. PAca Security Trends In embedded Security, Gardanne, France. 2008. 〈lirmm-00407011〉
  • Bettina Rebaud, Marc Belleville, Edith Beigne, Michel Robert, Philippe Maurine, et al.. On-Chip Timing Slack Monitoring. VLSI-SOC 2009: IFIP/IEEE International Conference on Very Large Scale Integration, Oct 2009, Florianopolis, Brazil. pp.89-94, 2009, Session: Physical Design, Low Power Design. 〈10.1109/VLSISOC.2009.6041336〉. 〈lirmm-00429350〉
  • Philippe Maurine. Electromagnetic analyses of secure circuits: Results on FPGA & ASIC. MARITE : Centre d'ELectronique de l'Armement (CELAR), France. 2009. 〈lirmm-00407014〉
  • Bettina Rebaud, Marc Belleville, Edith Beigne, Christian Bernard, Michel Robert, et al.. Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of Variabilities. Patmos'09: 19th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2009, Delft, Netherlands. Springer, pp.266-275, 2009. 〈lirmm-00433462〉
  • Thomas Ordas, Mathieu Lisart, Etienne Sicard, Philippe Maurine, Lionel Torres. Near-field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits. PATMOS'08: International Workshop on Power and Timing Modeling Optimization and Simulation, pp.229-236, 2008. 〈lirmm-00394395〉
  • Thomas Ordas, Ali Alaeldine, Philippe Maurine, Richard Perdriau, Lionel Torres, et al.. Evaluation of Countermeasures against Electromagnetic Analysis. EMC Europe: Electromagnetic Compatibility, Jun 2009, Athens, Greece. International Symposium on Electromagnetic Compatibility, 2009, EMC Europe. 〈10.1109/EMCEUROPE.2009.5189724〉. 〈hal-01271857〉
  • Victor Lomné, Rafael Soares, Thomas Ordas, Philippe Maurine, Lionel Torres, et al.. Prototyping Secure Triple Track Logic (STTL) Robustness Against DPA & DEMA on FPGA. CryptArchi'08: Cryptographic Architectures Embedded in Reconfigurable Devices, 2008, Tregastel, France. 2008, 〈http://labh-curien.univ-st-etienne.fr/cryptarchi/workshop08/index.htm〉. 〈lirmm-00373539〉
  • Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Définition d'une Métrique d'Insertion de Buffers. FTFC'03 : 4èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, Paris (France), pp. 131-136, 2003. 〈lirmm-00269520〉
  • Philippe Maurine, Xavier Michel, Nadine Azemard, Daniel Auvergne. Gate Speed Improvement at Minimal Power Dissipation. APPCAS'02, Denpasar, Bali, pp.278-282, 2002. 〈lirmm-00268628〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Structure Independant Representation of Output Transition Time for CMOS Library. PATMOS'02: 12th International Workshop on Power and Timing ModelingOptimization and Simulation, Seville, Espagne, Springer, pp.247-257, 2002, Lecture Notes in Computer Science. 〈lirmm-00268618〉
  • Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, et al.. Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numérique. FTFC'08 : 7èmes Journées d'Etudes Faible Tension Faible Consommation, May 2008, Louvain-La-Neuve, Belgique. pp.N/A, 2008, 〈http://www.isep.fr/ftfc/〉. 〈lirmm-00283731〉
  • Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert. A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. DELTA'08: Fourth IEEE International Symposium on Electronic Design, Test and Applications, Jan 2008, Hong Kong, China, IEEE Computer Society, pp.107-110, 2008, 〈www.ece.ust.hk/delta2008/〉. 〈lirmm-00243966〉
  • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. SSTA with Correlations Considering input Slope and Output Load Variations. IFIP VLSI-SOC 2008 - IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, Rhodes, Greece, pp.164-167, 2008. 〈lirmm-00332757〉
  • Benoit Lasbouygues, J. Schindler, S. Engels, Philippe Maurine, Nadine Azemard, et al.. Représentation Unifiée des Performances Temporelles d'une Bibliothèque de Cellules Standards. FTFC'03 : 4èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, Paris (France), pp. 119-124, 2003. 〈lirmm-00269519〉
  • Bettina Rebaud, Zeqin Wu, Marc Belleville, Christian Bernard, Michel Robert, et al.. Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétique. JNRDM'08 : Journées Nationales du Réseau Doctoral en Microélectronique, May 2008, pp.N/A, 2008, 〈http://www.u-bordeaux1.fr/jnrdm/〉. 〈lirmm-00281175v2〉
  • Zeqin Wu, Philippe Maurine, Gille Ducharme, Nadine Azemard. Conditional Moments based SSTA Considering Switching Process Induced Correlations. DCIS'08: Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. pp.70-77, 2008, 〈http://obaldia.imag.fr/〉. 〈lirmm-00340221〉
  • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. SSTA with Structure Correlations Considering input Slope and Output Load Variations. GDR SOC-SIP, Jun 2008, Paris, France. pp.3, 2008. 〈lirmm-00340231〉
  • Nadine Azemard, Philippe Maurine, Daniel Auvergne. Feasible Delay Bound Definition. SoC Design Methodologies - 11th International Conference on Very Large Scale Integration of Systems-on-Chips, Montpellier, France, Kluwer Academic Publishers, pp.325-335, 2002. 〈lirmm-00268478〉
  • Rafael Soares, Ney Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, et al.. Evaluating the Robustness of Secure Triple Track Logic Through Prototyping. SBCCI'08: Symposium on Integrated Circuits and Systems Design, Sep 2008, Gramado, Brazil, ACM, pp.193-198, 2008, 〈http://www.inf.ufrgs.br/chipinthepampa2008/〉. 〈10.1145/1404371.1404425〉. 〈lirmm-00373516〉
  • Zeqin Wu, Philippe Maurine, Gille Ducharme, Nadine Azemard. SSTA Considering Effects of Structure Correlations, Input Slope and Output Load Variations. FTFC'08 : 7èmes Journées d'Etudes Faible Tension Faible Consommation, May 2008, Louvain-la-Neuve, Belgique, pp.39-43, 2008, 〈www.isep.fr/ftfc〉. 〈lirmm-00288537〉
  • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. SSTA Considering Switching Process Induced Correlations. APCCAS'08: IEEE Asia Pacific Conference on Circuits and System, Nov 2008, pp.562-565, 2008. 〈lirmm-00340564〉
  • Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert. Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects. ISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, IEEE, pp.310-315, 2008. 〈lirmm-00280716〉
  • Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, et al.. Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, IEEE, pp.316-321, 2008. 〈lirmm-00280809〉
  • Benoit Lasbouygues, J. Schindler, S. Engels, Philippe Maurine, Xavier Michel, et al.. Continuous Representation of the Performance of a CMOS Library. ESSCIRC'03: 29th European Solid-State Circuits Conference, Estoril (Portugal), pp. 595-598, 2003. 〈lirmm-00269690〉
  • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Dimensionnement de Portes CMOS Sous Contrainte de Délai. FTFC'03 : 4èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, Paris (France), pp. 111-117, 2003. 〈lirmm-00269522〉
  • Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Evaluation et Optimisation de Chemins Combinatoires. Colloque du GDR CAO de Circuits et Systèmes Intégrés, Paris (France), France. pp. 173-176, 2002. 〈lirmm-00269329〉
  • Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert. A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. IEEE International Workshop on Memory Technology, Design and Testing, Dec 2007, Taipei, Taiwan, China. pp.032-036, 2007. 〈lirmm-00198383〉
  • Hanitriniaina Razafindraibe, Michel Robert, Philippe Maurine. Improvement of Dual Rail Logic as a Countermeasure Against DPA. IFIP VLSI-SOC 2007 - IFIP WG 10.5 International Conference on Very Large Scale Integration, Oct 2007, Atlanta, GA, USA, pp.270-275, 2007. 〈lirmm-00186174〉
  • Alin Razafindraibe, Philippe Maurine. A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates. PATMOS'07: Power and Timing Modeling, Optimization and Simulation, May 2007, Gothenburg, Sweden, Springer, pp.394-403, 2007, LNCS. 〈lirmm-00175108〉
  • Benoit Lasbouygues, Robin Wilson, Nadine Azemard, Philippe Maurine. Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops. DATE: Design, Automation and Test in Europe, Mar 2007, Nice, France. 2007, 〈10.1109/DATE.2007.364426〉. 〈lirmm-00178525〉
  • V. Migairou, R. Wilson, S. Engels, Zeqin Wu, Nadine Azemard, et al.. A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. FTFC 2007 : 6èmes Journées d'Etudes Faible - Tension Faible Consommation, May 2007, Paris, France, pp.19-25, 2007, 〈http://www.isep.fr/ftfc〉. 〈lirmm-00178454〉
  • Bettina Rebaud, Marc Belleville, Christian Bernard, Michel Robert, Philippe Maurine. Méthodologie d'estimation de l'influence de la variabilité sur un opérateur numérique. FTFC'07 : 6èmes journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France, France. pp.N/A, 2007, 〈http://www.isep.fr/ftfc/public/index.php〉. 〈lirmm-00204621〉
  • Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert. Process Variabilities and Performances in a 90nm embedded SRAM. IEEE International Integrated Reliability Workshop, Oct 2007, pp.050-055, 2007, 〈http://www.iirw.org/〉. 〈lirmm-00198373〉
  • Robin Perrot, Nadine Azemard, Philippe Maurine. Une Famille d'Additionneurs Asynchrones CMOS Bundled Data à Temps de Calcul Dépendant aux Données. FTFC 2007: 6èmes Journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France, pp.75-80, 2007, 〈www.isep.fr/ftfc〉. 〈lirmm-00178466〉
  • Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert. Variabilité de Process et Performances des Mémoires SRAM Embarquées. FTFC'07: 6èmes Journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France, pp.7-11, 2007, 〈http://www.isep.fr/ftfc〉. 〈lirmm-00178319〉
  • V. Migairou, R. Wilson, S. Engels, Zeqin Wu, Nadine Azemard, et al.. A Simple Statistical Timing Analysis Flow and its Application to Timing Margin Evaluation. PATMOS'07: Power and Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden, Springer, pp.138-147, 2007, LNCS. 〈lirmm-00175076〉
  • Alin Razafindraibe, Michel Robert, Philippe Maurine. Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. PATMOS'07: Power and Timing Modeling, Optimization and Simulation, 2007, Gothenburg, Sweden, Springer, pp.340-351, 2007, LNCS. 〈lirmm-00175100〉
  • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Circuit Sizing Method under Delay Constraint. ISCAS'06: IEEE International Symposium on Circuits and Systems, May 2006, Kos (Greece), pp.5123-5126, 2006. 〈lirmm-00106911〉
  • Benoit Lasbouygues, Robin Wilson, Nadine Azemard, Philippe Maurine. Timing Analysis in Presence of Voltage Drops and Temperature Gradients. TAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.28-34, 2006. 〈lirmm-00106705〉
  • Hanitriniaina Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin. Security Evaluation of Dual Rail Logic Against DPA Attacks. VLSI-SOC'06: 14th IFIP WG 10.5 International Conference on Very Large Scale Integration and System-On-Chip, Oct 2006, Nice (France), IEEE, pp.181-186, 2006. 〈lirmm-00109692〉
  • V. Migairou, R. Wilson, S. Engels, Nadine Azemard, Philippe Maurine. Statistical Characterization of Library Timing Performance. PATMOS'06: Power and Timing Modeling, Optimization and Simulation - Integrated Circuit and System Design, Sep 2006, Montpellier (France), Springer, pp.468-476, 2006, LNCS. 〈lirmm-00093233〉
  • B. Lasbouygues, Robin Wilson, Nadine Azemard, Philippe Maurine. Timing Analysis in Presence of Supply Voltage and Temperature Variations. ISPD: International Symposium on Physical Design, Apr 2006, San Jose, CA, United States. pp.10-16, 2006. 〈lirmm-00102760〉
  • Robin Perrot, Nadine Azemard, Philippe Maurine. Request-Skip Adders: CMOS Standard Cell Data Dependent Adders. ICECS'06: 13th IEEE International Conference on Electronics, Circuits and Systems, Dec 2006, Nice (France), pp.510-513, 2006. 〈lirmm-00130195〉
  • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Circuit Performance Optimization under Delay Constraints. DCIS'06: 21th Conference on Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain, pp.CDROM, 2006. 〈lirmm-00117119〉
  • Robin Perrot, Nadine Azemard, Philippe Maurine. Une Famille d'Additionneur Asynchrones CMOS à Temps de Calcul Dépendant de Données. JNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. 9ièmes Journées Nationales du Réseau Doctoral de Microélectronique, pp.469-472, 2006. 〈lirmm-00102842〉
  • Robin Perrot, Philippe Maurine, Nadine Azemard. Exploration of the Area-Latency Tradeoff of Asynchronous CMOS data Dependent Adders. DCIS'06: 21th Conference on Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain, pp.CDROM, 2006. 〈lirmm-00117102〉
  • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Speed Indicators for Circuit Optimization. PATMOS'05: 15th International Workshop on Power and Timing ModelingOptimization and Simulation, Sep 2005, Leuven, Belgium, pp.618-628, 2005. 〈lirmm-00106076〉
  • Robin Perrot, Nadine Azemard, Philippe Maurine. Ripple Carry Adder for Micropipeline Circuits. DCIS: Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal. 20th International Conference on Design of Circuits and Integrated Systems, pp.4d.3.1-4d.3.6, 2005. 〈lirmm-00106075〉
  • Alexis Landrault, Alexandre Verle, Philippe Maurine, Nadine Azemard. Synthèse Physique et Optimisation des Performances au Niveau Transistor. FTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.91-95, 2005. 〈lirmm-00106004〉
  • Alexandre Verle, Xavier Michel, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Low Power Oriented CMOS Circuit Optimization Protocol. DATE'05: Design, Automation and Test in Europe, Mar 2005, Munich, Germany. pp.640-645, 2005. 〈lirmm-00106452〉
  • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Optimization Protocol Based on Low Power Metrics. IWLS'05: 14th IEEE International Workshop on Logic Synthesis, Jun 2005, Lake Arrowhead Resort, CA (USA), pp.288-293, 2005. 〈lirmm-00106018〉
  • Robin Perrot, Nadine Azemard, Philippe Maurine. Additionneurs RCA Data Dependent Micropipelines. FTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.183-188, 2005. 〈lirmm-00106005〉
  • Alin Razafindraibe, Michel Robert, Philippe Maurine. Méthode de Conception de Primitives Asynchrones Double Rail. FTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.23-27, 2005. 〈lirmm-00106003〉
  • Alin Razafindraibe, Philippe Maurine, Michel Robert. La Technologie Asynchrone QDI pour la Sécurité des Cryptosystèmes. JNRDM'05 : 8ièmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France. pp.461-463, 2005. 〈lirmm-00106530〉
  • Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine. A Method to Design Compact Dual-rail Asynchronous Primitives. Paliouras, Vassilis; Verkest, Diederik; Vounckx, Johan. PATMOS: Power and Timing Modeling, Optimization and Simulation, 2005, Leuven, Belgium. Springer, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings, LNCS (3728), pp.571-580, 2005, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. 〈10.1007/11556930_58〉. 〈hal-00105846〉
  • Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine. Asynchronous Dual rail Cells to Secure Cryptosystem Against Side Channel Attacks. SAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia-Antipolis, 2005. 〈lirmm-00106539〉
  • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Circuit Optimization Based on Speed Indicators. ICECS'05: 12th IEEE International Conference on ElectronicsCircuits and Systems, Dec 2005, Gammarth, Tunisie, pp.167-170, 2005. 〈lirmm-00106439〉
  • Alin Razafindraibe, Michel Robert, Philippe Maurine. Design of Compact Dual Rail Asynchronous Primitives. DCIS'05: 20th International Conference on Design of Circuits and Integrated Systems, 2005, pp.P nd., 2005. 〈lirmm-00106434〉
  • Benoit Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Temperature Dependency in UDSM Process. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. 15th International Workshop on Power and Timing Modeling, Optimization and Simulation, LNCS (3728), pp.693-703, 2005, 〈10.1007/11556930_71〉. 〈lirmm-00106077〉
  • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard. Protocole d'Optimisation de Circuit CMOS Orienté Basse Puissance. FTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.17-22, 2005. 〈lirmm-00106002〉
  • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Path Optimization Protocol Based on Speed Low Power Metrics. EUROCON'05: International Conference on "Computer as a Tool", Nov 2005, Montenegro, Belgrade (Serbie), pp.523-526, 2005. 〈lirmm-00106428〉
  • Alexandre Verle, Xavier Michel, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Low Power Oriented CMOS Circuit Optimization Protocol. DATE: Design, Automation and Test in Europe, Mar 2005, Munich, Germany. Design, Automation and Test in Europe, pp.640-645, 2005. 〈lirmm-01507287〉
  • Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Definition of P/N Width Ratio for CMOS Standard Cell Library. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. 19th International Conference on Design of Circuits and Integrated Systems, pp.769-773, 2004. 〈lirmm-00108933〉
  • Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Optimization Protocol Based on Performance Metric. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. 19th International Conference on Design of Circuits and Integrated Systems, pp.964-968, 2004. 〈lirmm-00108935〉
  • Alin Razafindraibe, Michel Robert, Bertrand Folco, Philippe Maurine, Ghislain Bouesse, et al.. Secured Structures for Secured Asynchronous QDI Circuits. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. IEEE, XIX Conference on Design of Circuits and Integrated Systems, 2004. 〈hal-01393250〉
  • Alexis Landrault, Nadine Azemard, Philippe Maurine, Michel Robert, Daniel Auvergne. Design Optimization with Automated Cell Generation. PATMOS'04: 14th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2004, Santorini (Greece), Springer, pp.722-731, 2004, Lecture Notes in Computer Science. 〈lirmm-00108894〉
  • Benoit Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Temperature Dependence in Low Power CMOS UDSM Process. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. Springer, 14th International Workshop on Power and Timing Modeling Optimization and Simulation, LNCS (3254), pp.111-118, 2004, 〈10.1007/978-3-540-30205-6_13〉. 〈lirmm-00108893〉
  • Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Performance Metric Based Optimization Protocol. PATMOS'04: 14th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2004, Santorini (Greece), Springer, pp.100-109, 2004, Lecture Notes in Computer Science. 〈lirmm-00108892〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. RC on-chip interconnect Performance revisited. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. 19th International Conference on Design of Circuits and Integrated Systems, pp.809-814, 2004. 〈lirmm-00108934〉
  • Benoit Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Physical Extension of the Logical Effort Model. PATMOS'04: 14th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2004, Santorini (Greece), Springer, pp.838-848, 2004, Lecture Notes in Computer Science. 〈lirmm-00108895〉
  • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Delay Bound Based CMOS Gate Sizing Technique. ISCAS'04: International Symposium on Circuits and Systems, May 2004, Vancouver (Canada), pp.189-192, 2004. 〈lirmm-00108856〉
  • Alexis Landrault, Nadine Azemard, Philippe Maurine, Michel Robert, Daniel Auvergne. Automatic Layout Synthesis Based Performance Optimization. IWLS'04: 13th IEEE International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, pp.80-85, 2004. 〈lirmm-00108654〉
  • Guy Cathébras, S. Dussausay, Michel Robert, Philippe Maurine. Conception et Modélisation de Briques Elémentaires CMOS. CNFM'04 : 8ème Journées Pédagogiques du Comité National de Formation en Microélectronique, 2004, Saint-Malo, France. pp.35-37, 2004. 〈lirmm-00108672〉
  • Philippe Maurine, Jean-Baptiste Rigaud, Ghislain Bouesse, Gilles Sicard, Marc Renaudin. TAL : Une Bibliothèque de Cellules pour le Design de Circuits Asynchrones QDI. FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. 4èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, pp.41-49, 2003. 〈lirmm-00269521〉
  • Philippe Maurine, Jean-Baptiste Rigaud, Ghislain Bouesse, Gilles Sicard, Marc Renaudin. Static Implementation of QDI Asynchronous Primitives. Springer. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, LNCS (2799), pp.181-191, 2003. 〈lirmm-00269567〉
  • Philippe Maurine, Jean-Baptiste Rigaud, G. Sicard, Marc Renaudin. Static Implementation of QDI asynchronous primitives. 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'03), Sep 2003, Torino, Italy. pp.171-180. 〈hal-01376724〉
  • Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Metric Definition for Circuit Speed Optimization. Springer. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, LNCS (2799), pp.451-460, 2003. 〈lirmm-00269568〉
  • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. CMOS Gate Sizing under Delay Constraint. Springer. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. 12th International Workshop on Power And Timing Modeling, Optimization and Simulation, LNCS (2799), pp.60-69, 2003. 〈lirmm-00269566〉
  • Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Metric Definition for Circuit Speed Optimization. PAMOS'03: 13th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2003, Torino, Italy, pp.451-460, 2003. 〈lirmm-00244025〉
  • Benoit Lasbouygues, J. Schindler, S. Engels, Philippe Maurine, Xavier Michel, et al.. Continuous Representation of the Performance of a CMOS Library. ESSCIRC'03: 29th European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal, pp.595-598, 2003. 〈lirmm-00239459〉
  • Benoit Lasbouygues, J. Schindler, Sylvain Engels, Philippe Maurine, Xavier Michel, et al.. Timing Performance Representation of a CMOS Standard Cell Library. DCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. 18th International Conference on Design of Circuits and Integrated Systems, pp.83-88, 2003. 〈lirmm-00239460〉
  • Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Metric Definition for Circuit Speed Optimization. IWLS'03: IEEE 12th International Workshop on Logic & Synthesis, May 2003, pp.CD, 2003. 〈lirmm-00244020〉
  • Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Metric Definition for Circuit Speed Optimization. IWLS: International Workshop on Logic Synthesis, May 2003, Laguna Beach, CA, United States. 12th IEEE International Workshop on Logic Synthesis, 2003, 〈http://www.iwls.org/iwls2003/〉. 〈lirmm-00269689〉
  • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. CMOS Gate Sizing under Delay Constraint. PAMOS'03: 13th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2003, Torino, Italy, pp.60-69, 2003. 〈lirmm-00244021〉
  • Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Gate Sizing for Low Power Design. SoC Design Methodologies, 2002, Montpellier, France. Kluwer Academic Publishers, pp.301-312, 2002. 〈lirmm-00268519〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Defining the Maximum Speed of CMOS Gate Library. DCIS'02: XVII Design of Circuits and Integrated Systems Conference, Nov 2002, Santander, Espagne, pp.81-86, 2002. 〈lirmm-00239455〉
  • Philippe Maurine, Xavier Michel, Nadine Azemard, Daniel Auvergne. Gate Speed Improvement at Minimal Power Dissipation. APPCAS'02: IEEE Asia-Pacific Conference on Circuits and Systems, Oct 2002, Denpasar, Bali, pp.278-282, 2002. 〈lirmm-00239453〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Defining the Maximum Speed of CMOS Gate Library. DCIS: Design of Circuits and Integrated Systems, 2002, Santander, Spain. 17th International Conference on Design of Circuits and Integrated Systems, pp.81-86, 2002. 〈lirmm-00268431〉
  • Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Metric Definition for Buffer Insertion. DCIS'02: XVII Design of Circuits and Integrated Systems Conference, Nov 2002, Santander, Espagne, pp.307-312, 2002. 〈lirmm-00239458〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS'02: 12th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2002, Seville, Espagne, pp.247-257, 2002. 〈lirmm-00244012〉
  • Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Timing Closure Management based on Delay Bound Determination. VLSI-SoC'01: 11th IFIP International Conference on Very Large Scale Integration - The Global System On Chip Design & CAD Conference, Dec 2001, Montpellier, France, pp.430-434, 2001. 〈lirmm-00239452〉
  • Philippe Maurine, Régis Poirier, Nadine Azemard, Daniel Auvergne. Switching Current Modeling in CMOS Inverter for Speed and Power Estimation. DCIS'01: XVI Design of Circuits and Integrated Systems Conference, Nov 2001, Porto, Portugal, pp.618-622, 2001. 〈lirmm-00239448〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Technological Assignment for a Minimal Power Consumption. VLSI-SoC'01: 11th IFIP International Conference on Very Large Scale Integration - The Global System On Chip Design & CAD Conference, Dec 2001, Montpellier, France, pp.236-241, 2001. 〈lirmm-00239450〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Full Analyttical Model for delay Performance Estimation in Submicron CMOS. MIXDES'01: 8th Mixed Design of Integrated Circuits and Systems, Jun 2001, Zakopane, Pologne, pp.355-359, 2001. 〈lirmm-00239444〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Perfornance Evaluation for Submicron CMOS Design. PhD Forum at DAC 2001 : Design Automation Conference, Jun 2001, Las Vegas, Nevada, USA, pp.N/A, 2001. 〈lirmm-00239441〉
  • Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Delay Bound Determination for Timing Closure on CMOS Circuits. IWLS'01: IEEE 10th International Workshop on Logic & Synthesis, Jun 2001, Granlibakken Conference Center, USA, pp.96-100, 2001. 〈lirmm-00244007〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination. PATMOS'01: 11th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2001, Yverdon-Les-Bains, Switzerland, pp.5.3.1-5.3.10, 2001. 〈lirmm-00244010〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Performance Indicators for Designing CMOS Logic. ICM'01: 13th International Conference on Microelectronic, Oct 2001, Rabat, Maroc, pp.125-129, 2001. 〈lirmm-00239446〉

Poster2 documents

  • Nadine Azemard, Zeqin Wu, Philippe Maurine, Gille Ducharme. Statistical Timing Characterization. S0C'12: International Symposium on System-on-Chip, Oct 2012, Tmapere, Finland. pp.N/A, 2012. 〈lirmm-00762107〉
  • Florent Bruguier, Pascal Benoit, Philippe Maurine, Lionel Torres. A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis. FPL: Field Programmable Logic and Applications, Sep 2011, Crête, Greece. 21st International Conference on Field Programmable Logic and Applications, 2011. 〈lirmm-00616954〉

Ouvrage (y compris édition critique et traduction)3 documents

  • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. Delay-Correlation-Aware SSTA Based on Conditional Moments. Z. Wu and P. Maurine and N. Azemard and G. Ducharme. Microelectronic Journal, pp.263-276, 2012. 〈lirmm-00762085〉
  • Nadine Azemard, Philippe Maurine, Johan Vounckx. Power and Timing Modeling, Optimization and Simulation - Integration the VLSI Journal (Special Issue). Elsevier, 41 (2), pp.160, 2008. 〈lirmm-00189961〉
  • Nadine Azemard, Philippe Maurine, Johan Vounckx. PATMOS'06: Power and Timing Modeling, Optimization and Simulation - Integrated Circuit and System Design. J. Vounckx, N. Azémard, P. Maurine. Springer, pp.677, 2006, LNCS, 3-540-39094-4. 〈lirmm-00135046〉

Chapitre d'ouvrage7 documents

  • Pascal Benoit, Gilles Sassatelli, Philippe Maurine, Lionel Torres, Nadine Azemard, et al.. Towards Autonomous Scalable Integrated Systems. Design Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. 〈10.1007/978-94-007-1125-9_4〉. 〈lirmm-01399454〉
  • Victor Lomné, Amine Debhaoui, Philippe Maurine, Michel Robert, Lionel Torres. Side Channel Attacks. Security Trends for FPGAS From Secured to Secure Reconfigurable Systems, Springer, pp.47-72, 2011. 〈lirmm-00809329〉
  • Eduardo Wanderley, Romain Vaslin, Jérémie Crenne, Pascal Cotret, Jean-Philippe Diguet, et al.. SecurityFPGA Analysis. Security Trends for FPGAS - From Secured to Secure Reconfigurable Systems, pp.7-46, 2011. 〈lirmm-00809327〉
  • Hanitriniaina Razafindraibe, Michel Robert, Philippe Maurine. Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. Nadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.634-644, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. 〈10.1007/11847083_44〉. 〈lirmm-00109844〉
  • Daniel Auvergne, Philippe Maurine, Nadine Azemard. Modeling for Designing in Deep Sub-Micron Technologies. PIGUET C. Low-Power Electronics Design, CPR Press, 2004, 0-8493-1941-2. 〈lirmm-00109162〉
  • Michel Aline, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Feasible delay Bound Definition. SOC Design Methodologies, Kluwer Academic Publishers, pp.325-335, 2002. 〈lirmm-00239363〉
  • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Gate Sizing for Low Power Design. SOC Design Methodologies, Kluwer Academic Publishers, pp.301-312, 2002. 〈lirmm-00239359〉

Brevet3 documents

  • Philippe Maurine, Bruno Vaquie. Elément mémoire sécurises. France, N° de brevet: FR 2973138 (B1) WO/2012/127135 (A1). 2013, pp.N/A. 〈lirmm-00861489〉
  • Philippe Maurine, Lionel Vincent, Suzanne Lesecq, Edith Beigné. Système électronique à capteurs intégrés, procédé d'estimation de valeur de grandeur physique de fonctionnement et programme d'ordinateur correspondant. France, N° de brevet: 12 54781. 2012, pp.001-010. 〈lirmm-00762991〉
  • Bettina Rebaud, Philippe Maurine, Marc Belleville. Device for monitoring the operation of a digital circuit. France, N° de brevet: FR2944620 (A1) WO2010122036 (A1). 2010, pp.N/A. 〈lirmm-00402783〉

Autre publication3 documents

  • Maxime Lecomte, Jacques Jean-Alain Fournier, Philippe Maurine. Extraction of intrinsic structure for Hardware Trojan detection. Cryptology ePrint Archive: Report 2015/912. 2015, pp.2015/912. 〈lirmm-01319491〉
  • Florent Bruguier, Pascal Benoit, Philippe Maurine, Lionel Torres. Introduction à la sécurité numérique. Rencontres CAP’TRONIC, Saulxures (67), France, 22 mars 2013. 2013. 〈lirmm-01433825〉
  • Amine Debhaoui, Jean-Max Dutertre, Bruno Robisson, P. Orsatelli, Philippe Maurine, et al.. Injection of transient faults using electromagnetic pulses Practical results on a cryptographic system. Journal of Cryptology ePrint Archive: Report 2012/123. 2012. 〈emse-00742850〉