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Patrick Girard
21
Documents
Identifiants chercheurs
- patrick-girard-lirmm
- 0000-0003-0722-8772
Présentation
Publications
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Effective techniques for automatically improving the transition delay fault coverage of Self-Test LibrariesETS 2022 - 27th IEEE European Test Symposium, May 2022, Barcelona, Spain. pp.1-2, ⟨10.1109/ETS54262.2022.9810392⟩
Communication dans un congrès
lirmm-03739788v1
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Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage ImprovementIOLTS 2021 - 27th IEEE International Symposium on On-Line Testing and Robust System Design, Jun 2021, Torino, Italy. pp.1-4, ⟨10.1109/IOLTS52814.2021.9486711⟩
Communication dans un congrès
lirmm-03380201v1
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Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage ImprovementPESW 2021 - 9th Prague Embedded Systems Workshop, Jul 2021, Horoměřice, Czech Republic
Communication dans un congrès
lirmm-03988459v1
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An effective approach for functional test programs compactionDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. ⟨10.1109/DDECS.2016.7482466⟩
Communication dans un congrès
lirmm-01457396v1
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A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic CircuitsETS: European Test Symposium, May 2016, Amsterdam, Netherlands. ⟨10.1109/ETS.2016.7519296⟩
Communication dans un congrès
hal-01444734v1
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Improving the Functional Test Delay Fault Coverage: A Microprocessor Case StudyISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, PA, United States. pp.731-736, ⟨10.1109/ISVLSI.2016.42⟩
Communication dans un congrès
lirmm-01446917v1
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Exploring the impact of functional test programs re-used for power-aware testingDATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.1277-1280, ⟨10.7873/DATE.2015.1031⟩
Communication dans un congrès
lirmm-01272937v1
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Scan-chain intra-cell defects gradingDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. ⟨10.1109/DTIS.2015.7127349⟩
Communication dans un congrès
lirmm-01272696v1
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Design space exploration and optimization of a Hybrid Fault-Tolerant ArchitectureIOLTS: International On-Line Testing Symposium, Jul 2015, Halkidiki, Greece. pp.89-94, ⟨10.1109/IOLTS.2015.7229838⟩
Communication dans un congrès
lirmm-01272735v1
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An effective ATPG flow for Gate Delay FaultsDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. ⟨10.1109/DTIS.2015.7127350⟩
Communication dans un congrès
lirmm-01272719v1
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Peak Power Estimation: A Case Study on CPU CoresIEEE Asian Test Symposium, Nov 2012, Niigata, Japan. pp.167-172, ⟨10.1109/ATS.2012.58⟩
Communication dans un congrès
lirmm-00805389v1
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A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay TestingETS 2011 - 16th IEEE European Test Symposium, May 2011, Trondheim, Norway. pp.153-158, ⟨10.1109/ETS.2011.21⟩
Communication dans un congrès
lirmm-00647822v1
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An Exact and Efficient Critical Path Tracing AlgorithmDELTA'10: Electronic Design, Test and Application, Vietnam. pp.164-169, ⟨10.1109/DELTA.2010.35⟩
Communication dans un congrès
lirmm-00539738v1
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An Efficient Fault Simulation Technique for Transition Faults in Non-Scan Sequential CircuitsDDECS'09: 12th IEEE Symposium on Design and Diagnostics of Electronic Systems, pp.50-55
Communication dans un congrès
lirmm-00371197v1
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Proceedings of the 18th IEEE European Test Symposium (ETS 2013) - May 27-30, 2013 - Avignon, FranceIEEE, 2013, 978-1-4673-6375-4
Ouvrages
lirmm-01433571v1
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13th IEEE European Test Symposium (ETS'08)IEEE Computer Society, pp.250, 2008, 978-0-7695-3150-2
Ouvrages
lirmm-00326806v1
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