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Michel Robert
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Documents
Identifiants chercheurs
michel-robert-
0000-0002-5075-2898
Présentation
Michel ROBERT (PhD:1987) is Professor at the University of Montpellier (France), where he’s teaching microelectronics in the engineering program. His present research interests at the Montpellier Laboratory of Informatics, Robotics, and Micro-electronics ([LIRMM](https://www.lirmm.fr/)) are design and modelisation of system on chip architectures. He is author or co-author of more than 300 publications in the field of CMOS integrated circuits design. He has supervised around forty doctoral thesis. He chaired the IFIP WG 10.5 (International Federation for Information Processing) from 2007 to 2011.
He served as director of the doctoral school, of the LIRMM research laboratory, then of the laboratory of excellence for digital solutions and modeling for the environment and the living, before becoming president of the University of Montpellier (2012-2015). He has held various national responsibilities in monitoring and evaluation in higher education and research. He was Director of the Institutional Evaluation Department of the High Council for the Evaluation of Research and Higher Education (Hcéres) from 2016 to 2021.
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Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approachACM Transactions on Embedded Computing Systems (TECS), 2013, 12 (3), pp.75:22. ⟨10.1145/2442116.2442125⟩
Article dans une revue
lirmm-00818925v1
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Secure Triple Track Logic Robustness Against Differential Power and Electromagnetic AnalysesJournal of Integrated Circuits and Systems, 2009, 4 (1), pp.20-28. ⟨10.29292/jics.v4i1.293⟩
Article dans une revue
lirmm-03613238v1
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Uma Arquitetura Dinamicamente Reconfiguràvel para Criptografia Robusta contra Ataques pour Canais ColateraisREC'07: Actas das III Jornadas Sobre Sistemas Reconfiguràveis, Feb 2007, Lisboa, Portugal, pp.45-53
Communication dans un congrès
lirmm-00188346v1
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Architectural Issues in Homogeneous NOC-Based MPSOCRSP'07: 18th IEEE/IFIP International Workshop on Rapid System Prototyping, May 2007, Porto Alegre, Brazil, pp.139-142
Communication dans un congrès
lirmm-00179622v1
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A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPAIPDPS 2007 - 21th International Parallel and Distributed Processing Symposium, Mar 2007, Long Beach, CA, United States. pp.1-8
Communication dans un congrès
lirmm-00179638v1
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A Leak Resistant SoC to Counteract Side Channel AttacksSOC'06: International Symposium on System-On-Chip, Nov 2006, Tampere, Finlande, pp.N/A
Communication dans un congrès
lirmm-00352713v1
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A Leak Resistant Architecture Against Side Channel AttacksFPL: Field-Programmable Logic and Applications, Aug 2006, Madrid, Spain. pp.881-884, ⟨10.1109/FPL.2006.311335⟩
Communication dans un congrès
lirmm-00102784v1
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Current Mask Generation: an Analog Circuit to Thwart DPA AttacksVLSI-SoC 2005 - 13th International Conference on Very Large Scale Integration of System on Chip, Oct 2005, Perth, Australia. pp.317-330, ⟨10.1007/978-0-387-73661-7_20⟩
Communication dans un congrès
lirmm-00102782v1
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A GALS Network on Chip with Quality of Service supportSAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia Antipolis, France. pp.199-207
Communication dans un congrès
lirmm-00106526v1
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Current Mask Generation: A Transistor Level Security Against DPA AttacksSBCCI 2005 - 18th annual symposium on Integrated circuits and system design, Sep 2005, Florianolpolis, Brazil. pp.115-120, ⟨10.1145/1081081.1081114⟩
Communication dans un congrès
lirmm-03704230v1
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A Mesh Based Network on Chip characterization : A GALS ApproachDCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal. pp.10-15
Communication dans un congrès
lirmm-00106054v1
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Réseaux d'interconnexion pour les systèmes sur Puce : le réseau HERMESSCS 2004 - Signaux, Circuits et Systèmes, Mar 2004, Monastir, Tunisia. pp.35-40
Communication dans un congrès
lirmm-00352701v1
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Are Coarse Grain Reconfigurable Architectures Suitable for Cryptography?12th International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC), Dec 2003, Darmstadt, Germany. pp.276-281
Communication dans un congrès
lirmm-00269699v1
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A Physical Synthesis Design Flow based on Virtual ComponentsDCIS: Design of Circuits and Integrated Systems, Nov 2000, Montpellier, France. pp.740-745
Communication dans un congrès
lirmm-00239439v1
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Flexible Macrocell layout Generator4th ACM/SIGDA Physical Design Workshop, Layout Synthesis for the New Generation of VLSI ASIC Technologies, Apr 1993, UCLA Conference Center, CA, USA, pp.105-116
Communication dans un congrès
lirmm-00241344v1
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Tool Box for Performance Driven Macrocell layout SynthesisEurochip Workshop on VLSI Design Training, Sep 1993, Toledo, Spain. pp.56-61
Communication dans un congrès
lirmm-00241348v1
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Current Mask Generation: An Analog Circuit to Thwart DPA AttacksVLSI-SoC: From Systems to Silicon, Springer, pp.317-330, 2007, 978-0-387-73660-0
Chapitre d'ouvrage
lirmm-00203662v1
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Library free integrated circuit design for submicron technologies2002
Autre publication scientifique
lirmm-00259937v1
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Library Free Integrated Circuit Design for Submicron Technologies2000
Autre publication scientifique
lirmm-00259939v1
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Library Free Integrated Circuits for Submicron Technologies[Research Report] Lirmm, University of Montpellier. 2002
Rapport
lirmm-00268592v1
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