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Publications of Michel Robert


Michel ROBERT (PhD:1987) is Professor at the University of Montpellier (France), where he’s teaching microelectronics in the engineering program. His present research interests at the Montpellier Laboratory of Informatics, Robotics, and Micro-electronics (LIRMM) are design and modelisation of system on chip architectures. He is author or co-author of more than 300 publications in the field of CMOS integrated circuits design. He has supervised around forty doctoral thesis. He chaired the IFIP WG 10.5 (International Federation for Information Processing) from 2007 to 2011.

He served as director of the doctoral school, of the LIRMM research laboratory, then of the laboratory of excellence for digital solutions and modeling for the environment and the living, before becoming president of the University of Montpellier (2012-2015). He has held various national responsibilities in monitoring and evaluation in higher education and research. He was Director of the Institutional Evaluation Department of the High Council for the Evaluation of Research and Higher Education (Hcéres) from 2016 to 2021.


Journal articles22 documents

  • Michel Robert, Lionel Torres, Jean-Louis Bantignies, Romain Laffont. Les enjeux environnementaux et sociétaux en microélectronique : Impacts sur la formation. Journal sur l'enseignement des sciences et technologies de l'information et des systèmes, EDP Sciences, 2022, 21, pp.1006-1019. ⟨10.1051/j3ea/20221006⟩. ⟨lirmm-03693077⟩
  • Marcos de Melo da Silva, Abdoulaye Gamatié, Gilles Sassatelli, Michael Poss, Michel Robert. Optimization of Data and Energy Migrations in Mini Data Centers for Carbon-Neutral Computing. IEEE Transactions on Sustainable Computing, IEEE, In press, ⟨10.1109/TSUSC.2022.3197090⟩. ⟨lirmm-03746168⟩
  • Luciano Ost, Marcelo Mandelli, Gabriel Marchesan Almeida, Leandro Moller, Leandro Soares Indrusiak, et al.. Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach. ACM Transactions on Embedded Computing Systems (TECS), ACM, 2013, 12 (3), pp.75:22. ⟨10.1145/2442116.2442125⟩. ⟨lirmm-00818925⟩
  • Luciano Ost, Rafael Garibotti, Gilles Sassatelli, Gabriel Marchesan Almeida, Remi Busseuil, et al.. Novel Techniques for Smart Adaptive Multiprocessor SoCs. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2013, 62 (8), pp.1557-1569. ⟨10.1109/TC.2013.57⟩. ⟨lirmm-00820098⟩
  • Gilles Sassatelli, Olivier Brousse, Jérémie Guillot, François Grize, Thierry Gil, et al.. A Mobile Computing Framework for Pervasive Adaptive Platforms. International Journal of Distributed Sensor Networks, Hindawi Publishing Corporation, 2012, 2012, pp.#193864. ⟨10.1155/2012/193864⟩. ⟨lirmm-00820100⟩
  • Philippe Maurine, Amine Dehbaoui, Victor Lomné, Thomas Ordas, Lionel Torres, et al.. Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2012, 20 (3), pp.573-577. ⟨10.1109/TVLSI.2011.2104984⟩. ⟨lirmm-00761786⟩
  • Philippe Maurine, Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, et al.. Timing Slack Monitoring under Process and Environmental Variations: Application to a DSP Performance Optimization. Microelectronics Journal, Elsevier, 2011, 42 (5), pp.718-732. ⟨10.1016/j.mejo.2011.02.005⟩. ⟨lirmm-00607877⟩
  • Gabriel Marchesan Almeida, Remi Busseuil, Luciano Ost, Florent Bruguier, Gilles Sassatelli, et al.. Pi and pid regulation approaches for performance-constrained adaptive multiprocessor system-on-chip. IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers, 2011, 3 (3), pp.77-80. ⟨10.1109/LES.2011.2166373⟩. ⟨lirmm-00725660⟩
  • Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Nicolas Saint-Jean. Run Time Mapping for Dynamic Reconfiguration Management in Embedded Systems. International Journal of Embedded Systems, Inderscience, 2010, 4 (3/4), pp.276-291. ⟨10.1504/IJES.2010.039031⟩. ⟨lirmm-00818929⟩
  • Victor Lomné, Amine Dehbaoui, Thomas Ordas, Philippe Maurine, Lionel Torres, et al.. Secure Triple Track Logic Robustness Against Differential Power and Electromagnetic Analyses. Journal of Integrated Circuits and Systems, Brazilian Microelectronics Society, 2009, 4 (1), pp.20-28. ⟨10.29292/jics.v4i1.293⟩. ⟨lirmm-03613238⟩
  • Gabriel Marchesan Almeida, Gilles Sassatelli, Pascal Benoit, Nicolas Saint-Jean, Sameer Varyani, et al.. An Adaptive Message-Passing MPSoC Framework. International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, 2009, 2009, pp.#242981. ⟨10.1155/2009/242981⟩. ⟨lirmm-00373949⟩
  • Christel-Loic Tisse, Lionel Torres, Lionel Martin, Michel Robert. Systèmes Biométriques pour la Vérification d'Individu. Un exemple : l'iris. Traitement du Signal, Lavoisier, 2005, 22 (2), pp.99-119. ⟨lirmm-00105338⟩
  • Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, et al.. Méthode de caractérisation des architectures d'accélérateurs flexibles pour systèmes sur puce. Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, Lavoisier, 2005, 24 (6), pp.725-755. ⟨lirmm-00105324⟩
  • Alin Razafindraibe, Michel Robert, Philippe Maurine. Compact and Secured Primitives for the Design of Asynchronous Circuits. Journal of Low Power Electronics, American Scientific Publishers, 2005, 1 (1), pp.20-26. ⟨lirmm-00105365⟩
  • Alexis Landrault, Ludovic Pellier, Alexandre Richard, Christian Jay, Michel Robert, et al.. Transistor-Level Synthesis for Fast IP Migration. Electronics Systems and Software, Institution of Engineering and Technology, 2004, pp.25-29. ⟨lirmm-00108577⟩
  • Gilles Sassatelli, Pascal Benoit, Lionel Torres, Gaston Cambon, Jérôme Galy, et al.. Systolic Ring: A new approach for dynamical reconfigurable architectures. Traitement du Signal, Lavoisier, 2002, 19 (4), pp.293-313. ⟨lirmm-00268615⟩
  • Michel Robert. ASICs et Logiciels CAO Associés. Techniques de l'Ingenieur, Techniques de l'ingénieur, 2002, Électronique, TIP350WEB, pp.E2492. ⟨lirmm-00268617⟩
  • Camille Diou, Lionel Torres, Gilles Sassatelli, Michel Robert. Intégration d'une Architecture Récursive sur Silicium pour la Transformée en Ondelettes 2D. Traitement du Signal, Lavoisier, 2002, 19 (2), pp.101-117. ⟨lirmm-00268614⟩
  • Denis Deschacht, Michel Robert, Nadine Azemard, Daniel Auvergne. Post-Layout Timing Simulation of CMOS Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 1993, 12 (8), pp.1170-1177. ⟨10.1109/43.238609⟩. ⟨lirmm-00239206⟩
  • Michel Robert, Guy Cathébras, Nadine Azemard, Denis Deschacht, Daniel Auvergne. A Performance Driven Layout Synthesis Approach for Digital CMOS Cell Implementation. Integration, the VLSI Journal, Elsevier, 1993. ⟨lirmm-00239254⟩
  • Daniel Auvergne, Nadine Azemard, Denis Deschacht, Michel Robert. Input Waveform Slope Effects in CMOS Delays. IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 1990, 25 (6), pp.1588-1590. ⟨10.1109/4.62196⟩. ⟨lirmm-00239201⟩
  • Daniel Auvergne, Nadine Azemard, Guy Cathébras, Denis Deschacht, Michel Robert. Evaluation Dynamique et Optimisation des Structures CMOS et VLSI. Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, Lavoisier, 1989, 8 (6), pp.593-607. ⟨lirmm-00239199⟩

Conference papers118 documents

  • Thomas Leduc, Abdoulaye Gamatié, Daniel Siret, Gilles Sassatelli, Michel Robert. L’impact énergétique des flux de données numériques : Analyse des potentiels de déploiement d’une solution à la croisée des énergies renouvelables et de l’informatique distribuée dans l’environnement urbain. Colloque Energie du CNRS, Cellule énergie du CNRS, Dec 2021, Paris, France. ⟨hal-03521821⟩
  • Michel Robert. The Meaning of Assessment in Higher Education and Research. SBC/SBMicro/CASS-RS Special Event, IEEE CASS Rio Grande do Sul Chapter, Jun 2021, Rio Grande, Brazil. ⟨lirmm-03279878⟩
  • Francesco Di Gregorio, Abdoulaye Gamatié, Gilles Sassatelli, Arnaud Castelltort, Michel Robert. Exploration of Energy-Proportional Distributed Systems. 13ème Colloque National du GDR SOC², Jun 2019, Montpellier, France. ⟨hal-03326292⟩
  • Anastasiia Butko, Louisa Bessad, David Novo, Florent Bruguier, Abdoulaye Gamatié, et al.. OpenMP scheduling on ARM big.LITTLE architecture. MULTIPROG 2016 - 9th International Workshop on Programmability and Architectures for Heterogeneous Multicores, HIPEAC, Jan 2016, Prague, Czech Republic. ⟨lirmm-01377630⟩
  • Anastasiia Butko, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli, David Novo, et al.. Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration. MCSoC: Embedded Multicore/Many-core Systems-on-Chip, Sep 2016, Lyon, France. pp.201-208, ⟨10.1109/MCSoC.2016.20⟩. ⟨lirmm-01418745⟩
  • Anastasiia Butko, Abdoulaye Gamatié, Gilles Sassatelli, Lionel Torres, Michel Robert. Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.551-556, ⟨10.1109/ISVLSI.2015.28⟩. ⟨lirmm-01255927⟩
  • Rafael Garibotti, Luciano Ost, Remi Busseuil, Mamady Kourouma, Chris Adeniyi-Jones, et al.. Simultaneous multithreading support in embedded distributed memory MPSoCs. DAC 2013 - 50th Design Automation Conference, May 2013, Austin, United States. pp.83:1-83:7, ⟨10.1145/2463209.2488836⟩. ⟨lirmm-01391168⟩
  • Remi Busseuil, Lyonel Barthe, Gabriel Marchesan Almeida, Luciano Ost, Florent Bruguier, et al.. Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration. ReConFig 2011 - International Conference on Reconfigurable Computing and FPGAs, Nov 2011, Cancun, Mexico. pp.357-362, ⟨10.1109/ReConFig.2011.66⟩. ⟨hal-01139181⟩
  • Remi Busseuil, Gabriel Marchesan Almeida, Luciano Ost, Sameer Varyani, Gilles Sassatelli, et al.. Adaptation Strategies in Multiprocessors System on Chip. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Sep 2010, Madrid, Spain. pp.233-257, ⟨10.1007/978-3-642-28566-0_10⟩. ⟨hal-01515993⟩
  • Michel Robert. Adaptation in MP-SoCs: Opportunities for Meeting the Upcoming Design Challenges. NEWCAS 2010 - 8th IEEE International New Circuits and Systems Conference, Jun 2010, Montreal, QC, Canada. ⟨lirmm-00504878⟩
  • François Poucheret, Lyonel Barthe, Pascal Benoit, Lionel Torres, Philippe Maurine, et al.. Spatial EM Jamming: a Countermeasure Against EM Analysis ?. VLSI-SoC'10: 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, Madrid, Spain. pp.105-110. ⟨lirmm-00544358⟩
  • Gabriel Marchesan Almeida, Remi Busseuil, Sameer Varyani, Nicolas Hébert, Gilles Sassatelli, et al.. Providing Better Multi-Processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism. ReConFig 2010 - International Conference on ReConFigurable Computing and FPGAs, Dec 2010, Cancun, Mexico. pp.382-387, ⟨10.1109/ReConFig.2010.17⟩. ⟨lirmm-00548837⟩
  • Michel Robert, Gilles Sassatelli. Adaptative Integrated Systems for Optimal Hardware Usage. Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH 2010), Jan 2010, Chamonix, France. ⟨lirmm-00450767⟩
  • Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres, Michel Robert. Differential Power Analysis Enhancement with Statistical Preprocessing. DATE: Design, Automation and Test in Europe, 2010, Dresden, Germany. pp.1301-1304, ⟨10.1109/DATE.2010.5457007⟩. ⟨lirmm-00548738⟩
  • Philippe Maurine, Amine Dehbaoui, Thomas Ordas, Victor Lomné, Lionel Torres, et al.. Incoherence Analysis and its Application to Time Domain EM Analysis of Secure Circuits. APEMC 2010 - Asia-Pacific Symposium on Electromagnetic Compatibility, Apr 2010, Beijing, China. pp.1039-1042, ⟨10.1109/APEMC.2010.5475481⟩. ⟨lirmm-00607894⟩
  • Olivier Brousse, Gilles Sassatelli, Thierry Gil, Yoann Guillemenet, Michel Robert, et al.. Baf: A Bio-Inspired Agent Framework for Distributed Pervasive Applications. GEM'08: Genetic and Evolutionary Mechanisms, Las Vegas, USA, pp.N/A. ⟨lirmm-00374063⟩
  • Olivier Brousse, Gilles Sassatelli, Thierry Gil, Michel Robert, François Grize, et al.. The Perplexus Programming Framework: Combining Bio-inspiration and Agent-Oriented Programming for the Simulation of Large Scale Complex Systems. ICES'08: Evolvable Systems: From Biology to Hardware - 8th International Conference, Prague, Czech Republic, pp.402-407. ⟨lirmm-00373584⟩
  • Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, et al.. Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.266-275, ⟨10.1007/978-3-642-11802-9_31⟩. ⟨lirmm-00433462⟩
  • Bettina Rebaud, Marc Belleville, Edith Beigné, Michel Robert, Philippe Maurine, et al.. Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variations. FTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Suisse. ⟨lirmm-00404810⟩
  • Michel Robert. Systèmes intégrés "Hétérogènes" Flexibles. FETCH'09: Ecole d'Hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes, Jan 2009, Chexbres, Switzerland. ⟨lirmm-00358501⟩
  • Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, et al.. Triple Rail Logic Robustness Against DPA. ReConFig'08: International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp.415-420. ⟨lirmm-00350573⟩
  • Bettina Rebaud, Marc Belleville, Edith Beigné, Michel Robert, Philippe Maurine, et al.. On-Chip Timing Slack Monitoring. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2009, Florianopolis, Brazil. pp.89-94, ⟨10.1109/VLSISOC.2009.6041336⟩. ⟨lirmm-00429350⟩
  • Olivier Brousse, Jérémie Guillot, Thierry Gil, François Grize, Gilles Sassatelli, et al.. JubiTool: Unified Design Flow for the Perplexus SIMD Hardware Accelerator. CEC'09: IEEE Congress on Evolutionary Computation, 2009, Trondheim, Norway. pp.2070-2075. ⟨lirmm-00372859⟩
  • Amine Dehbaoui, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert. Enhancing Electromagnetic Attacks using Spectral Coherence based Cartography. VLSI-SoC 2009 - 17th IFIP International Conference on Very Large Scale Integration, Oct 2009, Florianopolis, Brazil. pp.11-16, ⟨10.1109/VLSISOC.2009.6041323⟩. ⟨lirmm-00429342⟩
  • Bettina Rebaud, Marc Belleville, Edith Beigné, Michel Robert, Philippe Maurine, et al.. An Innovative Timing Slack Monitor for Variation Tolerant Circuits. ICICDT: International Conference on IC Design & Technology, May 2009, Austin, TX, United States. pp.215-218, ⟨10.1109/ICICDT.2009.5166299⟩. ⟨lirmm-00371174⟩
  • Olivier Brousse, Jérémie Guillot, Gilles Sassatelli, Thierry Gil, Michel Robert, et al.. A Bio-Inspired Agent Framework for Hardware Accelerated Distributed Pervasive Applications. AHS'09: NASA/ESA Conference on Adaptive Hardware and Systems, Jul 2009, San Fransisco, United States. pp.415-422, ⟨10.1109/AHS.2009.54⟩. ⟨lirmm-00419914⟩
  • Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, et al.. Evaluation on FPGA of Triple Rail Logic Robustness Against DPA and DEMA. DATE: Design, Automation and Test in Europe, 2009, Nice, France. pp.634-639, ⟨10.1109/DATE.2009.5090744⟩. ⟨lirmm-00372847⟩
  • Olivier Brousse, Gilles Sassatelli, Thierry Gil, Michel Robert, Lionel Torres. Perplexus Project Programming Framework. ICESCA'08: International Conference on Embedded Systems & Critical Applications, May 2008, Gammarth, Tunisia. pp.35-40. ⟨lirmm-00282971⟩
  • Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert. MPI-Based Adaptive Task Migration Support on the HS-Scale System. ISVLSI 2008 - IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France. pp.105-110, ⟨10.1109/ISVLSI.2008.87⟩. ⟨lirmm-00280687⟩
  • Bettina Rebaud, Zeqin Wu, Marc Belleville, Christian Bernard, Michel Robert, et al.. Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétique. JNRDM: Journées Nationales du Réseau Doctoral en Microélectronique, May 2008, Bordeaux, France. ⟨lirmm-00281175v2⟩
  • Michael Yap San Min, Patrick Maurine, Michel Robert, Magali Bastian Hage-Hassan. Statistical Sizing Methodology of an SRAM in Presence of Signal Races and Variability Conditions. IFIP VLSI-SOC 2008 - IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, pp.193-198. ⟨lirmm-00332762⟩
  • Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, et al.. A Novel Approach for Architectural Models Characterization. An Exemple Through the Systolic Ring. FPL'03: 12th International Workshop on Field-Programmable Logic and Applications, Lisbon (Portugal), pp. 722-732. ⟨lirmm-00269558⟩
  • Michel Robert. Circuits et Systèmes Microélectroniques Complexes : Modélisation et Calcul Scientifique. Académie des Technologies, France. pp.P nd. ⟨lirmm-00269736⟩
  • Victor Lomné, Rafael A. Soares, Thomas Ordas, Philippe Maurine, Lionel Torres, et al.. Prototyping Secure Triple Track Logic (STTL) Robustness Against DPA & DEMA on FPGA. CryptArchi: Cryptographic Architectures, Jun 2008, Tregastel, France. ⟨lirmm-00373539⟩
  • Lionel Torres, Pascal Lepinay, Michel Robert, Guy Cathébras. Une Nouvelle Opération au CNFM : Le Programme SoC (Système sur Puce). CNFM'02 : 7èmes Journées Pédagogiques du Comité National de Formation en Microélectronique, St Malo (France), France. pp. 67-70. ⟨lirmm-00269345⟩
  • Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert. Bio-Inspiration Helps Computers: An New Machine. FPL'08: The 18th International Conference on Field-Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.697-698. ⟨lirmm-00326534⟩
  • Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, et al.. Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩. ⟨lirmm-00280809⟩
  • Michael Yap San Min, Philippe Maurine, Magali Bastian Hage-Hassan, Michel Robert. Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects. ISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, pp.310-315. ⟨lirmm-00280716⟩
  • Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, et al.. Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numérique. FTFC: Faible Tension - Faible Consommation, May 2008, Louvain-La-Neuve, Belgique. ⟨lirmm-00283731⟩
  • Michael Yap San Min, Philippe Maurine, Magali Bastian Hage-Hassan, Michel Robert. A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. DELTA 2008 - 4th IEEE International Symposium on Electronic Design, Test and Applications, Jan 2008, Hong Kong, China. pp.107-110, ⟨10.1109/DELTA.2008.72⟩. ⟨lirmm-00243966⟩
  • Bettina Rebaud, Marc Belleville, Christian Bernard, Michel Robert, Patrick Maurine, et al.. A Comparative Study of Variability Impact on Static Flip-Flop Timing Characteristics. ICICDT: International Conference on IC Design and Technology, Jun 2008, Grenoble, France. pp.167-170. ⟨lirmm-00305246⟩
  • Yoann Guillemenet, Ilham Hassoune, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon, et al.. A Non-Volatile Field Programmable Gate Array using Thermally Assisted Switching MRAMs. ICESCA'08: International Conference on Embedded Systems & Critical Applications, May 2008, Gammarth, Tunisia. pp.95-100. ⟨lirmm-00282964⟩
  • Rafael A. Soares, Ney Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, et al.. Evaluating the Robustness of Secure Triple Track Logic Through Prototyping. SBCCI'08: Symposium on Integrated Circuits and Systems Design, Sep 2008, Gramado, Brazil, France. pp.193-198, ⟨10.1145/1404371.1404425⟩. ⟨lirmm-00373516⟩
  • Hanitriniaina Razafindraibe, Michel Robert, Philippe Maurine. Improvement of Dual Rail Logic as a Countermeasure Against DPA. VLSI-SoC 2007 - IFIP International Conference on Very Large Scale Integration, Oct 2007, Atlanta, GA, United States. pp.270-275, ⟨10.1109/VLSISOC.2007.4402510⟩. ⟨lirmm-00186174⟩
  • Michael Yap San Min, Philippe Maurine, Michel Robert, Magali Bastian Hage-Hassan. Process Variability Considerations in the Design of an eSRAM. MTDT 2007 - IEEE International Workshop on Memory Technology, Design and Testing, Dec 2007, Taipei, Taiwan. pp.23-26, ⟨10.1109/MTDT.2007.4547609⟩. ⟨lirmm-00275258⟩
  • Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert. Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems. Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Jul 2007, Samos, Greece. pp.88-95, ⟨10.1109/ICSAMOS.2007.4285738⟩. ⟨lirmm-00179513⟩
  • Daniel Mesquita, Fernando Gehm Moraes, Ney Calazans, Lionel Torres, Michel Robert. Uma Arquitetura Dinamicamente Reconfiguràvel para Criptografia Robusta contra Ataques pour Canais Colaterais. REC'07: Actas das III Jornadas Sobre Sistemas Reconfiguràveis, Feb 2007, Lisboa, Portugal, pp.45-53. ⟨lirmm-00188346⟩
  • Bettina Rebaud, Marc Belleville, Christian Bernard, Michel Robert, Philippe Maurine. Méthodologie d'estimation de l'influence de la variabilité sur un opérateur numérique. FTFC'07 : 6èmes journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France, France. pp.N/A. ⟨lirmm-00204621⟩
  • Michael Yap San Min, Philippe Maurine, Magali Bastian Hage-Hassan, Michel Robert. Process Variabilities and Performances in a 90nm embedded SRAM. IEEE International Integrated Reliability Workshop, Oct 2007, pp.050-055. ⟨lirmm-00198373⟩
  • Olivier Brousse, Yoann Guillemenet, Gilles Sassatelli, Thierry Gil, Michel Robert, et al.. The Perplexus Project. DASIP'07: Workshop on Design and Architectures for Signal and Image Processing, Nov 2007, Grenoble, France, France. pp.N/A. ⟨lirmm-00202692⟩
  • Michael Yap San Min, Philippe Maurine, Magali Bastian Hage-Hassan, Michel Robert. Variabilité de Process et Performances des Mémoires SRAM Embarquées. FTFC'07: 6èmes Journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France, pp.7-11. ⟨lirmm-00178319⟩
  • Gilles Sassatelli, Nicolas Saint-Jean, Michel Robert, Cristiane Woszezenki, Isamael Augusto Grehs, et al.. Architectural Issues in Homogeneous NOC-Based MPSOC. RSP'07: 18th IEEE/IFIP International Workshop on Rapid System Prototyping, May 2007, Porto Alegre, Brazil, pp.139-142. ⟨lirmm-00179622⟩
  • Alin Razafindraibe, Michel Robert, Philippe Maurine. Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.340-351, ⟨10.1007/978-3-540-74442-9_33⟩. ⟨lirmm-00175100⟩
  • Gilles Sassatelli, Nicolas Saint-Jean, Pascal Benoit, Lionel Torres, Michel Robert. An Adaptative MP-SoC Architecture for Embedded Systems. CAR'07: 2nd National Workshop on Control Architectures of Robots: From Models to Execution on Distributed Control Architectures, Jun 2007, Paris, France. pp.101-107. ⟨lirmm-00179505⟩
  • Nicolas Saint-Jean, Camille Jalier, Gilles Sassatelli, Pascal Benoit, Lionel Torres, et al.. HS Scale: A Run-Time Adaptable MP-SoC Architecture. ReCoSoC'07: International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2007, Montpellier, France. pp.CDROM. ⟨lirmm-00179482⟩
  • Daniel Mesquita, Lionel Torres, Michel Robert, Fernando Gehm Moraes, Benoit Badrignans. A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA. IPDPS 2007 - 21th International Parallel and Distributed Processing Symposium, Mar 2007, Long Beach, CA, United States. pp.1-8. ⟨lirmm-00179638⟩
  • Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert. HS-Scale: A Hardware-Software Scalable MP-SOC Architecture for Embedded Systems. ISVLSI'07: IEEE Computer Society Annual Symposium on VLSI, 2007, Porto Allegre, Brazil, pp.21-28. ⟨lirmm-00154074⟩
  • Daniel Mesquita, Lionel Torres, Benoit Badrignans, Fernando Gehm Moraes, Gilles Sassatelli, et al.. A Leak Resistant SoC to Counteract Side Channel Attacks. SOC'06: International Symposium on System-On-Chip, Nov 2006, Tampere, Finlande, pp.N/A. ⟨lirmm-00352713⟩
  • Hanitriniaina Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin. Security Evaluation of Dual Rail Logic Against DPA Attacks. VLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration, Oct 2006, Nice, France. pp.181-186, ⟨10.1109/VLSISOC.2006.313230⟩. ⟨lirmm-00109692⟩
  • Benoit Badrignans, Daniel Mesquita, Jean-Claude Bajard, Lionel Torres, Gilles Sassatelli, et al.. Implémentation Matérielle d'une Arithmétique Résistante aux Fuites. RenPar'17 Rencontres Francophones en Parallélisme, CFSE'5 : Conférence Française sur les Systèmes d'Exploitation,SympAAA'06 : Symposium en Architecture et Adéquation Algorithme Architecture, Oct 2006, Canet en Roussillon (France), pp.57-74. ⟨lirmm-00107317⟩
  • Daniel Mesquita, Lionel Torres, Benoit Badrignans, Gilles Sassatelli, Michel Robert, et al.. A Leak Resistant Architecture Against Side Channel Attacks. FPL: Field-Programmable Logic and Applications, Aug 2006, Madrid, Spain. pp.881-884, ⟨10.1109/FPL.2006.311335⟩. ⟨lirmm-00102784⟩
  • Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, et al.. Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager. ISVLSI'06: IEEE Computer Society Annual Symposium on VLSI, Mar 2006, Karlsruhe (Germany), pp.251-256. ⟨lirmm-00102766⟩
  • Fabrice Gensolen, Guy Cathébras, Lionel Martin, Michel Robert. Focal Plane Integration of Image Texture Coding for Pixel Correspondence. PRIME: PhD Research in Microelectronics and Electronics, Jul 2005, Lausanne, Switzerland. pp.327-330. ⟨lirmm-00106065⟩
  • Fabrice Gensolen, Guy Cathébras, Lionel Martin, Michel Robert. An Integrated Image Motion Sensor for Micro Camera Module. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2005, Perth, Australia. pp.333-338. ⟨lirmm-00106497⟩
  • Fabrice Gensolen, Guy Cathébras, Lionel Martin, Michel Robert. Pixel Level Silicon Integration of Motion Estimation. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2005, Sopron, Hungary. pp.93-98. ⟨lirmm-00105989⟩
  • Gilles Sassatelli, Lionel Torres, Séverine Riso, Michel Robert. Packet-Switching Network-On-Chip Features Exploration and Characterization. VLSI-SOC'05: IFIP International Conference on Very Large Scale Integration, Oct 2005, Perth (Australia), pp.403-409. ⟨lirmm-00106440⟩
  • Alin Razafindraibe, Michel Robert, Philippe Maurine. Design of Compact Dual Rail Asynchronous Primitives. DCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, 2005, Lisbonne, Portugal. ⟨lirmm-00106434⟩
  • Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine. A Method to Design Compact Dual-rail Asynchronous Primitives. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.571-580, ⟨10.1007/11556930_58⟩. ⟨hal-00105846⟩
  • Daniel Gomes Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, et al.. Current Mask Generation: A Transistor Level Security Against DPA Attacks. SBCCI 2005 - 18th annual symposium on Integrated circuits and system design, Sep 2005, Florianolpolis, Brazil. pp.115-120, ⟨10.1145/1081081.1081114⟩. ⟨lirmm-03704230⟩
  • Séverine Riso, Lionel Torres, Gilles Sassatelli, Michel Robert, Fernando Gehm Moraes. A GALS Network on Chip with Quality of Service support. SAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia Antipolis, France. pp.199-207. ⟨lirmm-00106526⟩
  • Pascal Benoit, Gilles Sassatelli, Lionel Torres, Gaston Cambon, Michel Robert, et al.. Run-Time Scheduling for Random Multi Tasking in Reconfigurable Coprocessors. FPL'05 IEEE : 15th International Workshop on Field-Programmable Logic and Applications, Aug 2005, Tampere (Finlande), pp.703-706. ⟨lirmm-00106057⟩
  • Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathébras, et al.. Current Mask Generation: an Analog Circuit to Thwart DPA Attacks. VLSI-SoC 2005 - 13th International Conference on Very Large Scale Integration of System on Chip, Oct 2005, Perth, Australia. pp.317-330, ⟨10.1007/978-0-387-73661-7_20⟩. ⟨lirmm-00102782⟩
  • Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine. Asynchronous Dual rail Cells to Secure Cryptosystem Against Side Channel Attacks. SAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia-Antipolis. ⟨lirmm-00106539⟩
  • Fabrice Gensolen, Guy Cathébras, Lionel Martin, Michel Robert. Estimation du Mouvement Global par Mesures Locales Périphériques. READ: Rétines Electroniques / Asic-FPGA et DSP pour la Vision et le Traitement d'Images en Temps Réel, Jun 2005, Institut National des Télécommunications, Ivry, France. pp.77-82. ⟨lirmm-00106520⟩
  • Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon. Gestion Matérielle du Parallélisme pour les Architectures Reconfigurables à Grain Epais. JFAAA'05: Journées Francophones sur l'Adéquation Algorithme Architecture, Jan 2005, Dijon, France. pp.15-20. ⟨lirmm-00106510⟩
  • Alin Razafindraibe, Philippe Maurine, Michel Robert. La Technologie Asynchrone QDI pour la Sécurité des Cryptosystèmes. JNRDM'05 : 8ièmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France. pp.461-463. ⟨lirmm-00106530⟩
  • Laurent Latorre, Yves Bertrand, Michel Robert, Marie-Lise Flottes. Test Engineering Education in Europe: The EuNICE Test Project. EDUTECH'05, 2005, France. ⟨lirmm-00106506⟩
  • Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon. Automatic Task Scheduling/Loop Unrolling Using Dedicated RTR Controllers in Coarse Grain Recongigurable Architectures. IPDPS'05: International Parallel and Distributed Processing Symposium, RAW'05: Reconfigurable Architectures Workshop, Apr 2005, Denver, Colorado (USA), pp.148. ⟨lirmm-00105985⟩
  • Alin Razafindraibe, Michel Robert, Philippe Maurine. Méthode de Conception de Primitives Asynchrones Double Rail. FTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.23-27. ⟨lirmm-00106003⟩
  • Fabrice Gensolen, Guy Cathébras, Lionel Martin, Michel Robert. An Image Sensor with Global Motion Estimation for Micro Camera Module. ACIVS: Advanced Concepts for Intelligent Vision Systems, Sep 2005, Anvers, Belgium. pp.713-721. ⟨lirmm-00106498⟩
  • Gilles Sassatelli, Lionel Torres, Séverine Riso, Michel Robert, Fernando Gehm Moraes. A Mesh Based Network on Chip characterization : A GALS Approach. DCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal. pp.10-15. ⟨lirmm-00106054⟩
  • Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon. A RTR Hardware Controller for DSP Kernel Scheduling in Coarse Grain Reconfigurable Architecture. IPDPS'05: International Parallel and Distributed Processing SymposiumRAW'05: Reconfigurable Architectures Workshop, Apr 2005, pp.485-489. ⟨lirmm-00105958⟩
  • Séverine Riso, Michel Robert, Lionel Torres, Gilles Sassatelli. Réseau d'interconnexion pour les systèmes sur puces. JNRDM'04: 7èmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2004, Marseille, France. pp.451-453. ⟨lirmm-00355900⟩
  • Séverine Riso, Gilles Sassatelli, Lionel Torres, Michel Robert, Fernando Gehm Moraes. Réseau d'Interconnexion pour les Systèmes sur Puce : le Réseau HERMES. 2004, pp. 35-40. ⟨hal-00005844⟩
  • Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, et al.. Metrics for Digital Signal Processing Architectures Characterization: Remanance and Scability. Computer Systems: Architectures Modelling and Simulation, Jul 2004, Samos (Greece), pp.128-137. ⟨lirmm-00108930⟩
  • Michel Robert. Défi en CAO de Circuits et Systèmes Intégrés : Recherche, Formations, Métiers. CNFM'04 : 8ème Journées Pédagogiques du Comité National de Formation en Microélectronique, 2004, Saint-Malo, France. pp. 31-37. ⟨hal-00005846⟩
  • Michel Robert. CAO des Circuits et Systèmes sur Puce : Etat de l'Art, Enjeux et Perspectives Scientifiques. Architectures d'Interfaces et MicrocontrôleursPuissance en Electronique, May 2004, Carry le Rouet, France. ⟨lirmm-00108669⟩
  • Gilles Sassatelli, Lionel Torres, Séverine Riso, Michel Robert. Réseaux d'interconnexion pour les systèmes sur Puce : le réseau HERMES. IEEE SCS'04: Signaux, Circuits, Systèmes, Mar 2004, Monastir, Tunisia. pp.35-40. ⟨lirmm-00352701⟩
  • Olivier Omedes, Michel Robert, Mohamed Ramdani. Block Constraints Budgeting in Timing-Driven Hierarchical Flow. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.930-935. ⟨lirmm-00108941⟩
  • Alexis Landrault, Nadine Azemard, Philippe Maurine, Michel Robert, Daniel Auvergne. Design Optimization with Automated Cell Generation. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.722-731, ⟨10.1007/978-3-540-30205-6_74⟩. ⟨lirmm-00108894⟩
  • Gaston Cambon, Michel Robert, Gilles Sassatelli, Lionel Torres. System On Chip (SOC) : Du Composant... au Composant. Journées Nationales du GDR et RTP Nanoélectronique, May 2004, Aussois, France. ⟨lirmm-00108673⟩
  • Alexis Landrault, Nadine Azemard, Philippe Maurine, Michel Robert, Daniel Auvergne. Automatic Layout Synthesis Based Performance Optimization. IWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85. ⟨lirmm-00108654⟩
  • Alin Razafindraibe, Michel Robert, Bertrand Folco, Philippe Maurine, Ghislain Fraidy Bouesse, et al.. Secured Structures for Secured Asynchronous QDI Circuits. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. ⟨hal-01393250⟩
  • Olivier Omedes, Michel Robert, Muhammad Ramdani. A Flexible Aware Budgeting for Hierarchical Flow Timing Closure. ICCAD 2004 - 1st IEEE International Conference on Computer Aided Design, Nov 2004, San Jose, United States. pp.261-265, ⟨10.1109/ICCAD.2004.1382583⟩. ⟨lirmm-00108940⟩
  • Guy Cathébras, S. Dussausay, Michel Robert, Philippe Maurine. Conception et Modélisation de Briques Elémentaires CMOS. CNFM'04 : 8ème Journées Pédagogiques du Comité National de Formation en Microélectronique, 2004, Saint-Malo, France. pp.35-37. ⟨lirmm-00108672⟩
  • Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, et al.. Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability. IPDPS: International Parallel and Distributed Processing Symposium, Apr 2003, Nice, France. pp.176-180, ⟨10.1109/IPDPS.2003.1213324⟩. ⟨lirmm-00269655⟩
  • Michel Robert. Systèmes Microélectroniques Complexes sur Puce (SOC) : Du Circuit à la Plateforme. Colloque Intertronic "Conception Numérique Intégrée : Hardware&Software", 2003, Montpellier, France. ⟨lirmm-00269734⟩
  • Alexis Landrault, Ludovic Pellier, Alexandre Richard, Christian Jay, Michel Robert, et al.. A Fast Prototyping and IP Migration Strategy Using Transistor Level Synthesis. SAME: Sophia-Antipolis Forum on MicroElectronics, Oct 2003, Sophia Antipolis, France. ⟨lirmm-00269697⟩
  • Alexis Landrault, Ludovic Pellier, Alexandre Richard, Christian Jay, Michel Robert, et al.. An I.P. Migration and Prototyping Strategy Using Transistor Level Synthesis. DCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. pp.266-271. ⟨lirmm-00269694⟩
  • Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, et al.. Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability. Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Jul 2003, Samos, Greece. pp.128-137. ⟨lirmm-00269656⟩
  • Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon. Comparaison des Architectures Dédiées au Traitement des Données Numériques. JNRDM'03 : 6ièmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2003, Toulouse (France), France. pp.115-117. ⟨lirmm-00269542⟩
  • Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, et al.. Comparaison d'Architectures Dédiées au Traitement Numériques des Données : du Processeur aux Architectures Reconfigurables. RenPar'15 : Rencontres Francophones en Parallélisme, CFSE'3 : Conférence Française sur les Systèmes d'Exploitation, SympAAA'03 : Symposium en Architecture et Adéquation Algorithme Architecture, Oct 2003, La Colle sur Loup (France), France. pp.322-326. ⟨lirmm-00269654⟩
  • Daniel Mesquita, Lionel Torres, Michel Robert, Gilles Sassatelli, Fernando Gehm Moraes. Are Coarse Grain Reconfigurable Architectures Suitable for Cryptography?. 12th International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC), Dec 2003, Darmstadt, Germany. pp.276-281. ⟨lirmm-00269699⟩
  • Pascal Benoit, Gilles Sassatelli, Michel Robert, Lionel Torres, Gaston Cambon, et al.. The Systolic Ring: A Scalable Dynamically Reconfigurable Core for Embedded Systems. SAME'02: Sophia-Antipolis Forum on MicroElectronics, Oct 2002, Sophia-Antipolis (France), France. pp.85-90. ⟨lirmm-00269322⟩
  • Pascal Benoit, Gilles Sassatelli, Michel Robert, Lionel Torres, Gaston Cambon, et al.. Architectures Reconfigurables Dynamiquement pour Applications TSI. Colloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.67-70. ⟨lirmm-00269321⟩
  • Christel-Loic Tisse, Lionel Martin, Lionel Torres, Michel Robert. Iris Recognition System for Person Identification. PRIS: Pattern Recognition in Information Systems, 2002, Alicante, Spain. pp.71-75. ⟨lirmm-00268616⟩
  • Pascal Benoit, Gilles Sassatelli, Lionel Torres, Thierry Gil, Gaston Cambon, et al.. Caractérisation et Comparaison d'Architectures Reconfigurables Dynamiquement, Un Exemple : Le Systolic Ring. JFAAA'02: Journées Francophones sur l'Adéquation Algorithme Architecture, Dec 2002, Monastir (Tunisie), France. pp.30-34. ⟨lirmm-00269344⟩
  • Christel-Loic Tisse, Lionel Martin, Lionel Torres, Michel Robert. Person Identification Technique Using Human Iris Recognition. IV 2002 - 15th International Conference on Vision Interface, May 2002, Calgary, Canada. pp.294-299. ⟨lirmm-00269539⟩
  • Michel Robert. Systèmes Microélectroniques Complexes sur Puce (SoC). CNFM: Comité National de Formation en Microélectronique, Nov 2002, St Malo, France. ⟨lirmm-00269346⟩
  • Camille Diou, Lionel Torres, Michel Robert. A wavelet core for video processing. ICIP 2000 - 7th IEEE International Conference on Image Processing, Sep 2000, Vancouver, Canada. pp.395-398, ⟨10.1109/ICIP.2000.899406⟩. ⟨lirmm-03704303⟩
  • Fernando Gehm Moraes, Michel Robert, Daniel Auvergne, Nadine Azemard. A Physical Synthesis Design Flow based on Virtual Components. DCIS: Design of Circuits and Integrated Systems, Nov 2000, Montpellier, France. pp.740-745. ⟨lirmm-00239439⟩
  • Fernando Gehm Moraes, Nadine Azemard, Michel Robert, Daniel Auvergne. Tool Box for Performance Driven Macrocell layout Synthesis. Eurochip Workshop on VLSI Design Training, Sep 1993, Toledo, Spain. pp.56-61. ⟨lirmm-00241348⟩
  • Fernando Gehm Moraes, Nadine Azemard, Michel Robert, Daniel Auvergne. Flexible Macrocell layout Generator. 4th ACM/SIGDA Physical Design Workshop, Layout Synthesis for the New Generation of VLSI ASIC Technologies, Apr 1993, UCLA Conference Center, CA, USA, pp.105-116. ⟨lirmm-00241344⟩
  • Daniel Auvergne, Sylvie Amat, Myrian Mellah, Nadine Azemard, Michel Robert. Evaluation of Speed up Strategy from Gate Performance Modelling. IFIP Workshop on Logic and Architecture Synthesis, Dec 1993, Grenoble, France, pp.193-208. ⟨lirmm-00241358⟩
  • Nadine Azemard, Denis Deschacht, Michel Robert, Daniel Auvergne. Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor Sising. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 1992, Paris, France. pp.102-108. ⟨lirmm-00241327⟩
  • Daniel Auvergne, Nadine Azemard, Vincent Bonzom, Denis Deschacht, Michel Robert. Formal Sizing Rules of CMOS Circuits. EDAC 1991 - European Conference on Design Automation, Feb 1991, Amsterdam, Netherlands. pp.96-100, ⟨10.1109/EDAC.1991.206368⟩. ⟨lirmm-00239374⟩
  • Daniel Auvergne, Nadine Azemard, Denis Deschacht, Michel Robert. An Accurate and Efficient Delay Time Modelling and its Application to CMOS Data Path Evaluation and Transistor Sizing. World Congress on Computation and Applied Mathematics, IMACS: International Association for Mathematics and Computers in Simulation, Jul 1991, Dublin, Ireland. pp.1661-1663. ⟨lirmm-00239387⟩
  • Michel Robert, Joel Trauchessec, Guy Cathébras, Vincent Bonzom, Nadine Azemard, et al.. Evaluation of VLSI Layout Implementation for Efficiency. EURO-ASIC 1991 - European Conference on Design Automation with European Event in ASIC Design, May 1991, Paris, France. pp.362-365, ⟨10.1109/EUASIC.1991.212836⟩. ⟨lirmm-00239384⟩

Poster communications6 documents

  • Olivier Brousse, Gilles Sassatelli, Thierry Gil, François Grize, Michel Robert, et al.. Distributed Pervasive Phylogenetic Application using a Bio-Inspired Agent Framework. Colloque GDR SoC-SiP, 2008, Paris, France. 2008. ⟨lirmm-00406765⟩
  • Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert. Towards Self-Adaptability a Scalable MP-SOC Architecture Approach. Colloque du GDR SoC-SiP, 2007, Paris, France. 2007. ⟨lirmm-00406773⟩
  • Olivier Brousse, Gilles Sassatelli, Thierry Gil, Michel Robert, Lionel Torres. Perplexus Project. Colloque du GDR SoC-SiP, 2007, Paris, France. 2007. ⟨lirmm-00406772⟩
  • Laurent Latorre, Yves Bertrand, Marie-Lise Flottes, Michel Robert. Test Engineering Education in Europe: The CRTC Experience Through the EuNICE-Test Project. Achim Rettberg and Christophe Bobda. IFIP TC10 Working Conference: EduTech'05, Oct 2005, France. pp.63-77, 2005. ⟨lirmm-00106564⟩
  • Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon. Dynamic Hardware Multiplexing for Coarse Grain Reconfigurable Architectures. FPGA'05: ACM/SIGDA 9th International Symposium on Field Programmable Gate Arrays, Feb 2005, Monterey, CA, United States. ACM Press, 2005. ⟨lirmm-00105959⟩
  • Gilles Sassatelli, Lionel Torres, Séverine Riso, Michel Robert. Packet-Switching Network-On-Chip Feature Exploration and Characterization. RECoSoC'05: Reconfigurable Communication-Centric SoCs, Jun 2005, Montpellier, France. 2005. ⟨lirmm-00355893⟩

Books1 document

  • Michel Robert. Le sens de l'évaluation dans l'enseignement supérieur et la recherche. 2020, 978-2-9573353-0-5. ⟨lirmm-02917486⟩

Book sections7 documents

  • Pascal Benoit, Gilles Sassatelli, Philippe Maurine, Lionel Torres, Nadine Azemard, et al.. Towards Autonomous Scalable Integrated Systems. Design Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. ⟨10.1007/978-94-007-1125-9_4⟩. ⟨lirmm-01399454⟩
  • Lionel Torres, Pascal Benoit, Gilles Sassatelli, Michel Robert, Fabien Clermidy, et al.. An Introduction to Multi-Core System on Chip - Trends and Challenges. Hübner, Michael; Becker, Jürgen. Multiprocessor System-on-Chip - Hardware Design and Tool Integration, Springer, pp.1-21, 2011, Chapter 1, 978-1-4419-6459-5. ⟨10.1007/978-1-4419-6460-1_1⟩. ⟨lirmm-00574947⟩
  • Victor Lomné, Amine Dehbaoui, Philippe Maurine, Michel Robert, Lionel Torres. Side Channel Attacks. Security Trends for FPGAS
    From Secured to Secure Reconfigurable Systems
    , Springer, pp.47-72, 2011, 978-94-007-1337-6. ⟨10.1007/978-94-007-1338-3_3⟩. ⟨lirmm-00809329⟩
  • Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathébras, et al.. Current Mask Generation: An Analog Circuit to Thwart DPA Attacks. VLSI-SoC: From Systems to Silicon, Springer, pp.317-330, 2007, 978-0-387-73660-0. ⟨lirmm-00203662⟩
  • Hanitriniaina Razafindraibe, Michel Robert, Philippe Maurine. Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. Nadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.634-644, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. ⟨10.1007/11847083_44⟩. ⟨lirmm-00109844⟩
  • Gilles Sassatelli, Lionel Torres, Pascal Benoit, Gaston Cambon, Michel Robert, et al.. Dynamically Reconfigurable Architectures for Digital Signal Processing Applications. SOC Design Methodologies, 90, Kluwer Academic Publishers 2002, pp.63-74, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_6⟩. ⟨lirmm-00108929⟩
  • Camille Diou, Lionel Torres, Michel Robert. Implementation of a Wavelet Transform Architecture for Image Processing. VLSI: Systems on a Chip, 34, Springer US, pp.101-112, 2000, IFIP Advances in Information and Communication Technology, 978-1-4757-1014-4. ⟨10.1007/978-0-387-35498-9_10⟩. ⟨lirmm-03704293⟩

Directions of work or proceedings2 documents

  • Michel Robert, Michel Renovell, Samir Ben Ahmed, Slim Ben Saoud. First International Conference on Embedded Systems and Critical Applications (ICESCA 2008). May 2008, Tunis, Tunisia. 2008. ⟨lirmm-00342663⟩
  • Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes. SOC Design Methodologies: IFIP TC10 / WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC’01) December 3–5, 2001, Montpellier, France. Springer, 2002, ⟨10.1007/978-0-387-35597-9⟩. ⟨hal-00083323⟩

Patents3 documents

  • Gilles Sassatelli, Abdoulaye Gamatié, Michel Robert. Data Processing System with Energy Transfer. France, Patent n° : WO2017178571. 2016. ⟨lirmm-02145436⟩
  • Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, Jérôme Galy, et al.. Architecture de Transport de Données en Anneau comprenant un Réseau de Rétropopagation. États-Unis, N° de brevet: 0204162. 9764. 2002, pp.P/N. ⟨lirmm-00268654⟩
  • Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, Jérôme Galy, et al.. Architecture de Calcul Logique comprenant plusieurs Modes de Configuration. États-Unis, N° de brevet: 0204161. 9763. 2002, pp.P/N. ⟨lirmm-00268653⟩

Other publications5 documents

  • Michel Robert. La Recherche dans les Micro et Nanotechnologies : Du Nanoobjet au Système. 2003, pp.P nd. ⟨lirmm-00269738⟩
  • Michel Robert. Propriété Intellectuelle : La Vérification Système en Question. 2003, pp.34-43. ⟨lirmm-00269735⟩
  • Michel Robert. Systèmes Microélectroniques sur Puce : Complexité et Interconnections. 2003. ⟨lirmm-00269737⟩
  • Daniel Auvergne, Nadine Azemard, Jordi Carrabina, Philippe Coll, Alain Guyot, et al.. Library free integrated circuit design for submicron technologies. 2002. ⟨lirmm-00259937⟩
  • Daniel Auvergne, Nadine Azemard, Jordi Carrabina, Philippe Coll, Alain Guyot, et al.. Library Free Integrated Circuit Design for Submicron Technologies. 2000. ⟨lirmm-00259939⟩

Preprints, Working Papers, ...1 document

  • Abdoulaye Gamatié, Alejandro Nocua, Joel Wanza Weloli, Gilles Sassatelli, Lionel Torres, et al.. Emerging NVM Technologies in Main Memory for Energy-Efficient HPC: an Empirical Study. 2019. ⟨lirmm-02135043⟩

Reports1 document

  • Daniel Auvergne, Nadine Azemard, Jordi Carrabina, Philippe Coll, Alain Guyot, et al.. Library Free Integrated Circuits for Submicron Technologies. [Research Report] Lirmm, University of Montpellier. 2002. ⟨lirmm-00268592⟩