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Michel Robert
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Documents
Identifiants chercheurs
michel-robert-
0000-0002-5075-2898
Présentation
Michel ROBERT (PhD:1987) is Professor at the University of Montpellier (France), where he’s teaching microelectronics in the engineering program. His present research interests at the Montpellier Laboratory of Informatics, Robotics, and Micro-electronics ([LIRMM](https://www.lirmm.fr/)) are design and modelisation of system on chip architectures. He is author or co-author of more than 300 publications in the field of CMOS integrated circuits design. He has supervised around forty doctoral thesis. He chaired the IFIP WG 10.5 (International Federation for Information Processing) from 2007 to 2011.
He served as director of the doctoral school, of the LIRMM research laboratory, then of the laboratory of excellence for digital solutions and modeling for the environment and the living, before becoming president of the University of Montpellier (2012-2015). He has held various national responsibilities in monitoring and evaluation in higher education and research. He was Director of the Institutional Evaluation Department of the High Council for the Evaluation of Research and Higher Education (Hcéres) from 2016 to 2021.
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Timing Slack Monitoring under Process and Environmental Variations: Application to a DSP Performance OptimizationMicroelectronics Journal, 2011, 42 (5), pp.718-732. ⟨10.1016/j.mejo.2011.02.005⟩
Article dans une revue
lirmm-00607877v1
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A Performance Driven Layout Synthesis Approach for Digital CMOS Cell ImplementationIntegration, the VLSI Journal, 1993
Article dans une revue
lirmm-00239254v1
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Post-Layout Timing Simulation of CMOS CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993, 12 (8), pp.1170-1177. ⟨10.1109/43.238609⟩
Article dans une revue
lirmm-00239206v1
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Input Waveform Slope Effects in CMOS DelaysIEEE Journal of Solid-State Circuits, 1990, 25 (6), pp.1588-1590. ⟨10.1109/4.62196⟩
Article dans une revue
lirmm-00239201v1
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Evaluation Dynamique et Optimisation des Structures CMOS et VLSIRevue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, 1989, 8 (6), pp.593-607
Article dans une revue
lirmm-00239199v1
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On-Chip Timing Slack MonitoringVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2009, Florianopolis, Brazil. pp.89-94, ⟨10.1109/VLSISOC.2009.6041336⟩
Communication dans un congrès
lirmm-00429350v1
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An Innovative Timing Slack Monitor for Variation Tolerant CircuitsICICDT: International Conference on IC Design & Technology, May 2009, Austin, TX, United States. pp.215-218, ⟨10.1109/ICICDT.2009.5166299⟩
Communication dans un congrès
lirmm-00371174v1
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Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of VariabilitiesPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.266-275, ⟨10.1007/978-3-642-11802-9_31⟩
Communication dans un congrès
lirmm-00433462v1
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Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variationsFTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Suisse
Communication dans un congrès
lirmm-00404810v1
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Setup and Hold Timing Violations Induced by Process Variations, in a Digital MultiplierISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩
Communication dans un congrès
lirmm-00280809v1
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A Comparative Study of Variability Impact on Static Flip-Flop Timing CharacteristicsICICDT: International Conference on IC Design and Technology, Jun 2008, Grenoble, France. pp.167-170
Communication dans un congrès
lirmm-00305246v1
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Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numériqueFTFC: Faible Tension - Faible Consommation, May 2008, Louvain-La-Neuve, Belgique
Communication dans un congrès
lirmm-00283731v1
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Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétiqueJNRDM 2008 - 11e Journées Nationales du Réseau Doctoral de Microélectronique, May 2008, Bordeaux, France
Communication dans un congrès
lirmm-00281175v2
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Design Optimization with Automated Cell GenerationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.722-731, ⟨10.1007/978-3-540-30205-6_74⟩
Communication dans un congrès
lirmm-00108894v1
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Automatic Layout Synthesis Based Performance OptimizationIWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85
Communication dans un congrès
lirmm-00108654v1
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A Physical Synthesis Design Flow based on Virtual ComponentsDCIS: Design of Circuits and Integrated Systems, Nov 2000, Montpellier, France. pp.740-745
Communication dans un congrès
lirmm-00239439v1
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Evaluation of Speed up Strategy from Gate Performance ModellingIFIP Workshop on Logic and Architecture Synthesis, Dec 1993, Grenoble, France, pp.193-208
Communication dans un congrès
lirmm-00241358v1
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Flexible Macrocell layout Generator4th ACM/SIGDA Physical Design Workshop, Layout Synthesis for the New Generation of VLSI ASIC Technologies, Apr 1993, UCLA Conference Center, CA, USA, pp.105-116
Communication dans un congrès
lirmm-00241344v1
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Tool Box for Performance Driven Macrocell layout SynthesisEurochip Workshop on VLSI Design Training, Sep 1993, Toledo, Spain. pp.56-61
Communication dans un congrès
lirmm-00241348v1
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Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor SisingPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 1992, Paris, France. pp.102-108
Communication dans un congrès
lirmm-00241327v1
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An Accurate and Efficient Delay Time Modelling and its Application to CMOS Data Path Evaluation and Transistor SizingWorld Congress on Computation and Applied Mathematics, IMACS: International Association for Mathematics and Computers in Simulation, Jul 1991, Dublin, Ireland. pp.1661-1663
Communication dans un congrès
lirmm-00239387v1
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Formal Sizing Rules of CMOS CircuitsEDAC 1991 - European Conference on Design Automation, Feb 1991, Amsterdam, Netherlands. pp.96-100, ⟨10.1109/EDAC.1991.206368⟩
Communication dans un congrès
lirmm-00239374v1
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Evaluation of VLSI Layout Implementation for EfficiencyEURO-ASIC 1991 - European Conference on Design Automation with European Event in ASIC Design, May 1991, Paris, France. pp.362-365, ⟨10.1109/EUASIC.1991.212836⟩
Communication dans un congrès
lirmm-00239384v1
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Towards Autonomous Scalable Integrated SystemsDesign Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. ⟨10.1007/978-94-007-1125-9_4⟩
Chapitre d'ouvrage
lirmm-01399454v1
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Library free integrated circuit design for submicron technologies2002
Autre publication scientifique
lirmm-00259937v1
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Library Free Integrated Circuit Design for Submicron Technologies2000
Autre publication scientifique
lirmm-00259939v1
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Library Free Integrated Circuits for Submicron Technologies[Research Report] Lirmm, University of Montpellier. 2002
Rapport
lirmm-00268592v1
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