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Luigi Dilillo
160
Documents
Identifiants chercheurs
luigi-dilillo- IdRef : 18891885X
-
0000-0002-1295-2688
Présentation
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A Model-Based Framework to Assess the Reliability of Safety-Critical ApplicationsDDECS 2021 - 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2021, Vienna (virtual), Austria. pp.41-44, ⟨10.1109/DDECS52668.2021.9417059⟩
Communication dans un congrès
hal-03266848v1
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Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural NetworksLATS 2021 - IEEE 22nd Latin American Test Symposium, Oct 2021, Punta del Este, Uruguay. pp.1-5, ⟨10.1109/LATS53581.2021.9651807⟩
Communication dans un congrès
lirmm-03435567v1
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Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing SystemsDFT 2020 - 33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2020, Frascati, Italy. pp.1-6, ⟨10.1109/DFT50435.2020.9250865⟩
Communication dans un congrès
lirmm-03025736v1
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Effects of Thermal Neutron Irradiation on a Self-Refresh DRAMDTIS 2020 - 15th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Apr 2020, Marrakech, Morocco. pp.1-6, ⟨10.1109/DTIS48698.2020.9080918⟩
Communication dans un congrès
lirmm-03025721v1
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An effective BIST architecture for power-gating mechanisms in low-power SRAMsISQED 2016 - 17th International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. pp.185-191, ⟨10.1109/ISQED.2016.7479198⟩
Communication dans un congrès
lirmm-01457424v1
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Scan-chain intra-cell defects gradingDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. ⟨10.1109/DTIS.2015.7127349⟩
Communication dans un congrès
lirmm-01272696v1
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Design-for-Diagnosis Architecture for Power SwitchesDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. pp.43-48, ⟨10.1109/DDECS.2015.18⟩
Communication dans un congrès
lirmm-01272684v1
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An effective hybrid fault-tolerant architecture for pipelined coresETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. ⟨10.1109/ETS.2015.7138733⟩
Communication dans un congrès
lirmm-01272730v1
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An effective ATPG flow for Gate Delay FaultsDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. ⟨10.1109/DTIS.2015.7127350⟩
Communication dans un congrès
lirmm-01272719v1
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Exploring the impact of functional test programs re-used for power-aware testingDATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.1277-1280, ⟨10.7873/DATE.2015.1031⟩
Communication dans un congrès
lirmm-01272937v1
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An ATPG Flow to Generate Crosstalk-Aware Path Delay PatternISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.515-520, ⟨10.1109/ISVLSI.2015.99⟩
Communication dans un congrès
lirmm-01272933v1
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A Comprehensive Evaluation of Functional Programs for Power-Aware TestNATW: North Atlantic Test Workshop, May 2014, Johnson City, NY, United States. pp.69-72, ⟨10.1109/NATW.2014.23⟩
Communication dans un congrès
lirmm-01248597v1
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TSV aware timing analysis and diagnosis in paths with multiple TSVsVTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. ⟨10.1109/VTS.2014.6818772⟩
Communication dans un congrès
lirmm-01248594v1
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Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal considerationASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2014, Singapore, Singapore. pp.544-549, ⟨10.1109/ASPDAC.2014.6742948⟩
Communication dans un congrès
lirmm-01248596v1
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A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply NoiseISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.226-231, ⟨10.1109/ISVLSI.2014.42⟩
Communication dans un congrès
lirmm-01248592v1
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Test and diagnosis of power switchesDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.213-218, ⟨10.1109/DDECS.2014.6868792⟩
Communication dans un congrès
lirmm-01248590v1
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On the Generation of Diagnostic Test Set for Intra-cell DefectsATS: Asian Test Symposium, Nov 2014, Hangzhou, China. pp.312-317, ⟨10.1109/ATS.2014.57⟩
Communication dans un congrès
lirmm-01272539v1
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Protecting combinational logic in pipelined microprocessor cores against transient and permanent faultsDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.223-225, ⟨10.1109/DDECS.2014.6868794⟩
Communication dans un congrès
lirmm-01248598v1
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Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounceDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.207-212, ⟨10.1109/DDECS.2014.6868791⟩
Communication dans un congrès
lirmm-01248599v1
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Real-Time Testing of 90nm COTS SRAMs at Concordia Station in AntarcticaNSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France
Communication dans un congrès
lirmm-01237709v1
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iBoX — Jitter based Power Supply Noise sensorETS: European Test Symposium, May 2014, Paderborn, United States. ⟨10.1109/ETS.2014.6847830⟩
Communication dans un congrès
lirmm-01248601v1
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Efficient Dynamic Test Methods for COTS SRAMs Under Heavy Ion IrradiationNSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France
Communication dans un congrès
lirmm-01237660v1
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An intra-cell defect grading toolDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.298-301, ⟨10.1109/DDECS.2014.6868814⟩
Communication dans un congrès
lirmm-01248591v1
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Timing-aware ATPG for critical paths with multiple TSVsDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.116-121, ⟨10.1109/DDECS.2014.6868774⟩
Communication dans un congrès
lirmm-01248600v1
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SRAM Soft Error Rate Evaluation Under Atmospheric Neutron Radiation and PVT variationsIOLTS: International On-Line Testing Symposium, Jul 2013, Chania, Crete, Greece. pp.145-150, ⟨10.1109/IOLTS.2013.6604066⟩
Communication dans un congrès
lirmm-00818955v1
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Multiple-Cell-Upsets on a commercial 90nm SRAM in Dynamic ModeRADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. pp.1-4, ⟨10.1109/RADECS.2013.6937429⟩
Communication dans un congrès
lirmm-00839062v1
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Effect-Cause Intra-Cell Diagnosis at Transistor LevelISQED 2013 - 14th International Symposium on Quality Electronic Design, Mar 2013, Santa Clara, CA, United States. pp.460-467, ⟨10.1109/ISQED.2013.6523652⟩
Communication dans un congrès
lirmm-00817224v1
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Fast and Accurate Electro-Thermal Analysis of Three-Dimensional Power Delivery NetworksEuroSimE: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Apr 2013, Wroclaw, Poland. pp.1-4, ⟨10.1109/EuroSimE.2013.6529956⟩
Communication dans un congrès
lirmm-00839043v1
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Temperature Impact on the Neutron SER of a Commercial 90nm SRAMNSREC: Nuclear and Space Radiation Effects Conference, Jul 2013, San Francisco, Ca, United States. pp.1-4
Communication dans un congrès
lirmm-00805291v1
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On the Reuse of Read and Write Assist Circuits to Improve Test Efficiency in Low-Power SRAMsITC: International Test conference, Sep 2013, Anaheim, CA, United States. pp.1-10, ⟨10.1109/TEST.2013.6651927⟩
Communication dans un congrès
lirmm-00818977v1
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A Built-in Scheme for Testing and Repairing Voltage Regulators of Low-Power SRAMsVTS: VLSI Test Symposium, Apr 2013, Berkeley, CA, United States. pp.1-6, ⟨10.1109/VTS.2013.6548894⟩
Communication dans un congrès
lirmm-00805366v1
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Computing Detection Probability of Delay Defects in Signal Line TSVsETS: European Test Symposium, May 2013, Avignon, France. ⟨10.1109/ETS.2013.6569349⟩
Communication dans un congrès
lirmm-00839044v1
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Improving Defect Localization Accuracy by means of Effect-Cause Intra-Cell Diagnosis at Transistor LevelSDD: Silicon Debug and Diagnosis, Sep 2013, Anaheim, CA, United States
Communication dans un congrès
lirmm-00806872v1
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Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failuresDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Mar 2013, Abu Dhabi, United Arab Emirates. pp.39-44, ⟨10.1109/DTIS.2013.6527775⟩
Communication dans un congrès
lirmm-01248603v1
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SEU Monitoring in Mixed-Field Radiation Environments of Particle AcceleratorsRADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. pp.1-4, ⟨10.1109/RADECS.2013.6937419⟩
Communication dans un congrès
lirmm-00839085v1
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Worst-Case Power Supply Noise and Temperature Distribution Analysis for 3D PDNs with Multiple Clock DomainsNEWCAS: New Circuits and Systems, Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573628⟩
Communication dans un congrès
lirmm-00839042v1
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Performance Characterization of TAS-MRAM Architectures in Presence of Capacitive DefectsVALID: Advances in System Testing and Validation Lifecycle, Oct 2013, Venice, Italy. pp.39-44
Communication dans un congrès
lirmm-01433308v1
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Characterization of an SRAM Based Particle Detector For Mixed-Field Radiation EnvironmentsIWASI: International Workshop on Advances in Sensors and Interfaces, Jun 2013, Bari, Italy. pp.75-80, ⟨10.1109/IWASI.2013.6576070⟩
Communication dans un congrès
lirmm-00839046v1
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Analyzing resistive-open defects in SRAM core-cell under the effect of process variabilityETS: European Test Symposium, May 2013, Avignon, France. ⟨10.1109/ETS.2013.6569373⟩
Communication dans un congrès
lirmm-01921630v1
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Mitigate TSV Electromigration for 3D ICs - From the Architecture PerspectiveInternational Symposium on VLSI, Natale, Brazil. pp.6
Communication dans un congrès
lirmm-00839052v1
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Evaluating An SEU Monitor For Mixed-Field Radiation EnvironmentsiWoRID: International Workshop on Radiation Imaging Detectors, SOLEIL Synchrotron, Jun 2013, Paris, France
Communication dans un congrès
lirmm-01238433v1
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Test Solution for Data Retention Faults in Low-Power SRAMsDATE 2013 - 16th Design, Automation and Test in Europe Conference, Mar 2013, Grenoble, France. pp.442-447, ⟨10.7873/DATE.2013.099⟩
Communication dans un congrès
lirmm-00805140v1
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On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cellDFT: Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2013, New York, United States. pp.143-148, ⟨10.1109/DFT.2013.6653597⟩
Communication dans un congrès
lirmm-01238413v1
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A novel method to mitigate TSV electromigration for 3D ICsISVLSI: IEEE Computer Society Annual Symposium on VLSI, Aug 2013, Natal, Brazil. pp.121-126, ⟨10.1109/ISVLSI.2013.6654633⟩
Communication dans un congrès
lirmm-01248617v1
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Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line CouplingGDR SOC-SIP'11 : Colloque GDR SoC-SiP, Lyon, France
Communication dans un congrès
lirmm-00679522v1
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Electro-Thermal Analysis of 3D Power Delivery NetworksDAC: Design Automation Conference, 2012, San Francisco, United States
Communication dans un congrès
lirmm-00806836v1
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Test and Reliability of Magnetic Random Access MemoriesGDR SOC-SIP'11: Colloque GDR SoC-SiP, Lyon, France
Communication dans un congrès
lirmm-00679516v1
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Resistive-Open Defect Analysis for Through-Silicon-ViasDCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France
Communication dans un congrès
lirmm-00806803v1
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Defect Analysis in Power Mode Control Logic of Low-Power SRAMsETS: European Test Symposium, May 2012, Annecy, France. ⟨10.1109/ETS.2012.6233033⟩
Communication dans un congrès
lirmm-00805374v1
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Dynamic Mode Testing of SRAMS under Neutron RadiationSixième colloque du GDR SOC-SIP du CNRS, Jun 2012, Paris, France
Communication dans un congrès
lirmm-00807053v1
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Power Supply Noise Sensor Based on Timing Uncertainty MeasurementsATS: Asian Test Symposium, Nov 2012, Niigata, Japan. pp.161-166, ⟨10.1109/ATS.2012.46⟩
Communication dans un congrès
lirmm-00806890v1
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Peak Power Estimation: A Case Study on CPU CoresIEEE Asian Test Symposium, Nov 2012, Niigata, Japan. pp.167-172, ⟨10.1109/ATS.2012.58⟩
Communication dans un congrès
lirmm-00805389v1
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Low-power SRAMs Power Mode Control Logic: Failure Analysis and Test SolutionsITC'2012: International Test Conference, Nov 2012, Anaheim, CA, United States. pp.1-10, ⟨10.1109/TEST.2012.6401578⟩
Communication dans un congrès
lirmm-00805143v1
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SRAM testing under Neutron Radiation for the evaluation of different algorithms stress15ème Journées Nationales du Réseau Doctoral en Microélectronique, Jun 2012, Marseille, France
Communication dans un congrès
lirmm-00807054v1
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Complete Framework for the Estimation of the SRAM Core-Cell Resilience to RadiationRADECS: Radiation and its Effects on Components and Systems, Sep 2012, Biarritz, France
Communication dans un congrès
hal-01935785v1
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Robustness Improvement of Digital Circuits A New Hybrid Fault Tolerant ArchitectureJNRDM'11: Journées Nationales du Réseau Doctoral de Microélectronique, Paris, France
Communication dans un congrès
lirmm-00679509v1
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Impacts of Resistive-Open Defects in the Word-Line Selection of TAS-MRAMsColloque GDR SoC-SiP, 2012, Paris, France
Communication dans un congrès
lirmm-00806842v1
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Through-Silicon-Via Resistive-Open Defect AnalysisETS: European Test Symposium, May 2012, Annecy, France. ⟨10.1109/ETS.2012.6233037⟩
Communication dans un congrès
lirmm-00806848v1
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Why and How Controlling Power Consumption During Test: A SurveyATS: Asian Test Symposium, Nov 2012, Niigata, Japan. pp. 221-226, ⟨10.1109/ATS.2012.30⟩
Communication dans un congrès
lirmm-00818984v1
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Adaptive Voltage Scaling via Effective On-Chip Timing Uncertainty MeasurementsColloque GDR SoC-SiP, 2012, Paris, France
Communication dans un congrès
lirmm-00806859v1
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Evaluation of Test Algorithms Stress Effect on SRAMs under Neutron RadiationIOLTS: International On-Line Testing Symposium, Jun 2012, Sitges, Spain. pp.212-222, ⟨10.1109/IOLTS.2012.6313853⟩
Communication dans un congrès
lirmm-00805373v1
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A Novel Framework for Evaluating the SRAM Core-Cell Sensitivity to NeutronsRADECS: European Conference on Radiation and Its Effects on Components and Systems, Sep 2012, Biarritz, France. pp.1-4
Communication dans un congrès
lirmm-00805163v1
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Resistive-Open Defects Affecting Bit-Line Selection in TAS-MRAM ArchitecturesJNRDM: Journées Nationales du Réseau Doctoral en Microélectronique, 2012, Paris, France
Communication dans un congrès
lirmm-00806827v1
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Advanced Test Methods for SRAMsVTS: VLSI Test Symposium, Apr 2012, Hyatt Maui, HI, United States. pp.300-301, ⟨10.1109/VTS.2012.6231070⟩
Communication dans un congrès
lirmm-00805049v1
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A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant ArchitecturesVTS: VLSI Test Symposium, Apr 2012, Hawaii, United States. pp.50-55, ⟨10.1109/VTS.2012.6231079⟩
Communication dans un congrès
lirmm-00806778v1
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Impact of Resistive-Bridge Defects in TAS-MRAM ArchitecturesATS: Asian Test Symposium, Nov 2012, Niigata, Japan. pp.125-130, ⟨10.1109/ATS.2012.37⟩
Communication dans un congrès
lirmm-00806809v1
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Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM ArchitecturesDATE 2012 - 15th Design, Automation and Test in Europe Conference and Exhibition, Mar 2012, Dresden, Germany. pp.532-537, ⟨10.1109/DATE.2012.6176526⟩
Communication dans un congrès
lirmm-00689024v1
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A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital CircuitsGDR SOC-SIP'11 : Colloque GDR SoC-SiP, Lyon, France
Communication dans un congrès
lirmm-00679513v1
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Defect Localization Through an Effect-Cause based Intra-Cell DiagnosisColloque GDR SoC-SiP, 2012, Paris, France
Communication dans un congrès
lirmm-00806841v1
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Fault Localization Improvement through an Intra-Cell Diagnosis ApproachISTFA 2012 - 38th International Symposium for Testing and Failure Analysis, Nov 2012, Phoenix, AZ, United States. pp.509-519
Communication dans un congrès
lirmm-00806863v1
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Dynamic Mode Test of a Commercial 4Mb Toggle MRAM under Neutron RadiationRADECS: European Conference on Radiation and Its Effects on Components and Systems, Sep 2012, Biarritz, France. pp.1-4
Communication dans un congrès
lirmm-00805165v1
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Radiation Induced Effects on Electronic Systems and ICsSETS: South European Test Seminar, Mar 2012, Sauze d'Oulx, Italy
Communication dans un congrès
lirmm-00807055v1
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Tolérance aux fautes et rendement de fabricationGDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France
Communication dans un congrès
lirmm-00553995v1
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X-Identification of Transition Delay Fault Tests for Launch-off Shift SchemeWRTLT'10: 11th IEEE Workshop On RTL and High Level Testing, Shanghai, China. pp.N/A
Communication dans un congrès
lirmm-00566869v1
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Impact of Resistive-Bridging Defects in SRAM Core-CellDELTA'10: International Symposium on Electronic Design, Test & Applications, Ho Chi Minh, Vietnam. pp.265-270
Communication dans un congrès
lirmm-00553592v1
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Mapping Test Power to Functional Power through Smart X-Filling for LOS SchemeLPonTR'11: IEEE International Workshop on the Impact of Low Power on Test and Reliability, Trondheim, Norway
Communication dans un congrès
lirmm-00651905v1
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Error Resilient Infrastructure for Data Transfer in a Distributed Neutron DetectorDFT 2011 - International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2011, Vancouver, Canada. pp.294-301, ⟨10.1109/DFT.2011.41⟩
Communication dans un congrès
lirmm-00651226v1
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Test Relaxation and X-filling to Reduce Peak Power During At-Speed LOS TestingGDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France
Communication dans un congrès
lirmm-00553989v1
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Detecting NBTI Induced Failures in SRAM Core-CellsVTS'10: VLSI Test Symposium, Santa Cruz, CA, United States. pp.75-80
Communication dans un congrès
lirmm-00553612v1
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Failure Analysis and Test Solutions for Low-Power SRAMsATS: Asian Test Symposium, Nov 2011, New Delhi, India. pp.459-460, ⟨10.1109/ATS.2011.97⟩
Communication dans un congrès
lirmm-00805123v1
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Robust Structure for Data Collection and Transfer in a Distributed SRAM Based Neutron Test BenchWorkshop on Dependability Issues in Deep-Submicron Technologies, Trondheim, Norway
Communication dans un congrès
lirmm-00651796v1
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Simultaneous Power and Thermal Integrity Analysis for 3D Integrated SystemsLPonTR'11: IEEE International Workshop on the Impact of Low Power on Test and Reliability, Trondheim, Norway
Communication dans un congrès
lirmm-00651802v1
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Analysis of Resistive-Open Defects in TAS-MRAM ArrayITC: International Test Conference, Sep 2011, Anaheim, CA, United States
Communication dans un congrès
lirmm-00679524v1
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Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line CouplingDDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Netherlands. pp.353-358
Communication dans un congrès
lirmm-00592182v1
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Power-Aware Test Pattern Generation for At-Speed LOS TestingATS: Asian Test Symposium, Nov 2011, New Delhi, India. pp.506-510
Communication dans un congrès
lirmm-00651917v1
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Power Supply Noise and Ground Bounce Aware Pattern Generation for Delay TestingNEWCAS: International New Circuits and Systems Conference, Jun 2011, Bordeaux, France. pp.73-76, ⟨10.1109/NEWCAS.2011.5981222⟩
Communication dans un congrès
lirmm-00647815v1
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A Study of Path Delay Variations in the Presence of Uncorrelated Power and Ground Supply NoiseDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2011, Cottbus, Germany. pp.189-194, ⟨10.1109/DDECS.2011.5783078⟩
Communication dans un congrès
lirmm-00592000v1
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On Using Address Scrambling to Implement Defect Tolerance in SRAMsITC'2011: International Test Conference, Sep 2011, Anaheim, CA, United States. pp.N/A
Communication dans un congrès
lirmm-00647773v1
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A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital CircuitsATS 2011 - 20th IEEE Asian Test Symposium, Nov 2011, New Delhi, India. pp.136-141, ⟨10.1109/ATS.2011.89⟩
Communication dans un congrès
lirmm-00651238v1
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On Using Address Scrambling for Defect Tolerance in SRAMsInternational test Conference, Sep 2011, Anaheim, CA, United States. pp.1-8, ⟨10.1109/TEST.2011.6139149⟩
Communication dans un congrès
lirmm-00805334v1
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Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-FillingATS: Asian Test Symposium, 2011, New Delhi, India. pp.21-23
Communication dans un congrès
lirmm-00651247v1
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A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay TestingETS 2011 - 16th IEEE European Test Symposium, May 2011, Trondheim, Norway. pp.153-158, ⟨10.1109/ETS.2011.21⟩
Communication dans un congrès
lirmm-00647822v1
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Analyse et modélisation des défauts résistifs affectant les mémoires FlashGDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France
Communication dans un congrès
lirmm-00553947v1
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Robust Data Collection and Transfer Framework for a Distributed SRAM Based Neutron SensorIEEE International Workshop on Advances in Sensors and Interfaces, Jun 2011, Savelletri di Fasano, Italy. pp.176-180, ⟨10.1109/IWASI.2011.6004712⟩
Communication dans un congrès
lirmm-00805394v1
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Analysis and Fault Modeling of Actual Resistive Defects in Flash MemoriesJNRDM'10 : Journées Nationales du Réseau Doctoral de Microélectronique, Montpellier, France
Communication dans un congrès
lirmm-00553935v1
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A DfT Solution for Oxide Thickness Varitions in ATMEL eFlash TechnologyDTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2011, Athènes, Greece
Communication dans un congrès
lirmm-00647750v1
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Variability Analysis of an SRAM Test ChipETS: European Test Symposium, May 2011, Trondheim, Norway
Communication dans un congrès
lirmm-00651791v1
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On using a SPICE-like TSTAC™ eFlash model for design and testDDECS: Design and Diagnostics of Electronic Circuits ans Systems, Apr 2011, Cottbus, Germany. pp.359-370, ⟨10.1109/DDECS.2011.5783111⟩
Communication dans un congrès
lirmm-00592203v1
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Power Reduction Through X-filling of Transition Fault Test Vectors for LOS TestingDTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2011, Athènes, Greece. ⟨10.1109/DTIS.2011.5941434⟩
Communication dans un congrès
lirmm-00647760v1
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Analysis of Resistive-Bridging Defects in SRAM Core-Cells: a Comparative Study from 90nm down to 40nm Technology NodesETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.132-137
Communication dans un congrès
lirmm-00493236v1
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A Two-Layer SPICE Model of the ATMEL TSTAC eFlash Memory Technology for Defect Injection and Faulty Behavior PredictionETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.81-86
Communication dans un congrès
lirmm-00493204v1
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Power Reduction Through X-filling of Transition Fault Test Vectors for LOS TestingLPonTR:
Impact of Low-Power design on Test and Reliability, May 2010, Prague, Czech Republic
Communication dans un congrès
lirmm-00553930v1
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A Comprehensive System-on-Chip Logic DiagnosisATS: Asian Test Symposium, 2010, Shanghai, China. pp.237-242
Communication dans un congrès
lirmm-00545131v1
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A Statistical Simulation Method for Reliability Analysis of SRAM Core-CellsDAC: Design Automation Conference, Jun 2010, Anaheim, United States. pp.853-856
Communication dans un congrès
lirmm-00553619v1
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Setting Test Conditions for Detecting Faults Induced by Random Dopant Fluctuation in SRAM Core-CellsVARI: Workshop on CMOS Variability, 2010, Montpellier, France
Communication dans un congrès
lirmm-00553626v1
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Setting Test Conditions for Improving SRAM ReliabilityETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.257-262
Communication dans un congrès
lirmm-00492741v1
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Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Testing SchemesDDECS'10: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2010, Vienna, Austria. pp.376-381
Communication dans un congrès
lirmm-00475734v1
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A Memory Fault Simulator for Radiation-Induced Effects in SRAMsATS: Asian Test Symposium, 2010, Shanghai, China. pp.100-105
Communication dans un congrès
lirmm-00545102v1
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A Fault-Simulation-Based Approach for Logic DiagnosisDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2009, Cairo, Egypt. pp.216-221
Communication dans un congrès
lirmm-00371377v1
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Using TMR Architectures for SoC Yield ImprovementVALID'09: The First International Conference on Advances in System Testing and Validation Lifecycle, 2009, Porto, Portugal. pp.155-160
Communication dans un congrès
lirmm-00406967v1
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Delay Fault Diagnosis in Sequential CircuitsATS: Asian Test Symposium, Nov 2009, Taichung, Taiwan. pp.355-360
Communication dans un congrès
lirmm-00406968v1
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Comprehensive Bridging Fault Diagnosis based on the SLAT ParadigmDDECS'09: 12th IEEE Symposium on Design and Diagnostics of Electronic Systems, pp.264-269
Communication dans un congrès
lirmm-00371198v1
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Trade-off Between Power Dissipation and Delay Fault Coverage For LOS and LOC Testing SchemesImpact of Low-Power Design on Test and Reliability, Spain
Communication dans un congrès
lirmm-00435005v1
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A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMsITC'2008: International Test Conference, Oct 2008, Santa Clara, CA, United States. pp.1-10, ⟨10.1109/TEST.2008.4700555⟩
Communication dans un congrès
lirmm-00341798v1
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A Signature-based Approach for Diagnosis of Dynamic Faults in SRAMsDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Mar 2008, Tunis, Tunisia. pp.001-006, ⟨10.1109/DTIS.2008.4540243⟩
Communication dans un congrès
lirmm-00324143v1
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A History-Based Technique for Faults Diagnosis in SRAMsColloque GDR SoC-SiP, France
Communication dans un congrès
lirmm-00341821v1
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Fault-Effect Propagation Based Intra-cell Scan Chain DiagnosisColloque GDR SoC-SiP, Jun 2013, Lyon, France. 2013
Poster de conférence
lirmm-00839113v1
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Performance Evaluation of Capacitive defects on TAS-MRAMsColloque GDR SoC-SiP, 2013, Lyon, France. 2013
Poster de conférence
lirmm-00839093v1
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Investigating Multiple-Cell-Upsets on a 90mn SRAMColloque GDR SoC-SiP, 2013, Lyon, France. 2013
Poster de conférence
lirmm-00839108v1
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Coupling-Based Resistive-Open Defects in TAS-MRAM ArchitecturesETS: European Test Symposium, May 2012, Annecy, France. Test Symposium (ETS), 2012 17th IEEE European, 2012, ⟨10.1109/ETS.2012.6233034⟩
Poster de conférence
lirmm-00806793v1
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Resistive Open Defect Analysis for Through-Silicon-ViasETS: European Test Symposium, May 2012, Annecy, France. 17th IEEE European Test Symposium, pp.183, 2012
Poster de conférence
lirmm-00806795v1
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Parity Prediction Synthesis for Nano-Electronic Gate DesignsITC'2010: International Test Conference, Nov 2010, Austin, Texas, United States. pp.N/A, 2010
Poster de conférence
lirmm-00537938v1
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Is Test Power Reduction Through X-Filling Good Enough?ITC'2010: International Test Conference, Nov 2010, Austin, Texas, United States. 2010
Poster de conférence
lirmm-00537926v1
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Analysis of Resistive-Bridging Defects in SRAM Core-Cell: Impact within the Core-Cell and in the Memory ArrayETS: European Test Symposium, May 2009, Sevilla, Spain. 14th IEEE European Test Symposium, 2009
Poster de conférence
lirmm-00433796v1
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SoC Yield Improvement for Future Nanoscale TechnologiesETS 2009 - 14th IEEE European Test Symposium | PhD Forum, May 2009, Sevilla, Spain. 2009
Poster de conférence
lirmm-00433798v1
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A Logic Diagnosis Approach for Sequential CircuitsPoster de conférence lirmm-00433792v1 |
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Test des Mémoires FLASH NANDColloque GDR SoC-SiP, France. 2009
Poster de conférence
lirmm-00433770v1
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SRAM Core-cell Quality MetricsGDR SOC SIP, France. 2009
Poster de conférence
lirmm-00434962v1
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Trade-off Between Power Dissipation and Delay Fault Coverage for LOS and LOC Testing SchemesGDR SOC SIP, France. 2009
Poster de conférence
lirmm-00434959v1
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NAND Flash Testing: A Preliminary Study on Actual DefectsITC: International Test Conference, Nov 2009, Austin, TX, United States. 2009, ⟨10.1109/TEST.2009.5355898⟩
Poster de conférence
lirmm-00433765v1
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Advanced Test Methods for SRAMs - Effective Solutions for Dynamic Fault Detection in Nanoscaled TechnologiesSpringer, 171 p., 2009, 978-1-4419-0937-4
Ouvrages
lirmm-00371359v1
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Electromigration Alleviation Techniques for 3D Integrated CircuitsChao Wang. High Performance Computing for Big Data: Methodologies and Applications, CRC Press, pp.37-58, 2017, 9781498783996
Chapitre d'ouvrage
lirmm-01800220v1
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Rapport Technique de fin d'année, Contrat TOETS CT 302, Programme CEE CATRENE2011
Autre publication scientifique
lirmm-00679022v1
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Rapport Technique intermédiaire, Contrat TOETS CT 302, Programme CEE CATRENE2011
Autre publication scientifique
lirmm-00679018v1
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TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année2010
Autre publication scientifique
lirmm-00461745v1
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Contrat TOETS CT 302 - Programme CEE CATRENE (Rapport Intermédiaire)2010
Autre publication scientifique
lirmm-00504873v1
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Rapport Technique de fin de Contrat NanoTEST 2A702, Programme CEE MEDEA+2009
Autre publication scientifique
lirmm-00406974v1
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