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Laurent Fesquet
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Documents
Présentation
Maître de conférences
[Laboratoire TIMA](tima.imag.fr/ "Laboratoire TIMA")
Equipe [CDSI](http://tima.imag.fr/tima/en/cdsi/cdsioverview.html "équipe CDSI") (Design of Integrated devices, Circuits and Systems)
Associate Professor
[Laboratoire TIMA](tima.imag.fr/ "Laboratoire TIMA")
Team: [CDSI](http://tima.imag.fr/tima/en/cdsi/cdsioverview.html "équipe CDSI") (Design of Integrated devices, Circuits and Systems)
Publications
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A Generic Clock Controller for Low Power Systems: Experimentation on an AXI BusIFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'15) , Oct 2015, Daejeon, North Korea
Communication dans un congrès
hal-01393420v1
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