CV Accueil - Archive ouverte HAL

	An Area and Power Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits Jérémy Belot , Abdelkarim Cherkaoui , Raphael Laurent , Laurent Fesquet IEEE Design & Test, 2021, 38 (6), pp.69-77. ⟨10.1109/mdat.2021.3050694⟩ Article dans une revue hal-03662193v1
	An accurate time-to-digital converter based on a self-timed ring oscillator for on-the-fly time measurement Assia El Hadbi , A. Cherkaoui , Jean Simatic , Oussama Elissati , Laurent Fesquet Analog Integrated Circuits and Signal Processing, 2018, 97 (3), pp.471-481. ⟨10.1007/s10470-018-1223-4⟩ Article dans une revue hal-01827393v1
	Multi-phase low-noise digital ring oscillators with sub-gate-delay resolution Oussama Elissati , Abdelkarim Cherkaoui , Assia El Hadbi , Sébastien Rieubon , Laurent Fesquet AEÜ - International Journal of Electronics and Communications / Archiv für Elektronik und Übertragungstechnik, 2018, 84, pp.74 - 83. ⟨10.1016/j.aeue.2017.11.022⟩ Article dans une revue hal-01726767v1

	An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study Jérémy Belot , Abdelkarim Cherkaoui , Raphael Laurent , Laurent Fesquet 28th IEEE International Conference on Electronics Circuits and Systems (ICECS 2021), Nov 2021, Dubai, United Arab Emirates. ⟨10.1109/ICECS53924.2021.9665535⟩ Communication dans un congrès hal-03662362v1
	A Self-Timed Ring based PUF Grégoire Gimenez , A. Cherkaoui , Laurent Fesquet 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2020), May 2020, Snowbird, United States. pp.69-77 Communication dans un congrès hal-02952904v1
	Asynchronous circuits for new computation paradigms Laurent Fesquet , Raphael Frisch , M. Faix , Jérémy Belot , Jean Simatic IEEE International Nanodevices & Computing Conference (INC 2019), Apr 2019, Grenoble, France Communication dans un congrès hal-02165199v1
	Static Timing Analysis of Asynchronous Bundled-data Circuits Grégoire Gimenez , Abdelkarim Cherkaoui , Guillaume Cognard , Laurent Fesquet 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2018), May 2018, Vienna, Austria Communication dans un congrès hal-01726936v1
	Benchmarking of shared and distributed memory strategy for stochastic Bayesian machines Raphael Frisch , T. Hirtzlin , M. Faix , A. Cherkaoui , D. Querlioz IEEE International Conference on Rebooting Computing (ICRC 2018), Nov 2018, Washington DC, United States Communication dans un congrès hal-02170183v1
	Subthreshold Logic for Low-Area and Energy Efficient True Random Number Abdelkarim Cherkaoui , Mathieu Coustans , Laurent Fesquet , Christian Terrier , Stephanie Salgado IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips, Apr 2018, Yokohama, Japan Communication dans un congrès hal-01827411v1
	Low Phase-Noise CMOS Quadrature Oscillator Based on a (Nx4)-stage Self-Timed Ring Oussama Elissati , Assia El Hadbi , Abdelkarim Cherkaoui , Sébastien Rieubon , Laurent Fesquet Conference on Design of Circuits and Integrated Systems (DCIS 2018), Nov 2018, Lyon, France Communication dans un congrès hal-01971021v1
	Event-based processing: a new paradigm for low-power Laurent Fesquet , Sophie Germain , Jean Simatic , Abdelkarim Cherkaoui , Tugdual Le Pelleter 19th IEEE Mediterranean Electrotechnical Conference (IEEE Melecon’18), May 2018, Marrakesh, Morocco Communication dans un congrès hal-01726778v1
	A practical framework for specification, verification and design of self-timed pipelines Jean Simatic , Abdelkarim Cherkaoui , Bertrand François , Rodrigo Possamai Bastos , Laurent Fesquet 23rd IEEE International Symposium on Asynchronous Circuits and Systems (Async 2017), May 2017, San Diego, CA, United States. pp.65-72, ⟨10.1109/ASYNC.2017.16⟩ Communication dans un congrès hal-01512247v1
	On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept Assia El Hadbi , Abdelkarim Cherkaoui , Oussama Elissati , Jean Simatic , Laurent Fesquet 15th IEEE International New Circuits and Systems Conference (NEWCAS), Jun 2017, Strasbourg, France. pp.305-308, ⟨10.1109/NEWCAS.2017.8010166⟩ Communication dans un congrès hal-01627367v1
	From events to data-driven processing Laurent Fesquet , Jean Simatic , Amani Darwish , Abdelkarim Cherkaoui , Sophie Germain 3rd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), May 2017, Funchal, Portugal Communication dans un congrès hal-01514219v1
	A Subthreshold 30pJ/bit Self-timed Ring Based True Random Number Generator for Internet of Everything Mathieu Coustans , Christian Terrier , Thomas Eberhardt , Stephanie Salgado , Abdelkarim Cherkaoui IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S), Oct 2017, San Francisco, CA, United States. ⟨10.1109/S3S.2017.8308744⟩ Communication dans un congrès hal-01627338v1
	Self-timed Ring based True Random Number Generator: Threat model and countermeasures Grégoire Gimenez , Abdelkarim Cherkaoui , Raphael Frisch , Laurent Fesquet IEEE 2nd International Verification and Security Workshop (IVSW), Jul 2017, Thessaloniki, Greece. pp.31-38, ⟨10.1109/IVSW.2017.8031541⟩ Communication dans un congrès hal-01627350v1
	High Precision Time Measurement using Self-Timed Ring Oscillator based TDC Assia El Hadbi , Abdelkarim Cherkaoui , Oussama Elissati , Laurent Fesquet European Frequency and Time Forum & International Frequency Control Symposium (EFTF 2017), Jul 2017, Besançon, France. pp.77-78, ⟨10.1109/FCS.2017.8088805⟩ Communication dans un congrès hal-01627362v1
	Nouveau dispositif ultra-précis de mesure du temps basé sur un oscillateur auto-séquencé Assia El Hadbi , Abdelkarim Cherkaoui , Oussama Elissati , Laurent Fesquet Colloque GdR SoC-SiP, Jun 2017, Talence, France Communication dans un congrès hal-01627376v1
	CAR: on the highway towards desynchronization François Bertrand , Jean Simatic , Abdelkarim Cherkaoui , Anthony Maure , Laurent Fesquet 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2017, Batumi, Georgia. pp.339-343, ⟨10.1109/ICECS.2017.8292047⟩ Communication dans un congrès hal-01626177v1
	New asynchronous protocols for enhancing area and throughput in bundle-data pipelines Jean Simatic , Abdelkarim Cherkaoui , Rodrigo Possamai Bastos , Laurent Fesquet 29th Symposium on Integrated Circuits and Systems Design (SBCCI 2016), Aug 2016, Belo Horizonte, Brazil. pp.1-6, ⟨10.1109/SBCCI.2016.7724066⟩ Communication dans un congrès hal-01345749v1
	Event-based design for mitigating energy in electronic systems Laurent Fesquet , Jean Simatic , Amani Darwish , Abdelkarim Cherkaoui OAGM & ARW Joint Workshop on "Computer Vision and Robotics" , May 2016, Wels, Austria Communication dans un congrès hal-01345715v1
	A Self-timed Ring based True Random Number Generator with Monitoring and Entropy Assessment A. Cherkaoui , Laurent Fesquet , V. Fischer , A. Aubert University Booth at DATE 2015, Mar 2015, Grenoble, France. pp.session UB02.1 Communication dans un congrès hal-01166869v1
	Self-timed rings as low-phase noise programmable oscillators Laurent Fesquet , Abdelkarim Cherkaoui , Oussama Elissati The 12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), Jun 2014, Trois-Rivières, Canada. 4 p Communication dans un congrès ujm-01011287v1
	A Self-timed Ring Based True Random Number Generator Abdelkarim Cherkaoui , Viktor Fischer , Alain Aubert , Laurent Fesquet International symposium on advanced research in asynchronous circuits and systems - ASYNC 2013, May 2013, Santa Monica - California, United States. pp.99-106 Communication dans un congrès ujm-00840593v1
	True Random Numbers Generation Using Asynchronous Circuits Abdelkarim Cherkaoui , Viktor Fischer , Alain Aubert , Laurent Fesquet Journées scientifiques SEmba 2013, May 2013, St Germain au Mont d'Or, France Communication dans un congrès ujm-00840445v1
	A Very High Speed True Random Number Generator with Entropy Assessment Abdelkarim Cherkaoui , Viktor Fischer , Laurent Fesquet , Alain Aubert Cryptographic Hardware and Embedded Systems -- CHES 2013 15th International Workshop on Cryptographic Hardware and Embedded Systems -- CHES 2013, Aug 2013, Santa Barbara, California, United States. pp.179-196 Communication dans un congrès ujm-00859906v1
	A New Robust True Random Numbers Generator Using Self-Timed Rings Abdelkarim Cherkaoui , Viktor Fischer , Laurent Fesquet , Alain Aubert Cryptographic architectures embedded in reconfigurable devices - Cryptarchi 2012, Jun 2012, Saint-Etienne, France Communication dans un congrès ujm-00712552v1
	Self-Timed Rings as Sources of Entropy A. Cherkaoui , V. Fischer , A. Aubert , Laurent Fesquet 6ème colloque du GDR SOC-SIP du CNRS, Jun 2012, Paris, France Communication dans un congrès hal-00747474v1
	Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs Abdelkarim Cherkaoui , Viktor Fischer , Alain Aubert , Laurent Fesquet Design Automation and Test in Europe (DATE 2012), Mar 2012, Dresden, Germany. pp.1-6 Communication dans un congrès ujm-00667639v1
	Self-Timed Rings as Entropy Sources A. Cherkaoui , Laurent Fesquet , V. Fischer , A. Aubert 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012, Copenhagen, Denmark Communication dans un congrès hal-00747383v1
	Asynchronous Self-Timed Rings for Randomness Generation Abdelkarim Cherkaoui , Alain Aubert , Viktor Fischer , Laurent Fesquet International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2011, bochum, Germany Communication dans un congrès ujm-00667827v1

	Method for generating a unique data specific to an integrated silicon circuit Grégoire Gimenez , Abdelkarim Cherkaoui , Laurent Fesquet France, N° de brevet: FR3106424 (B1) 2022-02-11, EP3851995 (A1). 2021 Brevet hal-04023699v1
	Circuit and Method for Protecting Asynchronous Circuits Laurent Fesquet , A. Cherkaoui , Grégoire Gimenez , Raphael Frisch France, Patent n° : WO/2020/008229. 2020 Brevet hal-02952917v1
	Générateurs de nombres aléatoires vrais Laurent Fesquet , J. Hamon , A. Cherkaoui France, N° de brevet: FR 12 51079. 2012 Brevet hal-00750215v1

Laurent Fesquet

Présentation

Publications

An Area and Power Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits

An accurate time-to-digital converter based on a self-timed ring oscillator for on-the-fly time measurement

Multi-phase low-noise digital ring oscillators with sub-gate-delay resolution

An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study

A Self-Timed Ring based PUF

Asynchronous circuits for new computation paradigms

Static Timing Analysis of Asynchronous Bundled-data Circuits

Benchmarking of shared and distributed memory strategy for stochastic Bayesian machines

Subthreshold Logic for Low-Area and Energy Efficient True Random Number

Low Phase-Noise CMOS Quadrature Oscillator Based on a (Nx4)-stage Self-Timed Ring

Event-based processing: a new paradigm for low-power

A practical framework for specification, verification and design of self-timed pipelines

On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept

From events to data-driven processing

A Subthreshold 30pJ/bit Self-timed Ring Based True Random Number Generator for Internet of Everything

Self-timed Ring based True Random Number Generator: Threat model and countermeasures

High Precision Time Measurement using Self-Timed Ring Oscillator based TDC

Nouveau dispositif ultra-précis de mesure du temps basé sur un oscillateur auto-séquencé

CAR: on the highway towards desynchronization

New asynchronous protocols for enhancing area and throughput in bundle-data pipelines

Event-based design for mitigating energy in electronic systems

A Self-timed Ring based True Random Number Generator with Monitoring and Entropy Assessment

Self-timed rings as low-phase noise programmable oscillators

A Self-timed Ring Based True Random Number Generator

True Random Numbers Generation Using Asynchronous Circuits

A Very High Speed True Random Number Generator with Entropy Assessment

A New Robust True Random Numbers Generator Using Self-Timed Rings

Self-Timed Rings as Sources of Entropy

Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs

Self-Timed Rings as Entropy Sources

Asynchronous Self-Timed Rings for Randomness Generation

Method for generating a unique data specific to an integrated silicon circuit

Circuit and Method for Protecting Asynchronous Circuits

Générateurs de nombres aléatoires vrais