Giorgio Di Natale
21
Documents
Présentation
Giorgio Di Natale received the PhD in Computer Engineering from the Politecnico di Torino in 2003. He is director of research for the National Research Center of France at the TIMA laboratory in Grenoble.
His research interests include hardware security and trust, secure circuits design and test, reliability evaluation and fault tolerance, software implemented hardware fault tolerance, and VLSI testing.
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Using Approximate Circuits Against Hardware TrojansIEEE Design & Test, 2023, 40 (3), pp.8-16. ⟨10.1109/MDAT.2021.3117741⟩
Article dans une revue
hal-03370908v1
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Protection against Hardware Trojans with Logic Testing: Proposed Solutions and Challenges AheadIEEE Design & Test, 2018, 35 (2), pp.73-90. ⟨10.1109/MDAT.2017.2766170⟩
Article dans une revue
lirmm-01688166v1
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On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel AnalysisInformation Security Journal: A Global Perspective, 2014, Trustworthy Manufacturing and Utilization of Secure Devices, 22 (5-6), pp.226-236. ⟨10.1080/19393555.2014.891277⟩
Article dans une revue
lirmm-00991362v1
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Secure JTAG Implementation Using Schnorr ProtocolJournal of Electronic Testing: : Theory and Applications, 2013, 29 (2), pp.193-209. ⟨10.1007/s10836-013-5369-9⟩
Article dans une revue
lirmm-00837904v1
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Providing Confidentiality and Integrity in Ultra Low Power IoT DevicesDTIS 2019 - 14th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Apr 2019, Mykonos, Greece. ⟨10.1109/DTIS.2019.8735090⟩
Communication dans un congrès
hal-02166920v1
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A Comprehensive Approach to a Trusted Test InfrastructureIVSW 2019 - 4th IEEE International Verification and Security Workshop, Jul 2019, Rhodes, Greece. pp.43-48, ⟨10.1109/IVSW.2019.8854428⟩
Communication dans un congrès
lirmm-02306980v1
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SI ECCS: SECure context saving for IoT devicesDTIS 2018 - 13th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. ⟨10.1109/DTIS.2018.8368561⟩
Communication dans un congrès
hal-01740173v1
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A new secure stream cipher for scan chain encryption3rd IEEE International Verification and Security Workshop (IVSW 2018), Jul 2018, Platja d’Aro, Spain. pp.68-73, ⟨10.1109/IVSW.2018.8494852⟩
Communication dans un congrès
lirmm-01867256v1
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A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide ObfuscationIOLTS: International Symposium on On-Line Testing And Robust System Design, Jul 2018, Platja d'Aro, Spain. pp.41-42, ⟨10.1109/IOLTS.2018.8474077⟩
Communication dans un congrès
lirmm-02095736v1
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Encryption of test data: which cipher is better?PRIME: PhD Research in Microelectronics and Electronics, Jul 2018, Prague, Czech Republic. pp.85-88, ⟨10.1109/PRIME.2018.8430366⟩
Communication dans un congrès
lirmm-01867249v1
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Hacking the Control Flow error detection mechanismIVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.51-56, ⟨10.1109/IVSW.2017.8031544⟩
Communication dans un congrès
lirmm-01700739v1
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Hardware Trust through Layout Filling: a Hardware Trojan Prevention TechniqueISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, United States. pp.254-259, ⟨10.1109/ISVLSI.2016.22⟩
Communication dans un congrès
lirmm-01346529v1
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Using Outliers to Detect Stealthy Hardware Trojan Triggering?IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France
Communication dans un congrès
lirmm-01347119v1
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Duplication-based Concurrent Detection of Hardware Trojans in Integrated CircuitsTRUDEVICE, Nov 2016, Barcelona, Spain
Communication dans un congrès
lirmm-01385551v1
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New Testing Procedure for Finding Insertion Sites of Stealthy Hardware TrojansDATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.776-781, ⟨10.7873/DATE.2015.1102⟩
Communication dans un congrès
lirmm-01141619v1
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Hardware Trojan Prevention using Layout-Level Design ApproachECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. ⟨10.1109/ECCTD.2015.7300093⟩
Communication dans un congrès
lirmm-01234072v1
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A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware TrojansIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.49-54, ⟨10.1109/IOLTS.2014.6873671⟩
Communication dans un congrès
lirmm-01025275v1
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Identification of Hardware Trojans triggering signalsFirst Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, May 2013, Avignon, France
Communication dans un congrès
lirmm-00991360v1
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Is Side-Channel Analysis really reliable for detecting Hardware Trojans?DCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.238-242
Communication dans un congrès
lirmm-00823477v1
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SECCS: SECure Context Saving for IoT Devices12e Colloque National du GDR SoC/SiP, Jun 2018, Paris, France. 2018
Poster de conférence
hal-02042659v1
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Detection and Prevention of Hardware Trojan through Logic TestingTRUDEVICE, Nov 2016, Barcelona, Spain. , 4th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, Manufacturing test of secure devices / Reverse engineering countermeasures / Other topics, pp.#33, 2016, Posters IV
Poster de conférence
lirmm-01430007v1
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