Number of documents

193

Giorgio Di Natale


Giorgio Di Natale received the PhD in Computer Engineering from the Politecnico di Torino in 2003. He is director of research for the National Research Center of France at the TIMA laboratory in Grenoble.

His research interests include hardware security and trust, secure circuits design and test, reliability evaluation and fault tolerance, software implemented hardware fault tolerance, and VLSI testing. 


Journal articles37 documents

  • Alessandro Vallero, Alessandro Savino, Athanasios Chatzidimitriou, Manolis Kaliorakis, Maha Kooli, et al.. SyRA: Early System Reliability Analysis for Cross-layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2019, 68 (5), pp.765-783. ⟨10.1109/TC.2018.2887225⟩. ⟨lirmm-01961657⟩
  • Elena Ioana Vatajelu, Giorgio Di Natale. High-Entropy STT-MTJ-based TRNG. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2019, ⟨10.1109/TVLSI.2018.2879439⟩. ⟨hal-01994751⟩
  • Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2019, 38 (3), pp.538-550. ⟨10.1109/TCAD.2018.2818722⟩. ⟨lirmm-01867245⟩
  • Honorio Martin, Pedro Peris-Lopez, Giorgio Di Natale, M. Taouil, Said Hamdioui. Enhancing PUF Based Challenge-Response Sets by Exploiting Various Background Noise Configurations. Electronics, MDPI, 2019, 8 (2), ⟨10.3390/electronics8020145⟩. ⟨hal-02048700⟩
  • Emanuele Valea, Mathieu da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Survey on Security Threats and Countermeasures in IEEE Test Standards. IEEE Design & Test, IEEE, 2019, 36 (3), pp.95-116. ⟨10.1109/MDAT.2019.2899064⟩. ⟨hal-02166858⟩
  • Maha Kooli, Giorgio Di Natale, Alberto Bosio. Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems. Journal of Electronic Testing, Springer Verlag, 2019, ⟨10.1007/s10836-019-05785-0⟩. ⟨hal-02078889⟩
  • J.-M. Dutertre, Vincent Beroulle, Philippe Candelier, Stephan de Castro, Louis-Barthelemy Faber, et al.. Sensitivity to Laser Fault Injection: CMOS FD-SOI vs. CMOS bulk. IEEE Transactions on Device and Materials Reliability, Institute of Electrical and Electronics Engineers, 2019, 19 (1), pp.6-15. ⟨10.1109/TDMR.2018.2886463⟩. ⟨hal-01971932⟩
  • Honorio Martin, Giorgio Di Natale, Luis Entrena. Towards a Dependable True Random Number Generator With Self-Repair Capabilities. IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2018, 65 (1), pp.247-256. ⟨10.1109/TCSI.2017.2711033⟩. ⟨lirmm-01700736⟩
  • Mario Barbareschi, Giorgio Di Natale, Lionel Torres, Antonino Mazzeo. A Ring Oscillator-Based Identification Mechanism Immune to Aging and External Working Conditions. IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2018, 65 (2), pp.700-711. ⟨10.1109/TCSI.2017.2727546⟩. ⟨lirmm-01692481⟩
  • Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Protection against Hardware Trojans with Logic Testing: Proposed Solutions and Challenges Ahead. IEEE Design & Test, IEEE, 2018, 35 (2), pp.73-90. ⟨10.1109/MDAT.2017.2766170⟩. ⟨lirmm-01688166⟩
  • Raphael Andreoni Camponogara-Viera, Jean-Max Dutertre, Marie-Lise Flottes, Olivier Potin, Giorgio Di Natale, et al.. Assessing Body Built-In Current Sensors for Detection of Multiple Transient Faults. Microelectronics Reliability, Elsevier, 2018, 88-90 (29th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2018)), pp.128-134. ⟨10.1016/j.microrel.2018.07.111⟩. ⟨hal-01893676⟩
  • David Atienza, Giorgio Di Natale. Report on DATE 2017 in Lausanne. IEEE Design & Test, IEEE, 2017, 34 (4), pp.76-77. ⟨10.1109/MDAT.2017.2693266⟩. ⟨lirmm-01700737⟩
  • Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio, Pascal Benoit, et al.. Computing reliability: On the differences between software testing and software fault injection techniques. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2017, 50, pp.102-112. ⟨10.1016/j.micpro.2017.02.007⟩. ⟨lirmm-01693156⟩
  • Ioana Vatajelu, Giorgio Di Natale, Mario Barbareschi, Lionel Torres, Marco Indaco, et al.. STT-MRAM-Based PUF Architecture exploiting Magnetic Tunnel Junction Fabrication-Induced Variability. ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2016, 13 (1), ⟨10.1145/2790302⟩. ⟨lirmm-01234046⟩
  • Stephan de Castro, Jean-Max Dutertre, Bruno Rouzeyre, Giorgio Di Natale, Marie-Lise Flottes. Frontside Versus Backside Laser Injection: A Comparative Study. ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2016, Special Issue on Secure and Trustworthy Computing, 13 (1), pp.7. ⟨10.1145/2845999⟩. ⟨lirmm-01444121⟩
  • Mario Barbareschi, Giorgio Di Natale, Florent Bruguier, Pascal Benoit, Lionel Torres. Ring oscillators analysis for security purposes in Spartan-6 FPGAs. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, 47 (Part A), pp.3-10. ⟨10.1016/j.micpro.2016.06.005⟩. ⟨lirmm-01421001⟩
  • Lilian Bossuet, Giorgio Di Natale, Paris Kitsos. Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE). Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, 47 (A), pp.1-2. ⟨lirmm-01499334⟩
  • Alessandro Vallero, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Maha Kooli, et al.. Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2015, 39 (8), pp.1204-1214. ⟨10.1016/j.micpro.2015.06.003⟩. ⟨lirmm-01297595⟩
  • Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Thwarting Scan-Based Attacks on Secure-ICs with On-Chip Comparison. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (4), pp.947-951. ⟨10.1109/TVLSI.2013.2257903⟩. ⟨lirmm-00841650⟩
  • Jean da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Test versus Security: Past and Present. IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2014, 2 (1), pp.50-62. ⟨http://www.computer.org/csdl/trans/ec/preprint/06733305-abs.html⟩. ⟨10.1109/TETC.2014.2304492⟩. ⟨lirmm-00989627⟩
  • Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale. Testing Methods for PUF-Based Secure Key Storage Circuits. Journal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.581-594. ⟨10.1007/s10836-014-5471-7⟩. ⟨lirmm-01234059⟩
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Multi-Level Ionizing-Induced Transient Fault Simulator. Information Security Journal: A Global Perspective, Taylor & Francis, 2014, 22 (5-6), pp.251-264. ⟨http://www.tandfonline.com/doi/abs/10.1080/19393555.2014.891280#.VEEP7tTLc4l⟩. ⟨10.1080/19393555.2014.891280⟩. ⟨lirmm-01075393⟩
  • Giorgio Di Natale. TRUDEVICE: A COST Action on "Trustworthy Manufacturing and Utilization of Secure Devices" (Editorial). Information Security Journal: A Global Perspective, Taylor & Francis, 2014, 22 (5-6), pp.205-207. ⟨http://www.tandfonline.com/doi/abs/10.1080/19393555.2014.891283#.VEEVOdTLc4k⟩. ⟨10.1080/19393555.2014.891283⟩. ⟨lirmm-01075402⟩
  • Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis. Information Security Journal: A Global Perspective, Taylor & Francis, 2014, Trustworthy Manufacturing and Utilization of Secure Devices, 22 (5-6), pp.226-236. ⟨10.1080/19393555.2014.891277⟩. ⟨lirmm-00991362⟩
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS. Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2289-2294. ⟨10.1016/j.microrel.2014.07.151⟩. ⟨emse-01094805⟩
  • Amitabh Das, Jean da Rolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, et al.. Secure JTAG Implementation Using Schnorr Protocol. Journal of Electronic Testing, Springer Verlag, 2013, 29 (2), pp.193-209. ⟨10.1007/s10836-013-5369-9⟩. ⟨lirmm-00837904⟩
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre. A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic. Journal of Electronic Testing, Springer Verlag, 2013, pp.001-010. ⟨10.1007/s10836-013-5359-y⟩. ⟨lirmm-00838389⟩
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. Microelectronics Reliability, Elsevier, 2013, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 53 (9), pp.1320-1324. ⟨10.1016/j.microrel.2013.07.069⟩. ⟨emse-01100723⟩
  • Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Differential Scan Attack on Advanced DFT Structures. ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery, 2013, 18 (4), pp.58. ⟨10.1145/2505014⟩. ⟨lirmm-01075410⟩
  • Savino Alessandro, Stefano Di Carlo, Politano Gianfranco, Alfredo Benso, Alberto Bosio, et al.. Statistical Reliability Estimation of Microprocessor-Based Systems. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2012, 61 (11), pp.1521-1534. ⟨lirmm-00744608⟩
  • Jean da Rolt, Amitabh Das, Santos Ghosh, Giorgio Di Natale, Marie-Lise Flottes, et al.. Scan attacks on side-channel and fault attack resistant public-key implementations. Journal of Cryptographic Engineering, Springer, 2012, 2 (4), pp.207-219. ⟨10.1007/s13389-012-0045-z⟩. ⟨lirmm-00805687⟩
  • Rodrigo Possamai Bastos, Frank Sill Torres, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Novel Transient-Fault Detection Circuit Featuring Enhanced Bulk Built-in Current Sensor with Low-Power Sleep Mode. Microelectronics Reliability, Elsevier, 2012, 52 (9-10), pp.1781-1786. ⟨10.1016/j.microrel.2012.06.149⟩. ⟨lirmm-00715117⟩
  • Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. Self-Test Techniques for Crypto-Devices. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2009, 18 (2), pp.329-333. ⟨10.1109/TVLSI.2008.2010045⟩. ⟨lirmm-00365359⟩
  • Giorgio Di Natale, Doulcier Marion, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard. Journal of Electronic Testing, Springer Verlag, 2009, 25 (4-5), pp.269-278. ⟨10.1007/s10836-009-5106-6⟩. ⟨lirmm-00423026⟩
  • Alberto Bosio, Giorgio Di Natale. March Test BDN, a new March Test for Dynamic Faults. Journal of Control Engineering and Applied Informatics, SRAIT, 2008, 10 (2), pp.3-9. ⟨lirmm-00324111⟩
  • Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. March Test Generation Revealed. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2008, 57 (12), pp.1704-1713. ⟨10.1109/TC.2008.105⟩. ⟨lirmm-00350780⟩
  • S. Cavallaro, C. Beck, E. Berthoumieux, R. Dayras, E. de Filippo, et al.. Origin and decay-properties of binary fragments produced in the $^{35}$Cl + $^{24}$Mg reaction at E/A AP $ \approx$ 8 MeV/A. Nuclear Physics A, Elsevier, 1995, 583, pp.161-164. ⟨in2p3-00015254⟩

Conference papers123 documents

  • R. Leveugle, M. Portolan, S. Di Carlo, A. Savino, Giorgio Di Natale, et al.. Alternatives to fault injections for early safety/security evaluations. 24th IEEE European Test Symposium (ETS 2019), May 2019, Baden Baden, Germany. ⟨hal-02110119⟩
  • Emanuele Valea, Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Encryption-Based Secure JTAG. DDECS: Design and Diagnostics of Electronic Circuits Systems, Apr 2019, Cluj-Napoca, Romania. ⟨10.1109/DDECS.2019.8724654⟩. ⟨hal-02149061⟩
  • Elena Ioana Vatajelu, Giorgio Di Natale, L. Anghel. Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN). IEEE VLSI Test Symposium (VTS 2019), Apr 2019, Monterey, United States. ⟨hal-02166904⟩
  • Giorgio Di Natale, Elena Ioana Vatajelu, K. Senthamarai Kannan, L. Anghel. Hidden-Delay-Fault Sensor for Test, Reliability and Security. IEEE Design Automation and Test Conference in Europe (DATE 2019), Mar 2019, Florence, Italy. ⟨hal-02166929⟩
  • Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, et al.. Providing Confidentiality and Integrity in Ultra Low Power IoT Devices. DTIS: Design & Technology of Integrated Systems In Nanoscale Era, Apr 2019, Mykonos, Greece. ⟨10.1109/DTIS.2019.8735090⟩. ⟨hal-02166920⟩
  • L. Anghel, Giorgio Di Natale, Benoit Miramond, Elena Ioana Vatajelu, E. Vianello. Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies. 26th IFIP IEEE International Conference on Very Large Scale Integration (VLSI SOC 2018), Oct 2018, Verona, Italy. ⟨hal-01961756⟩
  • Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, et al.. A new secure stream cipher for scan chain encryption. IVSW: International Verification and Security Workshop, Jul 2018, Platja d’Aro, Spain. ⟨lirmm-01867256⟩
  • Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Does stream cipher-based scan chains encryption really prevent scan attacks?. TRUDEVICE Workshop, Mar 2018, Dresden, Germany. ⟨lirmm-01867286⟩
  • Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, et al.. SECCS: SECure Context Saving for IoT Devices. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. ⟨hal-01740173⟩
  • Honorio Martin, Luis Entrena, Sophie Dupuis, Giorgio Di Natale. A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation. IOLTS: International Symposium on On-Line Testing And Robust System Design, Jul 2018, Platja d'Aro, Spain. pp.41-42, ⟨10.1109/IOLTS.2018.8474077⟩. ⟨lirmm-02095736⟩
  • Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, et al.. Encryption of test data: which cipher is better?. PRIME: PhD Research in Microelectronics and Electronics, Jul 2018, Prague, Czech Republic. pp.85-88, ⟨10.1109/PRIME.2018.8430366⟩. ⟨lirmm-01867249⟩
  • Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, et al.. The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. IOLTS: International On-Line Testing Symposium, Jul 2018, Platja d’Aro, Spain. pp.214-219, ⟨10.1109/IOLTS.2018.8474230⟩. ⟨emse-01856000⟩
  • Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan de Castro, Louis-Barthelemy Faber, et al.. Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model. FDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. pp.1-6, ⟨10.1109/FDTC.2018.00009⟩. ⟨emse-01856008⟩
  • Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Scan Chain Encryption. DOCTIS: Journée des Doctorants de l’école doctorale I2S, 2017, Montpellier, France. ⟨lirmm-01867277⟩
  • Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Experimentations on scan chain encryption with PRESENT. IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.45-50, ⟨10.1109/IVSW.2017.8031543⟩. ⟨lirmm-01699258⟩
  • Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, et al.. Scan chain encryption for the test, diagnosis and debug of secure circuits. ETS: European Test Symposium, May 2017, Limassol, Cyprus. ⟨10.1109/ETS.2017.7968248⟩. ⟨lirmm-01699254⟩
  • Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto. Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories. IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.128-133, ⟨10.1109/IVSW.2017.8031552⟩. ⟨hal-01591549⟩
  • Mauro Contini, Giorgio Di Natale, Annelie Heuser, Thomas Poppelmann, Nele Mentens. Do we need a holistic approach for the design of secure IoT systems?. CF: Computing Frontiers, May 2017, Siena, Italy. pp.425-430, ⟨10.1145/3075564.3079070⟩. ⟨hal-01628683⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre. Hacking the Control Flow error detection mechanism. IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.51-56, ⟨10.1109/IVSW.2017.8031544⟩. ⟨lirmm-01700739⟩
  • Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Regis Leveugle. Reliability of computing systems: From flip flops to variables. IOLTS: International On-Line Testing Symposium, Jul 2017, Thessaloniki, Greece. pp.196-198, ⟨10.1109/IOLTS.2017.8046242⟩. ⟨lirmm-01700744⟩
  • Suman Sau, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Amlan Chakrabarti. SCHIFI: Scalable and flexible high performance FPGA-based fault injector. DCIS: Design of Circuits and Integrated Systems, Nov 2016, Granada, Spain. ⟨10.1109/DCIS.2016.7845375⟩. ⟨lirmm-01700747⟩
  • Luca Gnoli, Matteo Bollo, Marco Vacca, Mariagrazia Graziano, Giorgio Di Natale. True random number generator based on nanomagnets. NMDC: Nanotechnology Materials and Devices Conference, Oct 2016, Toulouse, France. ⟨10.1109/NMDC.2016.7777089⟩. ⟨lirmm-01444398⟩
  • Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Federico Venini. Faster-than-at-speed execution of functional programs: An experimental analysis. VLSI-SoC: Very Large Scale Integration and System-on-Chip, Sep 2016, Tallinn, Estonia. ⟨10.1109/VLSI-SoC.2016.7753581⟩. ⟨lirmm-01444403⟩
  • Manikandan Palanichamy, Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, et al.. Duplication-based Concurrent Detection of Hardware Trojans in Integrated Circuits. TRUDEVICE, Nov 2016, Barcelona, Spain. ⟨lirmm-01385551⟩
  • Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto. Security primitives (PUF and TRNG) with STT-MRAM. VTS: VLSI Test Symposium, Apr 2016, Las Vegas, United States. ⟨10.1109/VTS.2016.7477292⟩. ⟨lirmm-01374573⟩
  • Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio. Cache- and register-aware system reliability evaluation based on data lifetime analysis. VTS: VLSI Test Symposium, Apr 2016, Las Vegas, United States. ⟨10.1109/VTS.2016.7477299⟩. ⟨lirmm-01374569⟩
  • Alessandro Vallero, Alessandro Savino, Gianfranco Michele Maria Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, et al.. Cross-layer system reliability assessment framework for hardware faults. ITC: International Test Conference, Nov 2016, Fort Worth, TX, United States. ⟨10.1109/TEST.2016.7805863⟩. ⟨lirmm-01444774⟩
  • Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Ernesto Sanchez, et al.. Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs. VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, Sep 2016, Tallinn, Estonia. pp.130-151, ⟨10.1007/978-3-319-67104-8_7⟩. ⟨hal-01675205⟩
  • Maha Kooli, Giorgio Di Natale, Alberto Bosio. Cache-aware reliability evaluation through LLVM-based analysis and fault injection. IOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. pp.19-22, ⟨10.1109/IOLTS.2016.7604663⟩. ⟨lirmm-01444619⟩
  • Papa-Sidy Ba, Sophie Dupuis, Manikandan Palanichamy, Marie-Lise Flottes, Giorgio Di Natale, et al.. Hardware Trust through Layout Filling: a Hardware Trojan Prevention Technique. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, United States. pp.254-259, ⟨10.1109/ISVLSI.2016.22⟩. ⟨lirmm-01346529⟩
  • Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Using Outliers to Detect Stealthy Hardware Trojan Triggering?. IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France. ⟨lirmm-01347119⟩
  • Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto. STT-MTJ-based TRNG with on-the-fly temperature/current variation compensation. IOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. pp.179-184, ⟨10.1109/IOLTS.2016.7604694⟩. ⟨lirmm-01444408⟩
  • Firas Kaddachi, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Mojtaba Ebrahimi, et al.. System-level reliability evaluation through cache-aware software-based fault injection. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. ⟨10.1109/DDECS.2016.7482446⟩. ⟨lirmm-01444721⟩
  • Antonio Varriale, Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto, Pascal Trotta, et al.. SEcube™: An open-source security platform in a single SoC. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2016, Istanbaul, Turkey. ⟨10.1109/DTIS.2016.7483810⟩. ⟨lirmm-01444711⟩
  • Mojtaba Ebrahimi, Maryam Rashvand, Firas Kaddachi, Mehdi B. Tahoori, Giorgio Di Natale. Revisiting software-based soft error mitigation techniques via accurate error generation and propagation models. IOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. pp.66-71, ⟨10.1109/IOLTS.2016.7604674⟩. ⟨lirmm-01444612⟩
  • Alberto Carelli, Giorgio Di Natale, Pascal Trotta, Tiziana Margaria. Towards Model Driven Design of Crypto Primitives and Processes. SAM: Sensor Array and Multichannel Signal Processing, Jul 2016, Rio de Janeiro, Brazil. pp.152-158. ⟨lirmm-01444948⟩
  • Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto. Towards a Highly Reliable SRAM-based PUFs. DATE: Design, Automation and Test in Europe, Mar 2016, Dresden, Germany. pp.273-276. ⟨lirmm-01374279⟩
  • Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto. Exploiting the Variability of the Magnetic Tunnel Junction for Security Purposes. e-NVM: Leading Edge Embedded NVM, Sep 2015, Gardanne, France. ⟨lirmm-01276293⟩
  • Antonio Varriale, Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto, Tiziana Margaria. SEcubeTM: The most advanced, Open Source Security Platform in a Single Chip. TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. ⟨lirmm-01276298⟩
  • Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto. Zero Bit-Error-Rate Weak PUF based on Spin-Transfer-Torque MRAM Memories. TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. ⟨lirmm-01276300⟩
  • Mafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Multi-segment Enhanced Scan-chains for Secure ICs. TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. ⟨lirmm-01276304⟩
  • Mario Barbareschi, Giorgio Di Natale, Florent Bruguier, Pascal Benoit, Lionel Torres. Ring Oscillators Analysis for FPGA Security Purposes. TRUDEVICE, Mar 2015, Grenoble, France. ⟨lirmm-01419909⟩
  • Marie-Lise Flottes, João Azevedo, Giorgio Di Natale, Bruno Rouzeyre. Session-less based thermal-aware 3D-SIC test scheduling. ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. ⟨10.1109/ETS.2015.7138732⟩. ⟨lirmm-01922990⟩
  • Jerome Rampon, Renaud Perillat, Lionel Torres, Pascal Benoit, Giorgio Di Natale, et al.. Digital Right Management for IP Protection. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.200-203, ⟨10.1109/ISVLSI.2015.127⟩. ⟨lirmm-01234082⟩
  • Ioana Vatajelu, Giorgio Di Natale, Lionel Torres, Paolo Prinetto. STT-MRAM-Based Strong PUF Architecture. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.467-472, ⟨10.1109/ISVLSI.2015.128⟩. ⟨lirmm-01234079⟩
  • Raphael Andreoni Camponogara-Viera, Rodrigo Possamai Bastos, Jean-Max Dutertre, Olivier Potin, Marie-Lise Flottes, et al.. Validation Of Single BBICS Architecture In Detecting Multiple Faults. ATS: Asian Test Symposium, Nov 2015, Mumbai, India. ⟨lirmm-01234067⟩
  • Ricardo Chaves, Giorgio Di Natale, Lejla Batina, Shivam Bhasin, Baris Ege, et al.. Challenges in Designing Trustworthy Cryptographic Co-Processors. ISCAS: International Symposium on Circuits and Systems, May 2015, Lisbon, Portugal. pp.2009-2012, ⟨10.1109/ISCAS.2015.7169070⟩. ⟨lirmm-01234083⟩
  • Papa-Sidy Ba, Manikandan Palanichamy, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, et al.. Hardware Trojan Prevention using Layout-Level Design Approach. ECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. ⟨10.1109/ECCTD.2015.7300093⟩. ⟨lirmm-01234072⟩
  • Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, et al.. 3D DFT Challenges and Solutions. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.603-608, ⟨10.1109/ISVLSI.2015.11⟩. ⟨lirmm-01234076⟩
  • Stephan de Castro, Jean-Max Dutertre, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuits. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.362-367, ⟨10.1109/ISVLSI.2015.76⟩. ⟨emse-01227138⟩
  • Stephan de Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Sensitivity to fault laser injection: a comparison between 28nm bulk and FD-SOI technology. TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. ⟨lirmm-01234094⟩
  • Mafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Hierarchical Secure DfT. TRUDEVICE Workshop, Sep 2015, St Malo, France. ⟨lirmm-01234095⟩
  • Sophie Dupuis, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Papa-Sidy Ba. New Testing Procedure for Finding Insertion Sites of Stealthy Hardware Trojans. DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. pp.776-781, ⟨10.7873/DATE.2015.1102⟩. ⟨lirmm-01141619⟩
  • Ioana Vatajelu, Giorgio Di Natale, Marco Indaco, Paolo Prinetto. STT MRAM-Based PUFs. DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. pp.872-875, ⟨10.7873/DATE.2015.0505⟩. ⟨lirmm-01234087⟩
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Simulating Laser Effects on ICs, from Physical Level to Gate Level: a comprehensive approach. TRUDEVICE Workshop, May 2014, Paderborn, Germany. ⟨lirmm-01119614⟩
  • Maha Kooli, Giorgio Di Natale, Pascal Benoit, Alberto Bosio, Lionel Torres, et al.. Fault injection tools based on Virtual Machines. ReCoSoC: Reconfigurable and Communication-Centric Systems-on-Chip, May 2014, Montpellier, France. ⟨10.1109/ReCoSoC.2014.6861351⟩. ⟨hal-01075479⟩
  • Vincent Beroulle, Philippe Candelier, Stephan de Castro, Giorgio Di Natale, Jean-Max Dutertre, et al.. Laser-Induced Fault Effects in Security-Dedicated Circuits. VLSI-SoC: Very Large Scale Integration and System-on-Chip, Oct 2014, Playa del Carmen, Mexico. pp.220-240, ⟨10.1007/978-3-319-25279-7_12⟩. ⟨hal-01383737⟩
  • Jean-Max Dutertre, Stephan de Castro, Alexandre Sarafianos, Noémie Boher, Bruno Rouzeyre, et al.. Laser attacks on integrated circuits: from CMOS to FD-SOI. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. ⟨10.1109/DTIS.2014.6850664⟩. ⟨emse-01099042⟩
  • Sophie Dupuis, Papa-Sidy Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware Trojans. IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.49-54, ⟨10.1109/IOLTS.2014.6873671⟩. ⟨lirmm-01025275⟩
  • Stefano Di Carlo, Alessandro Vallero, Dimitris Gizopoulos, Giorgio Di Natale, Antonio Gonzales, et al.. Cross-Layer Early Reliability Evaluation: Challenges and Promises. IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.228-233, ⟨10.1109/IOLTS.2014.6873704⟩. ⟨lirmm-01234123⟩
  • Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale. Secure Test Method for Fuzzy Extractor. Joint MEDIAN-TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. ⟨lirmm-01234106⟩
  • Cristiana Bolchini, Luca Cassano, Giorgio Di Natale. Multi-stage Cross-layer Hardware Trojan Prevention, Detection and Tolerance. Joint MEDIAN-TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. ⟨lirmm-01234110⟩
  • Nicolas Sklavos, Giorgio Di Natale. TRUDEVICE Project: Trustworthy Manufacturing and Utilization of Secure Devices. HiPEAC Computing Systems Week (CSW), Oct 2014, Athens, Greece. ⟨lirmm-01234099⟩
  • Giorgio Di Natale, Paolo Prinetto, Ioana Vatajelu. MRAM-based PUF. Joint MEDIAN-TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. ⟨lirmm-01234112⟩
  • Said Hamdioui, Giorgio Di Natale, Battum Van, Jean-Luc Danger, Fethulah Smailbegovic, et al.. Hacking and Protecting IC Hardware. DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. ⟨10.7873/DATE.2014.112⟩. ⟨lirmm-01234147⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. Built-In Self-Test for Manufacturing TSV Defects before bonding. VTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. ⟨10.1109/VTS.2014.6818771⟩. ⟨lirmm-00989682⟩
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Layout-Aware Laser Fault Injection Simulation and Modeling: from physical level to gate level. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. ⟨10.1109/DTIS.2014.6850665⟩. ⟨lirmm-01119592⟩
  • Luca Cassano, Alberto Bosio, Giorgio Di Natale. A novel Adaptive Fault Tolerant Flip-Flop Architecture based on TMR. ETS: European Test Symposium, May 2014, Paderborn, Germany. ⟨10.1109/ETS.2014.6847831⟩. ⟨lirmm-01234133⟩
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Customized Cell Detector for Laser-Induced-Fault Detection. IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Spain. pp.37-42, ⟨10.1109/IOLTS.2014.6873669⟩. ⟨lirmm-01119576⟩
  • Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, et al.. 2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.386-391, ⟨10.1109/ISVLSI.2014.83⟩. ⟨lirmm-01119605⟩
  • Stefano Di Carlo, Alessandro Vallero, Dirnitris Gizopoulos, Giorgio Di Natale. Cross-Layer Early Reliability Evaluation for the Computing cOntinuum. DSD: Digital System Design, Aug 2014, Verona, Italy. pp.199-205, ⟨10.1109/DSD.2014.65⟩. ⟨lirmm-01234117⟩
  • Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale. Testing PUF-Based Secure Key Storage Circuits. DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. ⟨10.7873/DATE.2014.207⟩. ⟨lirmm-01234141⟩
  • Maha Kooli, Giorgio Di Natale. A survey on simulation-based fault injection tools for complex systems. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorini, Greece. ⟨10.1109/DTIS.2014.6850649⟩. ⟨hal-01075473⟩
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. ESREF: European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Sep 2013, Arcachon, France. pp.B3c-2 #68. ⟨hal-00872705⟩
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A smart test controller for scan chains in secure circuits. IOLTS: International On-Line Testing Symposium, Jul 2013, Chania, Greece. pp.228-229, ⟨10.1109/IOLTS.2013.6604085⟩. ⟨lirmm-01430814⟩
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Laser-Induced Fault Simulation. EUROMICRO DSD/SEAA, Sep 2013, Santander, Spain. pp.609-614, ⟨10.1109/DSD.2013.72⟩. ⟨lirmm-01430807⟩
  • Rodrigo Possamai Bastos, Franck Sill Torres, Jean Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, et al.. A Bulk Built-in Sensor for Detection of Fault Attacks. HOST: Hardware-Oriented Security and Trust, Jun 2013, Austin, TX, United States. pp.51-54, ⟨10.1109/HST.2013.6581565⟩. ⟨lirmm-01430800⟩
  • Hakim Zimouche, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale. A BIST Method for TSVs Pre-Bond Test. IDT'13: 8th IEEE International Design & Test Symposium, Dec 2013, Marrakesh, Morocco. pp.1-6, ⟨10.1109/IDT.2013.6727081⟩. ⟨lirmm-00989727⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. TSVs Pre-Bond Testing: a test scheme for capturing BIST responses. 3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States. ⟨lirmm-00989707⟩
  • Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Identification of Hardware Trojans triggering signals. First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, May 2013, Avignon, France. ⟨lirmm-00991360⟩
  • Yassine Fkih, Pascal Vivet, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A 3D IC BIST for pre-bond test of TSVs using Ring Oscillators. NEWCAS: New Circuits and Systems, Jun 2013, Paris, France. pp.001-004. ⟨lirmm-00838524⟩
  • Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, et al.. 3D Design For Test Architectures Based on IEEE P1687. 3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States. ⟨lirmm-00989717⟩
  • Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, et al.. A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. pp.157-163, ⟨10.1109/PATMOS.2013.6662169⟩. ⟨lirmm-00968621⟩
  • Rodolphe Giroudeau, Florent Hernandez, Michel Gendreau, Marie-Lise Flottes, Giorgio Di Natale, et al.. Circuits intégrés en 3D. ROADEF: Recherche Opérationnelle et Aide à la Décision, Apr 2012, Angers, France. ⟨lirmm-00805058⟩
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On-Chip Comparison for Testing Secure ICs. DCIS'2012: Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.112-117. ⟨lirmm-00795205⟩
  • Rodrigo Possamai Bastos, Frank Sill Torres, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode. ESREF: European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Oct 2012, Cagliari, Italy. ⟨hal-00867864⟩
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Are Advanced DfT Structures Sufficient for Preventing Scan-Attacks?. VTS'12: 30th IEEE VLSI Test Symposium, Apr 2012, Maui, Hawai, United States. IEEE, pp.246-251, 2012, IEEE Catalog number : CFP12029-CDR. 〈http://www.tttc-vts.org/public_html/new/2012/index.php〉. 〈lirmm-00694536〉
  • Jean Da Rolt, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Amitabh Das, et al.. A Scan-based Attack on Elliptic Curve Cryptosystems in presence of Industrial Design-for-Testability Structures. IEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, United States. http://www.dfts.org/. ⟨lirmm-00744472⟩
  • Jean Da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, et al.. A New Scan Attack on RSA in Presence of Industrial Countermeasures. Third International Workshop on Constructive Side-Channel Analysis and Secure Design, May 2012, Darmstadt, Germany. pp.89-104. ⟨lirmm-00719986⟩
  • Giorgio Di Natale, Sophie Dupuis, Bruno Rouzeyre. Is Side-Channel Analysis really reliable for detecting Hardware Trojans?. DCIS: Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.238-242. ⟨lirmm-00823477⟩
  • Jean Da Rolt, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. New side-channel attack against scan chains. 9th CryptArchi Workshop (2011), Jun 2011, Bochum, Germany. pp.2. ⟨lirmm-00648575⟩
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. How to Sample Results of Concurrent Error Detection Schemes in Transient Fault Scenarios?. RADECS: Radiation and Its Effects on Components and Systems, Sep 2011, Sevilla, Spain. pp.635-642, ⟨10.1109/RADECS.2011.6131361⟩. ⟨lirmm-00701776⟩
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A New Bulk Built-in Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies. DFT'2011: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2011, Vancouver, Canada. pp.302-308, ⟨10.1109/DFT.2011.15⟩. ⟨lirmm-00701789⟩
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Timing Issues for an Efficient Use of Concurrent Error Detection Codes. LATW: Latin American Test Workshop, Mar 2011, Porto de Galinhas, Brazil. pp.1-6, ⟨10.1109/LATW.2011.5985933⟩. ⟨lirmm-00627427⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Real. Power Consumption Traces Realignment to Improve Differential Power Analysis. DDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Germany. pp.201-206. ⟨lirmm-00592005⟩
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. New Security Threats Against Chips Containing Scan Chain Structures. HOST'11: IEEE International Symposium on Hardware-Oriented Security and Trust, San Diego, CA, United States. pp.105-110. ⟨lirmm-00599690⟩
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan Attacks and Countermeasures in Presence of Scan Response Compactors. ETS: European Test Symposium, May 2011, Trondheim, Norway. pp.19-24, ⟨10.1109/ETS.2011.30⟩. ⟨lirmm-00647062⟩
  • Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption Standard. IOLTS: International On-Line Testing Symposium, Jul 2010, Corfu, Greece. pp.223-228, ⟨10.1109/IOLTS.2010.5560196⟩. ⟨lirmm-00539232⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Ensuring High Testability without Degrading Security. DDECS'10: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Vienna, Austria. pp.6. ⟨lirmm-00480710⟩
  • Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption Standard. ETS: European Test Symposium, May 2010, Prague, Czech Republic. ⟨lirmm-00493247⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka. Waveforms re-Alignment to Improve DPA Attacks. CryptArchi: Cryptographic Architectures, Jun 2010, Gif-sur-Yvette, France. ⟨lirmm-00539994⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers. DELTA'10: Fifth IEEE International Symposium on Electronic Design, Test and Application, Jan 2010, Ho Chi Minh City, Vietnam. pp.256-261. ⟨lirmm-00539993⟩
  • Alberto Bosio, Giorgio Di Natale. LIFTING: An open source logic simulator. DATE: Design, Automation and Test in Europe, 2009, Nice, France. ⟨lirmm-00407166⟩
  • Marie-Lise Flottes, Giorgio Di Natale, Paolo Maistri, Bruno Rouzeyre, Régis Leveugle. Ensuring High Testability without Degrading Security. ETS: European Test Symposium, May 2009, Seville, Spain. ⟨lirmm-00407163⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Execution Time Reduction of Differential Power Analysis Experiments. LATW'09: 10th Latin-American Test Workshop, Mar 2009, Armaçao dos Buzios, Brazil, pp.1-5, ⟨10.1109/LATW.2009.4813819⟩. ⟨lirmm-00367712⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Tutorial on Design For Testability & Digital Security. IEEE 10th Latin American Test Workshop, 2009, Buzios, Brazil. ⟨lirmm-00407161⟩
  • Alberto Bosio, Giorgio Di Natale. LIFTING: A Flexible Open-Source Fault Simulator. ATS: Asian Test Symposium, Nov 2008, Saporro, Japan. pp.035-040. ⟨lirmm-00343610⟩
  • Alberto Bosio, Giorgio Di Natale. March Test BDN: A new March Test for Dynamic Faults. AQTR'08: Automation, Quality and Testing, Robotics, May 2008, Cluj-Napoca, Romania, pp.085-089. ⟨lirmm-00303528⟩
  • Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for the Advanced Encryption Standard. ETS: European Test Symposium, May 2008, Verbania, Italy. pp.13-18. ⟨lirmm-00285868⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Stuck-at-Faults Test using Differential Power Analysis. LPonTR'08: Workshop on Low Power Design Impact on Test and Reliability, May 2008, Italy. ⟨lirmm-00332529⟩
  • Philipp Öhler, Sybille Hellebrand, Alberto Bosio, Giorgio Di Natale. Modularer Selbsttest und Optimierte Reparaturanalyse für Eingebettete Speicher. ZUE'08: Zuverlässigkeit und Entwurf, Germany. pp.049-056. ⟨lirmm-00332558⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for Substitution Boxes in Integrated Cryptographic. DCIS'08: Conference on Design of Circuits and Integrated Systems, Nov 2008, pp.27-32. ⟨lirmm-00363783⟩
  • Alberto Bosio, Giorgio Di Natale. LIFTING: an Open-Source Logic Simulator. SAME'08: Sophia-Antipolis Forum on MicroElectronics 2008, Sep 2008, Sophia-Antipolis, France. ⟨lirmm-00363795⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An Integrated Validation Environment for Differential Power Analysis. SAME'08: Sophia-Antipolis Forum on MicroElectronics 2008, Sep 2008, Sophia-Antipolis, France. ⟨lirmm-00363796⟩
  • Stefano Di Carlo, Giorgio Di Natale, Mariani Riccardo. On-Line Instruction-Checking in Pipelined Microprocessors. ATS: Asian Test Symposium, Nov 2008, Saporro, Japan. pp.377-382, ⟨10.1109/ATS.2008.47⟩. ⟨lirmm-00363689⟩
  • Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. Low Cost Self-Test of Crypto-Devices. WDSN'08: 2nd Workshop on Dependable and Secure Nanocomputing, Jun 2008, Anchorage, Canada, United States. pp.41-46. ⟨lirmm-00295108⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An Integrated Validation Environment for Differential Power Analysis. DELTA: Electronic Design, Test and Applications, Jan 2008, Hong Kong, China. pp.527-532, ⟨10.1109/DELTA.2008.61⟩. ⟨lirmm-00407165⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Observability of Stuck-at-Faults with Differential Power Analysis. LATW'08: IEEE Latin American Test Workshop, Feb 2008, Mexico. pp.N/A. ⟨lirmm-00295498⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Parity Bit Scheme for SBOX in AES Circuits. DDECS'07: Design and Diagnostics of Electronic Cicruits and Systems, Apr 2007, Cracovie, Pologne, pp.267-271. ⟨lirmm-00141799⟩
  • Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Marion Doulcier. Test and Security. CryptArchi: Cryptographic Architectures, Jun 2007, Montpellier, France. ⟨lirmm-00163017⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IOLTS: International On-Line Testing Symposium, Jul 2007, Heraklion, Crete, Greece. pp.57-62, ⟨10.1109/IOLTS.2007.16⟩. ⟨lirmm-00163244⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On-Line Self-Test of AES Hardware Implementations. DSN'07: Workshop on Dependable and Secure Nanocomputing, Jun 2007, Edinburgh, United Kingdom. ⟨lirmm-00163405⟩
  • C. Beck, D. Mahboub, R. Nouicer, B. Djerroud, R.M. Freeman, et al.. Light charged particle emission in highly excited and deformed $^{59}$Cu di-nucleus. XXXIII International Winter Meeting on Nuclear Physics, Jan 1995, Bormio, Italy. pp.127-139. ⟨in2p3-00015252⟩

Poster communications17 documents

  • Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan chain encryption, a countermeasure against scan attacks. PHISIC: Practical Hardware Innovations in Security Implementation and Characterization, May 2018, Gardanne, France. Workshop on Practical Hardware Innovations in Security Implementation and Characterization, 2018, ⟨http://phisic2018.emse.fr⟩. ⟨lirmm-01882565v2⟩
  • Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan chain encryption in Test Standards. SURREALIST: SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices, May 2018, Bremen, Germany. Workshop on SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices, 2018, ⟨http://www.lirmm.fr/surrealist18/⟩. ⟨lirmm-01882578v2⟩
  • Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Sécurité des moyens de test des SoC. Journée thématique des GDR SoC² et Sécurité Informatique : Sécurité des SoC complexes hétérogènes – de la TEE au matériel, Sep 2018, Paris, France. 2018. ⟨lirmm-01882552⟩
  • Emanuele Valea, Mathieu da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, et al.. SECCS: SECure Context Saving for IoT Devices. Colloque du GDR SoC-SiP, Jun 2018, Paris, France. 12ème Colloque National du GDR SoC-SiP, 2018. ⟨hal-02042659⟩
  • Mathieu da Silva, Emanuele Valea, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Stream cipher-based scan encryption in test standards. Colloque du GDR SoC-SiP, Jun 2018, Paris, France. 12ème Colloque National du GDR SoC-SiP, 2018. ⟨lirmm-01867283⟩
  • Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan Chain Encryption for the Test, Diagnosis and Debug of Secure Circuits. SETS: South European Test Seminar, Mar 2017, Alpe d'Huez, France. 2017, ⟨http://tima.univ-grenoble-alpes.fr/conferences/sets/2017/⟩. ⟨lirmm-01892667⟩
  • Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Sécurisation des structures de test : étude comparative. Colloque du GDR SoC-SiP, Jun 2017, Bordeaux, France. 11ème Colloque National du GDR SoC-SiP, 2017. ⟨lirmm-01867279⟩
  • Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Detection and Prevention of Hardware Trojan through Logic Testing. TRUDEVICE, Nov 2016, Barcelona, Spain. 4th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, Manufacturing test of secure devices / Reverse engineering countermeasures / Other topics, pp.#33, 2016, Posters IV. ⟨https://trudevice2016.eel.upc.edu/⟩. ⟨lirmm-01430007⟩
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Giorgio Di Natale, et al.. Design of Bulk Built-In Current Sensors to Detect Single Event Effects and Laser-Induced Fault Injection Attempts. Joint MEDIAN–TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. 2014. ⟨emse-01099040⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre. tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital Circuits. DCIS'2012: XVII Conference on Design of Circuits and Integrated Systems, Nov 2012, avignon, France. pp.1, 2012, ⟨http://www.lirmm.fr/dcis2012/⟩. ⟨lirmm-00799892⟩
  • Rodolphe Giroudeau, Giorgio Di Natale, Marie-Lise Flottes, Florent Hernandez. Exact wafer matching process wafer to wafer inegration. 3D Integration Applications, 2012, Grenoble, France. Workshop on 3D Integration Applications, Technology, Architecture, Design, Automation, and Test, 2012. ⟨lirmm-00805059⟩
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Calibrating Bulk Built-in Current Sensors for Detecting Transient Faults. Colloque GDR SoC-SiP, 2012, Lyon, France. 2012, Colloque National du Groupement de Recherche System-On-Chip et System-In-Package. ⟨lirmm-00715126⟩
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Timing Issues of Transient Faults in Concurrent Error Detection Schemes. GdR SoC-SiP'2011: Colloque national du Groupement de Recherche System-On-Chip et System-In-Package, Lyon, France. http://www2.lirmm.fr/~w3mic/SOCSIP/, 2011, ⟨http://www2.lirmm.fr/~w3mic/SOCSIP/⟩. ⟨lirmm-00701798⟩
  • Alberto Bosio, Giorgio Di Natale. Parallel Test of Identical Cores Using Test Elevators in 3D Circuits. 3D-Test: First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, Texas, United States. pp.N/A, 2010, ⟨http://3dtest.tttc-events.org⟩. ⟨lirmm-00537857⟩
  • Philipp Öhler, Alberto Bosio, Giorgio Di Natale, Sybille Hellebrand. A Modular Memory BIST for Optimized Memory Repair. IEEE Computer Society. IOLTS: International On-Line Testing Symposium, Jul 2008, Rhodes, Greece. 14th International On-Line Testing and Robust System Design Symposium, pp.171-172, 2008, ⟨10.1109/IOLTS.2008.30⟩. ⟨lirmm-00363724⟩
  • Mohammad Hosseinabady, Mohammad Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, et al.. Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. IOLTS: International On-Line Testing Symposium, Jul 2007, Heraklion, Crete, Greece. 13th IEEE International Symposium on On-Line Testing and Robust System Design, pp.205-206, 2007, ⟨10.1109/IOLTS.2007.17⟩. ⟨lirmm-00163343⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Dependable Parallel Architecture for SBoxes. ReCoSoc'07: International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2007, Montpellier, France. pp.CD-ROM, 2007. ⟨lirmm-00163414⟩

Book sections3 documents

Directions of work or proceedings6 documents

  • David Atienza, Giorgio Di Natale, Laura Pozzi. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2017). DATE: Design, Automation and Test in Europe, Mar 2017, Lausanne, Switzerland. EDAA, 2017, ⟨https://www.date-conference.com⟩. ⟨lirmm-01499298⟩
  • Said Hamdioui, Maria Michael, Giorgio Di Natale, Haralampos-G. Stratigopoulos. Proceedings of IEEE European Test Symposium (ETS 2016). ETS: European Test Symposium, May 2016, Amsterdam, Netherlands. IEEE, 2016. ⟨lirmm-01499309⟩
  • Liviu Miclea, Said Hamdioui, Paolo Prinetto, Giorgio Di Natale. Proceedings of IEEE European Test Symposium (ETS). ETS: European Test Symposium, May 2015, Cluj Napoca, Romania. IEEE, 2015. ⟨lirmm-01499307⟩
  • Paolo Prinetto, Giorgio Di Natale. Proceedings of the 10th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. 2015, ⟨http://www.dtis2015.teiath.gr⟩. ⟨lirmm-01499305⟩
  • Aida Todri-Sanial, Giorgio Di Natale, Patrick Girard, Marc Belleville, Saraju P. Mohanty, et al.. Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015). Jul 2015, Montpellier, France. 2015, 978-1-4799-8718-4. ⟨www.isvlsi.org⟩. ⟨lirmm-01433587⟩
  • Patrick Girard, Sybille Hellebrand, Zabo Peng, Matteo Sonza Reorda, Giorgio Di Natale. Proceedings of IEEE European Test Symposium (ETS - 2013). May 2013, Avignon, France. IEEE, 2013, 978-1-4673-6375-4. ⟨http://www.ieee-ets.org/past_events/ets13/⟩. ⟨lirmm-01433571⟩

Other publications5 documents

  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Rapport Technique intermédiaire, Contrat TOETS CT 302, Programme CEE CATRENE. 2011. 〈lirmm-00679018〉
  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Rapport Technique de fin d'année, Contrat TOETS CT 302, Programme CEE CATRENE. 2011. 〈lirmm-00679022〉
  • Patrick Girard, Florence Azaïs, Serge Bernard, Alberto Bosio, Luigi Dilillo, et al.. TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année. 2010. ⟨lirmm-00461745⟩
  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Contrat TOETS CT 302 - Programme CEE CATRENE (Rapport Intermédiaire). 2010. ⟨lirmm-00504873⟩
  • Marion Doulcier, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Test and Harware Security. 2008. ⟨lirmm-00365276⟩

Reports1 document

  • Nadia El Mrabet, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Jean-Claude Bajard. Differential Power Analysis against the Miller Algorithm. RR-08021, 2008. ⟨lirmm-00323684⟩

Habilitation à diriger des recherches1 document

  • Giorgio Di Natale. Conception et test des circuits et systèmes numériques à haute fiabilité et sécurité. Micro and nanotechnologies/Microelectronics. Université de Montpellier II, 2014. ⟨tel-01276281⟩