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Number of documents

28

Mes publis


Journal articles4 documents

  • Ville Yli-Mayry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, et al.. Diffusional Side-channel Leakage from Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Transactions on Information Forensics and Security, Institute of Electrical and Electronics Engineers, 2020, pp.1-1. ⟨10.1109/TIFS.2020.3033441⟩. ⟨hal-02977542⟩
  • Xuan-Thuy Ngo, Jean-Luc Danger, Sylvain Guilley, Tarik Graba, Yves Mathieu, et al.. Cryptographically Secure Shield for Security IPs Protection. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2017, 66 (2). ⟨hal-02287686⟩
  • Loic de Pontual, Yves Mathieu, Christelle Golzio, Marlène Rio, Valérie Malan, et al.. Mutational, functional, and expression studies of the TCF4 gene in Pitt-Hopkins syndrome. Human Mutation, Wiley, 2009, 30 (4), pp.669-676. ⟨10.1002/humu.20935⟩. ⟨hal-02134020⟩
  • Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu. Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors. IEEE Design & Test of Computers, Institute of Electrical and Electronics Engineers, 2007, 24 (6), pp.546-555. ⟨10.1109/MDT.2007.202⟩. ⟨hal-02893104⟩

Conference papers20 documents

  • Sofiane Takarabt, Sylvain Guilley, Youssef Souissi, Laurent Sauvage, Yves Mathieu, et al.. Formal Evaluation and Construction of Glitch-resistant Masked Functions. HOST, Dec 2021, Virtual, United States. ⟨hal-03365025⟩
  • Laurent Sauvage, Sofiane Takarabt, Youssef Souissi, Sylvain Guilley, Yves Mathieu. Detection of Side-channel Lleakage Through Glitches Using an Automated Tool. International Conference on Defense Systems: Architectures and Technologies (DAT’2020), Apr 2020, Constantine, Algeria. ⟨hal-02951758⟩
  • Sofiane Takarabt, Kais Chibani, Youssef Souissi, Laurent Sauvage, Sylvain Guilley, et al.. Pre-Silicon Embedded System Evaluation as new EDA for Security Verification. International Verification and Security Workshop (IVSW), Jun 2018, Platja d’Aro, Spain. ⟨hal-02287930⟩
  • Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, et al.. Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. 2018 21st Euromicro Conference on Digital System Design (DSD), Aug 2018, Prague, Czech Republic. pp.508-515. ⟨hal-02271687⟩
  • Noriyuki Miura, Kohei Matsuda, Karol Myszkowski, Makoto Nagata, Shivam Bhasin, et al.. A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor. Symposium on VLSI Circuits, Jun 2017, Kyoto, Japan. pp.C266-C267. ⟨hal-02288491⟩
  • Jean-Luc Danger, Yves Mathieu, Thibault Porteboeuf. IC variability : Pros and cons for security blocks. TRUDEVICE, Mar 2015, Grenoble, France. ⟨hal-02412162⟩
  • Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger. Countering Early Propagation and Routing Imbalance of DPL. International Conference on IC Design and Technology (ICICDT), Jun 2015, Leuven, Belgium. ⟨10.1109/ICICDT.2015.7165897⟩. ⟨hal-02287122⟩
  • Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, et al.. Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1--4, ⟨10.1109/FPL.2014.6927422⟩. ⟨hal-01372613⟩
  • Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu. Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS, Mar 2014, Dresden, Germany. ⟨10.1145/2559627.2559628⟩. ⟨hal-02412041⟩
  • Jean-Michel Cioranesco, Jean-Luc Danger, Tarik Graba, Sylvain Guilley, Yves Mathieu, et al.. Cryptographically secure shields. HOST 2014 - IEEE International Symposium on Hardware-Oriented Security and Trust, May 2014, Washington, United States. pp.25 - 31, ⟨10.1109/HST.2014.6855563⟩. ⟨hal-01110463⟩
  • Molka Ben Romdhane, Jean-Luc Danger, Tarik Graba, Yves Mathieu. Design Methodology of an ASIC TRNG based on an open-loop delay chain. NEWCAS, Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573654⟩. ⟨hal-02411986⟩
  • Mariem Slimani, Philippe Matherat, Yves Mathieu. A Dual Threshold Voltage Technique for Glitch Minimization. 19th IEEE International Conference on Electronics, Circuits and Systems, Dec 2012, Séville, Spain. pp.444-447, ⟨10.1109/ICECS.2012.6463554⟩. ⟨hal-01166345⟩
  • Stéphane Mancini, Lionel Pierrefeu, Z. Larabi, Yves Mathieu. Calibrating a predictive cache emulator for SoC design. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2010, Anaheim, Californie, United States. pp.273-280, ⟨10.1109/AHS.2010.5546246⟩. ⟨hal-02278686⟩
  • Zahir Larabi, Yves Mathieu, Stéphane Mancini. High Efficiency Reconfigurable Cache for Image Processing. ERSA'2009, Jul 2009, Las Vegas USA, United States. pp.226-232. ⟨hal-00384989⟩
  • Zahir Larabi, Yves Mathieu, Stéphane Mancini. Efficient data access management for FPGA-Based image processing SoCs. 20th IEEE/IFIP International Symposium on Rapid System Prototyping (RSP\'2009), Jun 2009, Paris, France. pp.159-165. ⟨hal-00368532v2⟩
  • Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar. Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.. Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., Apr 2009, NICE, France. pp.640-645. ⟨hal-00325417v3⟩
  • Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, et al.. Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig, Dec 2009, Cancún, Mexico. pp.213 - 218, ⟨10.1109/ReConFig.2009.50⟩. ⟨hal-00411843v3⟩
  • Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu. Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. Secure System Integration and Reliability Improvement, Jul 2008, Yokohama, Japan. pp.16-23, ⟨10.1109/SSIRI.2008.31⟩. ⟨hal-00259153v5⟩
  • Sylvain Guilley, Florent Flament, Yves Mathieu, Renaud Pacalet. Security Evaluation of a Balanced Quasi-Delay Insensitive Library (SecLib). Conference on Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. 6 p., ISBN: 978-2-84813-124-5. ⟨hal-00283405v5⟩
  • Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet. The “Backend Duplication” Method: A Leakage-Proof Place-and-Route Strategy for ASICs. Workshop on Cryptographic Hardware and Embedded Systems (CHES), Aug 2005, Edinburgh, United Kingdom. pp.383-397, ⟨10.1007/11545262_28⟩. ⟨hal-02893271⟩

Book sections2 documents

  • Kais Chibani, Adrien Facon, Sylvain Guilley, Damien Marion, Yves Mathieu, et al.. Fault Analysis Assisted by Simulation. Jakub Breier; Xiaolu Hou; Shivam Bhasin. Automated Methods in Cryptographic Fault Analysis, Springer International Publishing, pp.263-277, 2019, 978-3-030-11332-2. ⟨10.1007/978-3-030-11333-9_12⟩. ⟨hal-02915671⟩
  • J. Le Feuvre, Yves Mathieu. 23 : Graphics Composition for Multiview Displays. Emerging Technologies for 3D Video, Wiley, 2013. ⟨hal-02286558⟩

Preprints, Working Papers, ...2 documents

  • Sumanta Chaudhuri, Tarik Graba, Yves Mathieu. Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. 2019. ⟨hal-02287527⟩
  • Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar. Successful Attack on an FPGA-based Automatically Placed and Routed WDDL+ Crypto Processor.. 2008. ⟨hal-00339858⟩