Mots-clés

Nombre de documents

31

Vianney Lapotre


I received my M.Sc. and my Ph.D. in Electrical and Computer Engineering from the University of Bretagne-Sud, France, in 2010 and 2013 respectively. In 2012 I spent six months as an invited researcher at the Ruhr-University of Bochum, Germany. From 2013 to 2014, I was a Postdoctoral at LIRMM, Montpellier, France. I was involved in the European Mont-Blanc project. I am currently associate professor at University of Bretagne-Sud, France. My research interests include reconfigurable and self-adaptive multiprocessor architectures, NoC-based architectures, high performance embedded systems and system security.


Article dans une revue3 documents

Communication dans un congrès25 documents

  • Cyrielle Feron, Vianney Lapotre, Loïc Lagadec. PAnTHErS: A Prototyping and Analysis Tool for Homomorphic Encryption Schemes. 14th International Joint Conference on e-Business and Telecommunications, Jul 2017, Madrid, Spain. 〈hal-01595789〉
  • Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, et al.. ARMHEx: embedded security through hardware-enhanced information flow tracking. RESSI 2017 : Rendez-vous de la Recherche et de l'Enseignement de la Sécurité des Systèmes d'Information, May 2017, Grenoble (Autrans), France. 〈https://ressi2017.sciencesconf.org/〉. 〈hal-01558155〉
  • Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, et al.. ARMHEx: a framework for efficient DIFT in real-world SoCs. Field Programmable Logic (FPL), Sep 2017, Ghent, Belgium. 2017, 〈https://www.fpl2017.org/〉. 〈hal-01558475〉
  • Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, et al.. ARMHEx: A hardware extension for DIFT on ARM-based SoCs. Field Programmable Logic (FPL), Sep 2017, Ghent, Belgium. 2017, 〈https://www.fpl2017.org/〉. 〈hal-01558473〉
  • Maria Méndez Real, Migliore Vincent, Vianney Lapotre, Guy Gogniat. ALMOS many-core operating system extension with new secure-enable mechanisms for dynamic creation of secure zones. 24th Euromicro International Conference on Parallel, Distributed and Netwprk-Based Processing (PDP 2016), Feb 2016, Heraklion - Crete, Greece. 〈hal-01273173〉
  • Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, et al.. Towards a hardware-assisted information flow tracking ecosystem for ARM processors. 26th International Conference on Field-Programmable Logic and Applications (FPL 2016), Aug 2016, Lausanne, Switzerland. 2016, 〈http://www.fpl2016.org〉. 〈hal-01337579〉
  • Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, et al.. A portable approach for SoC-based Dynamic Information Flow Tracking implementations. 11ème Colloque du GDR SoC/SiP, Jun 2016, Nantes, France. 2016. 〈hal-01311045〉
  • Maria Méndez Real, Vincent Migliore, Vianney Lapotre, Guy Gogniat, Philipp Wehner, et al.. Dynamic Spatially Isolated Secure Zones for NoC-based Many-core Accelerators. 8th IEEE International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Jun 2016, Tallinn, Finland. 〈hal-01347175〉
  • Maria Méndez Real, Vincent Migliore, Vianney Lapotre, Guy Gogniat, Philipp Wehner, et al.. MPSoCSim extension: An OVP Simulator for the Evaluation of Cluster-based Multicore and Many-core architectures. 4rd Work­shop on Vir­tu­al Pro­to­typ­ing of Par­al­lel and Em­bed­ded Sys­tems (ViPES) as part of the In­ter­na­tio­nal Con­fe­rence on Em­bed­ded Com­pu­ter Sys­tems: Ar­chi­tec­tu­res, Mo­de­ling, and Si­mu­la­ti­on (SAMOS), Jul 2016, Samos, Greece. 〈hal-01347188〉
  • Anastasiia Butko, Rafael Garibotti, Luciano Ost, Chris Adeniyi-Jones, Vianney Lapotre, et al.. A trace-driven approach for fast and accurate simulation of manycore architectures. ASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2015, Chiba, Tokyo, Japan. 2015, 20th Asia and South Pacific Design Automation Conference. 〈10.1109/ASPDAC.2015.7059093〉. 〈lirmm-01255921〉
  • Vincent Migliore, Maria Méndez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, et al.. Exploration of Polynomial Multiplication Algorithms for Homomorphic Encryption Schemes. 2015 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2015), Dec 2015, Cancun, Mexico. 〈hal-01273192〉
  • Pascal Cotret, Guillaume Hiet, Guy Gogniat, Vianney Lapotre. HardBlare: an efficient hardware-assisted DIFC for non-modified embedded processors. CHES 2015 - Workshop on Cryptographic Hardware and Embedded Systems, Sep 2015, Saint-Malo, France. 2015. 〈hal-01252597〉
  • Charles Effiong, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial, et al.. On the Performance Exploration of 3D NoCs with Resistive-Open TSVs. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.579-584, 2015, 〈10.1109/ISVLSI.2015.49〉. 〈lirmm-01248588〉
  • Anelise Kologeski, Fernanda Lima Kastensmidt, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, et al.. Performance exploration of partially connected 3D NoCs under manufacturing variability. NEWCAS: International New Circuits and Systems Conference, Jun 2014, Trois-Rivieres, QC, Canada. IEEE, New Circuits and Systems Conference (NEWCAS), 2014 IEEE 12th International, pp.61-64, 2014, 〈10.1109/NEWCAS.2014.6933985〉. 〈lirmm-01248595〉
  • Vianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Nono Wouafo, Robin Danilo. Dynamic Branch Prediction For High-Level Synthesis. International Conference on Field Programmable Logic and Applications, Sep 2013, Portugal. pp.XX-YY, 2013. 〈hal-00830417〉
  • Vianney Lapotre, Purushotham Murugappa Velayuthan, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, et al.. A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP. ISVLSI 2013 : IEEE Computer Society Annual Symposium on VLSI, Aug 2013, Natal, Brazil. 2013. 〈hal-01002828〉
  • Vianney Lapotre, Hübner Michael, Guy Gogniat, Purushotham Murugappa Velayuthan, Amer Baghdadi, et al.. An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture. ReCoSoC 2013 : 8th IEEE International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Jul 2013, Darmstadt, Germany. 2013, 〈10.1109/ReCoSoC.2013.6581518〉. 〈hal-00873978〉
  • Vianney Lapotre, Purushotham Murugappa Velayuthan, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, et al.. Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder. ISCAS 2013 : IEEE International Symposium on Circuits and Systems, May 2013, Beijing, Chine. pp.493 - 496, 2013, 〈10.1109/ISCAS.2013.6571888〉. 〈hal-00873979〉
  • Vianney Lapotre, Purushotham Murugappa Velayuthan, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet. Plateforme multi-ASIP reconfigurable dynamiquement pour le turbo décodage dans un contexte multi-standard. GRETSI 2013 : 24ème colloque du Groupement de Recherche en Traitement du Signal et des Images, Sep 2013, Brest, France. 2013. 〈hal-00876009〉
  • Vianney Lapotre, Purushotham Murugappa Velayuthan, Guy Gogniat, Amer Baghdadi, Salim Haddad, et al.. Efficient dynamic configuration of a multi-ASIP turbo decoder. GDR SoC-SiP 2013 : Colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2013, Lyon, France. 〈hal-00876017〉
  • Vianney Lapotre, Purushotham Murugappa Velayuthan, Guy Gogniat, Amer Baghdadi, Michael Hubner, et al.. Stopping-free dynamic configuration of a multi-ASIP turbo decoder. DSD 2013 : 16th Euromicro Conference on Digital System Design, Sep 2013, Santander, Spain. pp.155 - 162, 2013, 〈10.1109/DSD.2013.24 〉. 〈hal-00876005〉
  • Purushotham Murugappa Velayuthan, Vianney Lapotre, Amer Baghdadi, Michel Jezequel. Rapid Design and Prototyping of a Reconfigurable Decoder Architecture for QC-LDPC Codes. RSP 2013 : 24th IEEE International Symposium on Rapid System Prototyping, Oct 2013, Montreal, Canada. 2013. 〈hal-00876088〉
  • Vianney Lapotre, Salim Haddad, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet. An analytical approach for sizing of heterogeneous multiprocessor flexible platform for iterative demapping and channel decoding. International Conference on ReConFigurable Computing and FPGAs (Reconfig), Dec 2012, Mexico. 2012. 〈hal-00747714〉
  • Vianney Lapotre, Guy Gogniat, Amer Baghdadi, Salim Haddad, Jean-Philippe Diguet, et al.. Management of reconfigurable multi-standards ASIP-based receiver. SOC-SIP : colloque national du groupe de recherches System On Chip - System In Package, Jun 2011, Lyon, France. 2011. 〈hal-00724998〉
  • Vianney Lapotre, Philippe Coussy, Cyrille Chavet. Prédiction de Branchement dans la Synthèse de Haut Niveau. SYMPosium en Architectures, Saint Malo, Mai 2011, May 2011, St Malo, France. pp.XX-YY, 2011. 〈hal-00592606〉

Poster2 documents

  • Mounir Nasr Allah, Guillaume Hiet, Muhammad Abdul Wahab, Pascal Cotret, Guy Gogniat, et al.. HardBlare: a Hardware-Assisted Approach for Dynamic Information Flow Tracking. Séminaire des doctorantes et doctorants en informatique de la Société Informatique de France, Apr 2016, Paris, France. 2016. 〈hal-01311032〉
  • Rafael Garibotti, Luciano Ost, Abdoulaye Gamatié, Vianney Lapotre, Chris Adeniyi-Jones, et al.. Multithreading for Compute Accelerators Through Distributed Shared Memory Design. DAC: Design Automation Conference, Jun 2014, San Francisco, United States. IEEE Design Automation Conference, 2014, Work-in-Progress Session. 〈lirmm-01419120〉

Thèse1 document

  • Vianney Lapotre. Toward dynamically reconfigurable high throughput multiprocessor Turbo decoder in a multimode and multi-standard context. Electronics. Université de Bretagne-Sud, 2013. English. 〈tel-01096975〉