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16 résultats
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Flexible Runtime Verification Based On Logical Clock ConstraintsFDL 2016 - Forum on specification & Design Languages, ECSI, Sep 2016, Bremen, Germany
Communication dans un congrès
hal-01421890v1
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TRAP: trace runtime analysis of propertiesFrontiers of Computer Science, 2020, 14 (3), pp.1-15. ⟨10.1007/s11704-018-7217-7⟩
Article dans une revue
hal-02402957v1
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Fast Dynamic Translation Using LLVM On Multi-Core Hosts5th Workshop on Architectural and Microarchitectural Support for Binary Translation (AMAS-BT), Intel Corporation, Jun 2012, Portland, Oregon, United States
Communication dans un congrès
hal-00777156v1
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SimSoC: A full system simulation software for embedded systems2009 International Workshop on Open-source Software for Scientific Computation (OSSC-2009), LIAMA, Institute of Automation, CAS, Beijing, China Guizhou Normal University, China, Sep 2009, Guiyang, China. 7 p
Communication dans un congrès
inria-00435247v1
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Towards Verified Faithful SimulationXuandong Li, Zhiming Liu, Wang Yi. Dependable Software Engineering: Theories, Tools, and Applications, 9409, Springer, pp.315, 2015, Lecture Notes in Computer Science, ISBN 978-3-319-25942-0. ⟨10.1007/978-3-319-25942-0⟩
Chapitre d'ouvrage
hal-01241837v1
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Towards Verified Faithful SimulationDependable Software Engineering: Theories, Tools, and Applications, Nov 2015, Nanjing, China
Communication dans un congrès
hal-01242963v1
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PSCV: A Runtime Verification Tool for Probabilistic SystemC Models CAV 2016 - 28th International Conference on Computer Aided Verification, Jul 2016, Toronto, Canada. pp.84 - 91, ⟨10.1007/978-3-319-41528-4_5⟩
Communication dans un congrès
hal-01406488v1
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SimSoC: A SystemC TLM integrated ISS for full system simulationAPCCAS - IEEE Asia-Pacific Conference on Circuits and Systems - 2008, IEEE, Nov 2008, Macau, Macau SAR China. ⟨10.1109/APCCAS.2008.4746381⟩
Communication dans un congrès
hal-00777158v1
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Automated Generation of Instruction Set Simulator from SpecificationInternational Conference on Computer Engineering (ICOCE 2014), Prof. Yulin Wang, Wuhan University, China Prof. Yulin Wang, Wuhan University, China and Prof. Sheng-Uei Guan, Xi'an Jiaotong-Liverpool University, China, Nov 2014, Shenzhen, China
Communication dans un congrès
hal-01081105v1
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Generation of Executable Representation for Processor Simulation with Dynamic Translation2008 International Conference on Computer Science and Software Engineering, Dec 2008, Wuhan, China. ⟨10.1109/CSSE.2008.635⟩
Communication dans un congrès
hal-00777157v1
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A Graphics Editor for Document PreparationACM SIGSMALL Symposium on Personal and Small Computers, SIGSMALL : ACM Special Interest Group on Small and Personal Computing Systems and Applications, 1983, San Diego, United States
Communication dans un congrès
inria-00350527v1
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Automated Generation of Instruction Set Simulator from Specification2014 International Conference on Computer Engineering (ICOCE 2014), SAISE, Nov 2014, Shenzhen, China
Communication dans un congrès
hal-01098899v1
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Fast approximately timed simulationWIT Transactions on Information and Communication Technologies, 2015, WIT Transactions on Information and Communication Technologies, 978-1-78466-054-3 (68), pp.756
Article dans une revue
hal-01081104v1
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Fast Instruction Set Simulation Using LLVM-based Dynamic TranslationInternational MultiConference of Engineers and Computer Scientists 2011, IAENG, Mar 2011, Hong Kong, China. pp.212-216
Communication dans un congrès
hal-00646947v1
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Designing a CPU model: from a pseudo-formal document to fast code3rd Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2011, Heraklion, Greece
Communication dans un congrès
inria-00546228v1
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TurboJ, a Java Bytecode-to-Native CompilerACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, 1998, Montreal, Canada
Communication dans un congrès
inria-00350525v1
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