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Number of documents

36

Tarik Graba (Télécom Paris)


Journal articles6 documents

  • Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, et al.. High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2020, 69 (4), pp.534-548. ⟨10.1109/TC.2019.2957355⟩. ⟨hal-02517649⟩
  • Xuan-Thuy Ngo, Jean-Luc Danger, Sylvain Guilley, Tarik Graba, Yves Mathieu, et al.. Cryptographically Secure Shield for Security IPs Protection. IEEE Transcation on Computers, 2017, 66 (2). ⟨hal-02287686⟩
  • Han Le Duc, D. M. Nguyen, Chadi Jabbour, Tarik Graba, Patricia Desgreys, et al.. All-Digital Calibration of Timing Skews for TIADCs Using The Polyphase Decomposition. IEEE Transactions on Circuits and Systems II, 2016, 63 (1), pp.99-103. ⟨hal-01271601⟩
  • Laurent Sauvage, Tarik Graba, Thibault Porteboeuf. Multi-Level Formal Analysis, A New Direction for Fault Injection Attack?. Journal of Cryptographic Engineering, 2016. ⟨hal-02287457⟩
  • Anthony Kolar, Andrea Pinna, Olivier Romain, Sylvain Viateur, Thomas Ea, et al.. A Multishutter Time Sensor for Multispectral Imaging in a 3D reconstruction integrated sensor. IEEE Sensors Journal, Institute of Electrical and Electronics Engineers, 2009, 9, pp.478-484. ⟨hal-01534262⟩
  • Anthony Kolar, Olivier Romain, Jad Ayoub, David Faura, Sylvain Viateur, et al.. A system for an accurate 3D reconstruction in video endoscopy capsule. EURASIP Journal on Embedded Systems, SpringerOpen, 2009, 2009, pp.716317. ⟨10.1155/2009/716317⟩. ⟨hal-01198848⟩

Conference papers28 documents

  • Etienne Tehrani, Tarik Graba, Abdelmalek Si Merabet, Sylvain Guilley, Jean-Luc Danger. Classification of Lightweight Block Ciphers for Specific Processor Accelerated Implementations. 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2019, Genoa, Italy. pp.747-750, ⟨10.1109/ICECS46596.2019.8965156⟩. ⟨hal-02517585⟩
  • Etienne Tehrani, Tarik Graba, Jean-Luc Danger. Acceleration of Lightweight Block Ciphers on Microprocessors. CryptArchi 2019, Jun 2019, Prague, Poland. ⟨hal-02271470⟩
  • Etienne Tehrani, Jean-Luc Danger, Tarik Graba. Generic Architecture for Lightweight Block Ciphers: A First Step Towards Agile Implementation of Multiple Ciphers. 12th IFIP International Conference on Information Security Theory and Practice (WISTP), Dec 2018, Brussels, Belgium. pp.28-43, ⟨10.1007/978-3-030-20074-9_4⟩. ⟨hal-02294599⟩
  • Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, et al.. Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. 2018 21st Euromicro Conference on Digital System Design (DSD), Aug 2018, Prague, Czech Republic. pp.508-515. ⟨hal-02271687⟩
  • Noriyuki Miura, Kohei Matsuda, Karol Myszkowski, Makoto Nagata, Shivam Bhasin, et al.. A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor. Symposium on VLSI Circuits, Jun 2017, Kyoto, Japan. pp.C266-C267. ⟨hal-02288491⟩
  • Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger. Countering Early Propagation and Routing Imbalance of DPL. International Conference on IC Design and Technology (ICICDT), Jun 2015, Leuven, Belgium. ⟨10.1109/ICICDT.2015.7165897⟩. ⟨hal-02287122⟩
  • Han Le Duc, D. M. Nguyen, Chadi Jabbour, Tarik Graba, Patricia Desgreys, et al.. Hardware Implementation of All Digital Calibration for Undersampling TIADCs. IEEE International Symposium on Circuits and Systems ISCAS2015, May 2015, Lisbon, Portugal. ⟨hal-02287188⟩
  • Jean-Michel Cioranesco, Jean-Luc Danger, Tarik Graba, Sylvain Guilley, Yves Mathieu, et al.. Cryptographically secure shields. HOST 2014 - IEEE International Symposium on Hardware-Oriented Security and Trust, May 2014, Washington, United States. pp.25 - 31, ⟨10.1109/HST.2014.6855563⟩. ⟨hal-01110463⟩
  • Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, et al.. Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1--4, ⟨10.1109/FPL.2014.6927422⟩. ⟨hal-01372613⟩
  • Taoufik Chouta, Tarik Graba, Jean-Luc Danger, Julien Bringer, Maël Berthier, et al.. Side channel analysis on an embedded hardware fingerprint biometric comparator & low cost countermeasures.. HASP, Jun 2014, Minneapolis, United States. ⟨10.1145/2611765.2611771⟩. ⟨hal-02412116⟩
  • Shivam Bhasin, Tarik Graba, Jean-Luc Danger, Zakaria Najm. A Look into SIMON from a Side-channel Perspective. HOST, May 2014, Washington DC, United States. ⟨10.1109/HST.2014.6855568⟩. ⟨hal-02412115⟩
  • Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu. Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS, Mar 2014, Dresden, Germany. ⟨10.1145/2559627.2559628⟩. ⟨hal-02412041⟩
  • Molka Ben Romdhane, Jean-Luc Danger, Tarik Graba, Yves Mathieu. Design Methodology of an ASIC TRNG based on an open-loop delay chain. NEWCAS, Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573654⟩. ⟨hal-02411986⟩
  • Florent Lozac'H, Molka Ben Romdhane, Tarik Graba, Jean-Luc Danger. FPGA design of an Open-Loop True Random Number Generator. 16th euromicro conference on digital system design, Sep 2013, Santander, Spain. pp.615-622, ⟨10.1109/DSD.2013.73⟩. ⟨hal-02412025⟩
  • Molka Ben Romdhane, Tarik Graba, Jean-Luc Danger. Stochastic model of a Metastability-based True Random Number Generator. TRUST, Jun 2013, Londres, United Kingdom. ⟨10.1007/978-3-642-38908-5_7⟩. ⟨hal-02412461⟩
  • Taoufik Chouta, Jean-Luc Danger, Laurent Sauvage, Tarik Graba. A Small and High-performance Coprocessor for Fingerprint Match-On-Card. DSD, Sep 2012, Cesme/Izmir, Turkey. ⟨10.1109/DSD.2012.14⟩. ⟨hal-02286419⟩
  • Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, et al.. Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig, Dec 2009, Cancún, Mexico. pp.213 - 218, ⟨10.1109/ReConFig.2009.50⟩. ⟨hal-00411843v3⟩
  • Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger. WDDL is Protected Against Setup Time Violation Attacks. CHES, Sep 2009, Lausanne, Switzerland. pp.73-83, ⟨10.1109/FDTC.2009.40⟩. ⟨hal-00410135⟩
  • Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Tarik Graba, Jean-Luc Danger, et al.. Shall we trust WDDL?. Future of Trust in Computing, Jun 2008, Berlin, Germany. pp.208-215, ⟨10.1007/978-3-8348-9324-6_22⟩. ⟨hal-00409024⟩
  • Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu. Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. Secure System Integration and Reliability Improvement, Jul 2008, Yokohama, Japan. pp.16-23, ⟨10.1109/SSIRI.2008.31⟩. ⟨hal-00259153v5⟩
  • Anthony Kolar, Tarik Graba, Andrea Pinna, Olivier Romain, Eric Belhaire, et al.. Smart Bi-Spectral Image Sensor for 3D Vision. IEEE Sensor, 2007, Unknown, Unknown Region. ⟨hal-01534347⟩
  • Anthony Kolar, Tarik Graba, Andrea Pinna, Olivier Romain, Thomas Ea, et al.. A multi shutter time sensor for multispectral imaging in a 3D Reconstruction embedded sensor. DCIS, 2007, Unknown, Unknown Region. ⟨hal-01534346⟩
  • Tarik Graba, David Faura, Sylvain Viateur, Olivier Romain, Bertrand Granado, et al.. Seuillage dynamique temps réel dans un système embarqué. Gretsi, 2007, Unknown, Unknown Region. ⟨hal-01534424⟩
  • Anthony Kolar, Tarik Graba, Andrea Pinna, Olivier Romain, Bertrand Granado. A digital processing architecture for 3D reconstruction. IEEE International Workshop on Computer Architecture for Machine Perception and Sensing (CAMPS2006), 2006, montreal, Canada. ⟨hal-01534350⟩
  • Anthony Kolar, Tarik Graba, Andrea Pinna, Olivier Romain, Bertrand Granado. An integrated digital architecture for the real-time reconstruction in a VSIP sensor. IEEE International Conference on Electronics, Circuits and Systems (ICECS 2006), 2006, Nice, France. ⟨hal-01534351⟩
  • Tarik Graba, Bertrand Granado, Olivier Romain, Thomas Ea, Andrea Pinna, et al.. Cyclope, une Architecture Pour la Vision Temps Réel en Relief. Journées Francophones Adéquation Algorithme Architecture, 2005, Unknown, Unknown Region. ⟨hal-01534426⟩
  • Tarik Graba, Bertrand Granado, Olivier Romain, Thomas Ea, Andrea Pinna, et al.. Reconstruction 3D temps réel dans un VSIP. Actes du 20 ième colloque GRETSI: Traitement du signal et des images, 2005, Unknown, Unknown Region. pp.819-822. ⟨hal-01534425⟩
  • Tarik Graba, Bertrand Granado, Olivier Romain, Thomas Ea, Andrea Pinna, et al.. Cyclope: an integrated real-time 3D image sensor. XIX Conference on design of circuits and integrated systems, 2004, Unknown, Unknown Region. ⟨hal-01534353⟩

Book sections1 document

  • Anthony Kolar, Olivier Romain, Tarik Graba, Thomas Ea, Bertrand Granado. Stereo Vision. http://intechweb.org/. Stereo Vision, 9 - The Integrated Active Stereoscopic Vision Theory, Integration and Application, I-tech, pp.131 - 152, 2008. ⟨hal-01534448⟩

Preprints, Working Papers, ...1 document

  • Sumanta Chaudhuri, Tarik Graba, Yves Mathieu. Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. 2019. ⟨hal-02287527⟩