Tarik Graba
Télécom Paris
41
Documents
Publications
Jitter Compensation Mechanism for Dynamic Deterministic NetworksOptical Fiber Communication Conference (OFC) 2023, Mar 2023, San Diego California, United States. pp.Th3D.2, ⟨10.1364/OFC.2023.Th3D.2⟩
Communication dans un congrès
hal-04426205v1
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RISC-V Extension for Lightweight Cryptography, Protection against SCAWorkshop on Practical Hardware Innovations in Security Implementation and Characterization (PHISIC 2022), May 2022, Gardanne, France
Communication dans un congrès
hal-03752972v1
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RSM Protection of the PRESENT Lightweight Cipher as a RISC-V Extension2021 24th Euromicro Conference on Digital System Design (DSD), Sep 2021, Palermo, Italy. pp.325-332, ⟨10.1109/DSD53832.2021.00056⟩
Communication dans un congrès
hal-03376955v1
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RISC-V Extension for Lightweight Cryptography2020 23rd Euromicro Conference on Digital System Design (DSD), Aug 2020, Kranj, Slovenia. pp.222-228, ⟨10.1109/DSD51259.2020.00045⟩
Communication dans un congrès
hal-02977544v1
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Classification of Lightweight Block Ciphers for Specific Processor Accelerated Implementations2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2019, Genoa, Italy. pp.747-750, ⟨10.1109/ICECS46596.2019.8965156⟩
Communication dans un congrès
hal-02517585v1
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Acceleration of Lightweight Block Ciphers on MicroprocessorsCryptArchi 2019, Jun 2019, Prague, Poland
Communication dans un congrès
hal-02271470v1
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Generic Architecture for Lightweight Block Ciphers: A First Step Towards Agile Implementation of Multiple Ciphers12th IFIP International Conference on Information Security Theory and Practice (WISTP), Dec 2018, Brussels, Belgium. pp.28-43, ⟨10.1007/978-3-030-20074-9_4⟩
Communication dans un congrès
hal-02294599v1
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Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology2018 21st Euromicro Conference on Digital System Design (DSD), Aug 2018, Prague, Czech Republic. pp.508-515
Communication dans un congrès
hal-02271687v1
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A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic ProcessorSymposium on VLSI Circuits, Jun 2017, Kyoto, Japan. pp.C266-C267
Communication dans un congrès
hal-02288491v1
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Hardware Implementation of All Digital Calibration for Undersampling TIADCsIEEE International Symposium on Circuits and Systems ISCAS2015, May 2015, Lisbon, Portugal
Communication dans un congrès
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Countering Early Propagation and Routing Imbalance of DPLInternational Conference on IC Design and Technology (ICICDT), Jun 2015, Leuven, Belgium. ⟨10.1109/ICICDT.2015.7165897⟩
Communication dans un congrès
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Cryptographically secure shieldsHOST 2014 - IEEE International Symposium on Hardware-Oriented Security and Trust, May 2014, Washington, United States. pp.25 - 31, ⟨10.1109/HST.2014.6855563⟩
Communication dans un congrès
hal-01110463v1
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A Look into SIMON from a Side-channel PerspectiveHOST, May 2014, Washington DC, United States. ⟨10.1109/HST.2014.6855568⟩
Communication dans un congrès
hal-02412115v1
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Side channel analysis on an embedded hardware fingerprint biometric comparator & low cost countermeasures.HASP, Jun 2014, Minneapolis, United States. ⟨10.1145/2611765.2611771⟩
Communication dans un congrès
hal-02412116v1
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Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation MethodologyES4CPS, Mar 2014, Dresden, Germany. ⟨10.1145/2559627.2559628⟩
Communication dans un congrès
hal-02412041v1
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Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical securityFPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1--4, ⟨10.1109/FPL.2014.6927422⟩
Communication dans un congrès
hal-01372613v1
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FPGA design of an Open-Loop True Random Number Generator16th euromicro conference on digital system design, Sep 2013, Santander, Spain. pp.615-622, ⟨10.1109/DSD.2013.73⟩
Communication dans un congrès
hal-02412025v1
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Design Methodology of an ASIC TRNG based on an open-loop delay chainNEWCAS, Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573654⟩
Communication dans un congrès
hal-02411986v1
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Stochastic model of a Metastability-based True Random Number GeneratorTRUST, Jun 2013, Londres, United Kingdom. ⟨10.1007/978-3-642-38908-5_7⟩
Communication dans un congrès
hal-02412461v1
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A Small and High-performance Coprocessor for Fingerprint Match-On-CardDSD, Sep 2012, Cesme/Izmir, Turkey. ⟨10.1109/DSD.2012.14⟩
Communication dans un congrès
hal-02286419v1
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Combined SCA and DFA Countermeasures Integrable in a FPGA Design FlowReConFig, Dec 2009, Cancún, Mexico. pp.213 - 218, ⟨10.1109/ReConFig.2009.50⟩
Communication dans un congrès
hal-00411843v3
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WDDL is Protected Against Setup Time Violation AttacksCHES, Sep 2009, Lausanne, Switzerland. pp.73-83, ⟨10.1109/FDTC.2009.40⟩
Communication dans un congrès
hal-00410135v1
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Shall we trust WDDL?Future of Trust in Computing, Jun 2008, Berlin, Germany. pp.208-215, ⟨10.1007/978-3-8348-9324-6_22⟩
Communication dans un congrès
hal-00409024v1
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Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAsSecure System Integration and Reliability Improvement, Jul 2008, Yokohama, Japan. pp.16-23, ⟨10.1109/SSIRI.2008.31⟩
Communication dans un congrès
hal-00259153v5
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Seuillage dynamique temps réel dans un système embarquéGretsi, 2007, Unknown, Unknown Region
Communication dans un congrès
hal-01534424v1
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Smart Bi-Spectral Image Sensor for 3D VisionIEEE Sensor, 2007, Unknown, Unknown Region
Communication dans un congrès
hal-01534347v1
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A multi shutter time sensor for multispectral imaging in a 3D Reconstruction embedded sensorDCIS, 2007, Unknown, Unknown Region
Communication dans un congrès
hal-01534346v1
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An integrated digital architecture for the real-time reconstruction in a VSIP sensorIEEE International Conference on Electronics, Circuits and Systems (ICECS 2006), 2006, Nice, France
Communication dans un congrès
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A digital processing architecture for 3D reconstructionIEEE International Workshop on Computer Architecture for Machine Perception and Sensing (CAMPS2006), 2006, montreal, Canada
Communication dans un congrès
hal-01534350v1
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Cyclope, une Architecture Pour la Vision Temps Réel en ReliefJournées Francophones Adéquation Algorithme Architecture, 2005, Unknown, Unknown Region
Communication dans un congrès
hal-01534426v1
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Reconstruction 3D temps réel dans un VSIPActes du 20 ième colloque GRETSI: Traitement du signal et des images, 2005, Unknown, Unknown Region. pp.819-822
Communication dans un congrès
hal-01534425v1
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Cyclope: an integrated real-time 3D image sensorXIX Conference on design of circuits and integrated systems, 2004, Unknown, Unknown Region
Communication dans un congrès
hal-01534353v1
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Stereo Visionhttp://intechweb.org/. Stereo Vision, 9 - The Integrated Active Stereoscopic Vision Theory, Integration and Application, I-tech, pp.131 - 152, 2008
Chapitre d'ouvrage
hal-01534448v1
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Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology2019
Pré-publication, Document de travail
hal-02287527v1
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