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74 résultats
A Complete Design-Flow for the Generation of Ultra Low-Power WSN Node Architectures Based on Micro-TaskingProc. of the 47th IEEE/ACM Design Automation Conference (DAC), Jun 2010, Anaheim, CA, USA, x-proceedings = yes, x-international-audience = yes, x-editorial-board = yes, x-in, United States. pp.693 - 698
Communication dans un congrès
inria-00554202v1
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Hybrid-JIT : Compilateur JIT Matériel/Logiciel pour les Processeurs VLIW EmbarquésConférence d’informatique en Parallélisme, Architecture et Système (Compas), Jul 2016, Lorient, France
Communication dans un congrès
hal-01345306v1
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Ultra low-power FSM for control oriented applicationsIEEE International Symposium on Circuits and Systems, 2009., May 2009, Taipe, Taiwan
Communication dans un congrès
inria-00453945v1
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Safe Overclocking for CNN Accelerators through Algorithm-Level Error DetectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39 (12), pp.4777 - 4790. ⟨10.1109/TCAD.2020.2981056⟩
Article dans une revue
hal-03094811v1
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Fine-Grain Iterative Compilation for WCET EstimationWCET 2018 - 18th International Workshop on Worst-Case Execution Time Analysis, Jul 2018, Barcelona, Spain. pp.1-12, ⟨10.4230/OASIcs.WCET.2018.9⟩
Communication dans un congrès
hal-01889944v1
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Design Exploration of RISC-V Soft-Cores through Speculative High-Level SynthesisFPT 2022 - International Conference on Field Programmable Technology, Dec 2022, Honk Kong / Hybrid, Hong Kong SAR China. pp.1-6, ⟨10.1109/ICFPT56656.2022.9974478⟩
Communication dans un congrès
hal-03828841v1
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Maximal Atomic irRedundant Sets: a Usage-based Dataflow Partitioning AlgorithmIMPACT 2023 - 13th International Workshop on Polyhedral Compilation Techniques, Jan 2023, Toulouse, France. pp.1-9
Communication dans un congrès
hal-04410835v1
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How to accelerate genomic sequence alignment 4X using half an FPGA2011
Autre publication scientifique
hal-00637833v1
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Efficient Nested Loop Pipelining in High Level Synthesis using Polyhedral Bubble InsertionIEEE International Conference on Field-Programmable Technology (FPT'11), Dec 2011, New Delhi, India. ⟨10.1109/FPT.2011.6132715⟩
Communication dans un congrès
hal-00746434v1
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Runtime dependency analysis for loop pipelining in High-Level Synthesis50th Design Automation Conference (DAC),, May 2013, Austin, United States
Communication dans un congrès
hal-00921416v1
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A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic ClustersJournal of Low Power Electronics, 2011, 7 (4), pp.482-489. ⟨10.1166/jolpe.2011.1159⟩
Article dans une revue
hal-00747721v1
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A Flexible Approach for Compiling Scilab to Reconfigurable Multi-Core Embedded SystemsInternational Workshop on Reconfigurable Communication-centric Systems-on-Chip, Jul 2012, york, United Kingdom. pp.1-8
Communication dans un congrès
hal-00752644v1
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System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design FlowACM Transactions on Design Automation of Electronic Systems, 2012, 17 (1), pp.2:1--2:24. ⟨10.1145/2071356.2071358⟩
Article dans une revue
hal-00752652v1
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Tightening contention delays while scheduling parallel applications on multi-core architecturesInternational Conference on Embedded Software (EMSOFT), 2017, Oct 2017, Seoul, South Korea. pp.20, ⟨10.1145/3126496⟩
Communication dans un congrès
hal-01590508v1
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Supporting Runtime Reconfigurable VLIWs Cores Through Dynamic Binary TranslationDATE 2018 - IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, Mar 2018, Dresden, Germany. pp.1009-1014, ⟨10.23919/DATE.2018.8342160⟩
Communication dans un congrès
hal-01653110v2
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Enabling Overclocking with HLS Tools through Algorithm-Level Error DetectionFPT 2018 - International Conference on Field-Programmable Technology, Dec 2018, Naha, Japan
Communication dans un congrès
hal-01942429v1
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Using Model Types to Support Contract-Aware Model Substitutability9th European Conference on Modelling Foundations and Applications (ECMFA 2013), Jul 2013, Montpellier, France. pp.118-133, ⟨10.1007/978-3-642-39013-5_9⟩
Communication dans un congrès
hal-00808770v1
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Accelerating HMMER on FPGA using Parallel Prefixes and ReductionsProc. of the IEEE International Conference on Field-Programmable Technology (FPT'10), Dec 2010, Beijing, China, China. x-proceedings = yes, x-international-audience = yes, x-editorial-board = yes, x-invited-conference
Communication dans un congrès
inria-00554191v1
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System-Level Synthesis for Ultra Low-Power Wireless Sensor NodesProc. of the 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), Sep 2010, Lille, France, France. pp.493 - 500
Communication dans un congrès
inria-00554204v1
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Combining execution pipelines to improve parallel implementation of HMMER on FPGAMicroprocessors and Microsystems: Embedded Hardware Design , 2015, 39, pp.457-470. ⟨10.1016/j.micpro.2015.06.006⟩
Article dans une revue
hal-01235328v1
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A high-level synthesis approach optimizing accumulations in floating-point programs using custom formats and operators2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Apr 2017, Napa, United States. pp.80-80, ⟨10.1109/FCCM.2017.41⟩
Communication dans un congrès
hal-01498357v2
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Hybrid-DBT: Hardware Accelerated Dynamic Binary TranslationRISC-V 2019 - Workshop Zurich, Jun 2019, Zurich, Switzerland. pp.1
Poster de conférence
hal-02155019v1
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Applied Reconfigurable Computing. Architectures, Tools, and ApplicationsARC 2021 - 17th International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications, 12700, Springer, pp.1-338, 2021, LNCS, 978-3-030-79025-7. ⟨10.1007/978-3-030-79025-7⟩
Proceedings/Recueil des communications
hal-03315772v1
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Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil ComputationsPACT 2023 - International Conference on Parallel Architectures and Compilation Techniques, Oct 2023, Vienna, Austria. pp.1-12
Communication dans un congrès
hal-04394874v2
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One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAsFPL - 27th International Conference on Field Programmable Logic and Applications, Sep 2017, Gand, Belgium. ⟨10.23919/FPL.2017.8056781⟩
Communication dans un congrès
hal-01655590v1
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Application-specific arithmetic in high-level synthesis toolsACM Transactions on Architecture and Code Optimization, 2020, ⟨10.1145/3377403⟩
Article dans une revue
hal-02423363v3
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Toward Speculative Loop Pipelining for High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39 (11), pp.4229 - 4239. ⟨10.1109/TCAD.2020.3012866⟩
Article dans une revue
hal-02949516v1
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Component-Level Datapath Merging in System-Level Design of Wireless Sensor Node Controllers for FPGA-Based ImplementationsEuromicro Conference on Digital System Design (DSD), Sep 2013, Santander, Spain. pp.543-550, ⟨10.1109/DSD.2013.64⟩
Communication dans un congrès
hal-00921421v1
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Derivation of Efficient FSM from Loop NestsInternational Conference on Field-Programmable Technology (ICFPT), Dec 2013, Kyoto, Japan
Communication dans un congrès
hal-00921446v1
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HLS Tools for FPGA : faster development with better performancesProceeding of the 7th International Symposium on Applied Reconfigurable Computing, Feb 2011, Belfast, United Kingdom. pp.67-78
Communication dans un congrès
hal-00637830v1
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