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17 résultats
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Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIWIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, pp.1-14. ⟨10.1109/TCAD.2018.2864288⟩
Article dans une revue
hal-01856163v1
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GhostBusters: Mitigating Spectre Attacks on a DBT-Based ProcessorDATE 2020 - 23rd IEEE/ACM Design, Automation and Test in Europe, Mar 2020, Grenoble, France. pp.1-6
Communication dans un congrès
hal-02396631v1
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Comet: a RISC-V Core Synthesized from C++ SpecificationsSpring 2022 RISC-V Week, May 2022, Paris, France
Poster de conférence
hal-03885663v1
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Supporting Runtime Reconfigurable VLIWs Cores Through Dynamic Binary TranslationDATE 2018 - IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, Mar 2018, Dresden, Germany. pp.1009-1014, ⟨10.23919/DATE.2018.8342160⟩
Communication dans un congrès
hal-01653110v2
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SmolPhone: a smartphone with energy limitsIGSC 2023 - 14th International Green and Sustainable Computing, C. Mani Krishna; Michele Magno, Oct 2023, Toronto, Canada. pp.4
Communication dans un congrès
hal-04156447v3
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Hybrid-DBT: Hardware Accelerated Dynamic Binary TranslationRISC-V 2019 - Workshop Zurich, Jun 2019, Zurich, Switzerland. pp.1
Poster de conférence
hal-02155019v1
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Hybrid Obfuscation to Protect against Disclosure Attacks on Embedded MicroprocessorsIEEE Transactions on Computers, 2017
Article dans une revue
hal-01426565v1
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Hybrid-JIT : Compilateur JIT Matériel/Logiciel pour les Processeurs VLIW EmbarquésConférence d’informatique en Parallélisme, Architecture et Système (Compas), Jul 2016, Lorient, France
Communication dans un congrès
hal-01345306v1
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Attack detection through monitoring of timing deviations in embedded real-time systemsECRTS 2020 - 32nd Euromicro Conference on Real-Time Systems, Jul 2020, Modena, Italy. pp.1-22, ⟨10.4230/LIPIcs.ECRTS.2020.8⟩
Communication dans un congrès
hal-02559549v1
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Design Exploration of RISC-V Soft-Cores through Speculative High-Level SynthesisFPT 2022 - International Conference on Field Programmable Technology, Dec 2022, Honk Kong / Hybrid, Hong Kong SAR China. pp.1-6, ⟨10.1109/ICFPT56656.2022.9974478⟩
Communication dans un congrès
hal-03828841v1
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Toward Speculative Loop Pipelining for High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39 (11), pp.4229 - 4239. ⟨10.1109/TCAD.2020.3012866⟩
Article dans une revue
hal-02949516v1
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What You Simulate Is What You Synthesize: Designing a Processor Core from C++ SpecificationsICCAD 2019 - 38th IEEE/ACM International Conference on Computer-Aided Design, Nov 2019, Westminster, CO, United States. pp.1-8
Communication dans un congrès
hal-02303453v1
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SpecHLS: Speculative Accelerator Design using High-Level SynthesisIEEE Micro, In press, pp.1-10. ⟨10.1109/mm.2022.3188136⟩
Article dans une revue
hal-03714101v1
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Hardware-Accelerated Dynamic Binary TranslationIEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2017, Lausanne, Switzerland
Communication dans un congrès
hal-01423639v1
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What You Simulate Is What You Synthesize: Design of a RISC-V Core from C++ SpecificationsRISC-V Workshop 2019, Jun 2019, Zurich, Switzerland. pp.1-2
Communication dans un congrès
hal-02394911v1
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Aggressive Memory Speculation in HW/SW Co-Designed MachinesDATE 2019 - 22nd IEEE/ACM Design, Automation and Test in Europe, Mar 2019, Florence, Italy. pp.332-335, ⟨10.23919/DATE.2019.8715010⟩
Communication dans un congrès
hal-01941876v1
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RT-DFI: Optimizing Data-Flow Integrity for Real-Time SystemsECRTS 2022 - 34th Euromicro Conference on Real-Time Systems, Jul 2022, Modène, Italy. pp.1-24, ⟨10.4230/LIPIcs.ECRTS.2022.18⟩
Communication dans un congrès
hal-03641576v1
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