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Serge Weber
4%
Libre accès
46
Documents
Identifiants chercheurs
serge-webe-
0000-0002-7851-9916
- IdRef : 031823343
Présentation
Publications
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Scalable, dynamic and growing hardware self-organizing architecture for real-time vector quantization2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2020, Glasgow, France. pp.1-4, ⟨10.1109/ICECS49266.2020.9294921⟩
Communication dans un congrès
hal-03938456v1
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High performance scalable hardware SOM architecture for real-time vector quantization2018 IEEE International Conference on Image Processing, Applications and Systems (IPAS), Dec 2018, Sophia Antipolis, France. ⟨10.1109/IPAS.2018.8708863⟩
Communication dans un congrès
hal-03982206v1
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Systemc model of a MPEG-2 DVB-T bit-rate measurement architecture for FPGA implementationProceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004., Jun 2013, Geneva, Italy. pp.157-163, ⟨10.1109/IWRSP.2004.1311111⟩
Communication dans un congrès
hal-03938768v1
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Methodology and reconfigurable architecture for effective placement of variable-size hardware tasks2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2013, Torino, Italy. pp.156-163, ⟨10.1109/AHS.2013.6604240⟩
Communication dans un congrès
hal-03983256v1
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Methodology and reconfigurable architecture for effective placement of variable-size hardware tasksAHS 2013 NASA/ESA Conference on Adaptive Hardware and Systems, Jun 2013, Turin, Italy. pp.156-163, ⟨10.1109/AHS.2013.6604240⟩
Communication dans un congrès
hal-01397753v1
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Partially reconfigurable entropy encoder for multi standards video adaptation2011 IEEE 15th International Symposium on Consumer Electronics - (ISCE 2011), Jun 2011, Singapore, Singapore. pp.492-496, ⟨10.1109/ISCE.2011.5973879⟩
Communication dans un congrès
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Efficient reconfigurable entropy coder for embedded multi-standards video adaptation2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops (CVPR Workshops), Jun 2011, Colorado Springs, United States. pp.144-149, ⟨10.1109/CVPRW.2011.5981836⟩
Communication dans un congrès
hal-02337960v1
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Efficient reconfigurable entropy coder for embedded multi-standards video adaptationComputer Vision and Pattern Recognition Workshops (CVPRW), 2011 IEEE Computer Society Conference, Jun 2011, Colorado Springs, United States. pp.144 - 149, ⟨10.1109/CVPRW.2011.5981836⟩
Communication dans un congrès
hal-00649155v1
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Partially reconfigurable entropy encoder for multi standards video adaptationConsumer Electronics (ISCE), 2011 IEEE 15th International Symposium on Consumer Electronics, Jun 2011, Singapour, Singapore. pp.492 - 496, ⟨10.1109/ISCE.2011.5973879⟩
Communication dans un congrès
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An efficient VLSI implementation of H.264/AVC intra-frame transcoder2011 18th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2011), Dec 2011, Beirut, Lebanon. pp.1-4, ⟨10.1109/ICECS.2011.6122199⟩
Communication dans un congrès
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FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding2009 IEEE International SOC Conference (SOCC 2009), Sep 2009, Belfast, United Kingdom. pp.423-426, ⟨10.1109/SOCCON.2009.5398004⟩
Communication dans un congrès
hal-03983465v1
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Transrating by frequencies selectivity for H.264/AVC intra pictures2009 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting (BMSB), May 2009, Bilbao, Spain. pp.1-7, ⟨10.1109/ISBMSB.2009.5133730⟩
Communication dans un congrès
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TOSCANE: TOwards SCalable audiovisual communication networks2009 Global Information Infrastructure Symposium (GIIS), Jun 2009, Hammemet, Tunisia. pp.1-6, ⟨10.1109/GIIS.2009.5307043⟩
Communication dans un congrès
hal-03983467v1
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Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), Jan 2008, Hong Kong, China. pp.153-157, ⟨10.1109/DELTA.2008.122⟩
Communication dans un congrès
hal-03983596v1
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An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip2008 IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France. pp.499-502, ⟨10.1109/ISVLSI.2008.79⟩
Communication dans un congrès
hal-03983481v1
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Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), Jan 2008, Hong Kong, France. ⟨10.1109/delta.2008.122⟩
Communication dans un congrès
hal-01874048v1
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An Efficient Implementation of Scalable Architecture for Discrete Wavelet Transform On FPGA2007 6th IEEE Dallas Circuits and Systems Workshop on System-on-Chip, Nov 2007, Dallas, United States. pp.1-3, ⟨10.1109/DCAS.2007.4433206⟩
Communication dans un congrès
hal-03983621v1
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Cluster-Based Hybrid Reconfigurable Architecture for Auto-adaptive SoC2007 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS '07), Dec 2007, Marrakech, France. pp.979-982, ⟨10.1109/ICECS.2007.4511156⟩
Communication dans un congrès
hal-03938689v1
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Cluster-Based Hybrid Reconfigurable Architecture for Auto-adaptive SoC2007 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS '07), Dec 2007, Marrakech, Morocco. pp.979-982, ⟨10.1109/ICECS.2007.4511156⟩
Communication dans un congrès
hal-03983599v1
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Auto-adaptive reconfigurable architecture for scalable multimedia applications2007 2nd NASA/ESA Conference on Adaptive Hardware and Systems, Aug 2007, Edinburgh, France. pp.139-145, ⟨10.1109/AHS.2007.34⟩
Communication dans un congrès
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Implementation materielle d'un decodeur conceptuel pour l'analyse video MPEG-2 temps reelCanadian Conference on Electrical and Computer Engineering, 2005., May 2005, Saskatoon, Canada. pp.1743-1746, ⟨10.1109/CCECE.2005.1557320⟩
Communication dans un congrès
hal-03983649v1
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Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysisInternational Conference on Field Programmable Logic and Applications, 2005., Aug 2005, Tampere, Finland. pp.386-390, ⟨10.1109/FPL.2005.1515752⟩
Communication dans un congrès
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Proof-based design of a microelectronic architecture for MPEG-2 bit-rate measurementForum on specification and Design Languages - FDL'03, 2003, Frankfurt, Germany, France. 12 p
Communication dans un congrès
inria-00099834v1
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Proof-based design of a microelectronic architecture for mpeg-2 bit-rate measurementForum on specification and Design Languages-FDL'03, Sep 2003, Frankfurt, Germany
Communication dans un congrès
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Design and implementation of a Smart Strain Gage Conditioner2003 IEEE International Workshop on Computer Architectures for Machine Perception, May 2003, New Orleans, United States. pp.184-192, ⟨10.1109/CAMP.2003.1598163⟩
Communication dans un congrès
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Large-scale distributed and scalable SOM-based architecture for high-dimensional data reductionMuhammad Zeeshan Shakir; Naeem Ramzan. AI for Emerging Verticals: Human-robot computing, sensing and networking, Institution of Engineering and Technology, pp.315-336, 2020, 9781785619823. ⟨10.1049/pbpc034e_ch16⟩
Chapitre d'ouvrage
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FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-TField Programmable Logic and Application, 3203, Springer Berlin Heidelberg, pp.1027-1031, 2004, Lecture Notes in Computer Science, 978-3-540-22989-6. ⟨10.1007/978-3-540-30117-2_120⟩
Chapitre d'ouvrage
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SOPC-based Embedded Smart Strain Gage SensorField-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, 2438, Springer Berlin Heidelberg, pp.1131-1134, 2002, Lecture Notes in Computer Science, 978-3-540-44108-3. ⟨10.1007/3-540-46117-5_124⟩
Chapitre d'ouvrage
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DEVICE FOR MEASURING PARAMETERS RELATING TO PROGRAM CLOCK REFERENCES ESPECIALLY IN STREAMS, AND FREQUENCY SYNTHESISERFrance, Patent n° : WO2007/090858. 2007
Brevet
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