Sébastien Bilavarn
66
Documents
Publications
Synaptic Activity and Hardware Footprint of Spiking Neural Networks in Digital Neuromorphic SystemsACM Transactions on Embedded Computing Systems (TECS), 2022, 37 (4), pp.26. ⟨10.1145/3520133⟩
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Efficiency analysis of Artificial vs Spiking Neural Networks on FPGAsJournal of Systems Architecture, 2022, pp.11 / SYSARC 102765. ⟨10.1016/j.sysarc.2022.102765⟩
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Energy efficient mapping on manycore with dynamic and partial reconfiguration: Application to a smart cameraInternational Journal of Circuit Theory and Applications, 2018, 46 (9), pp.1648-1662. ⟨10.1002/cta.2508⟩
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Efficiency modeling and exploration of 64-bit ARM compute nodes for exascaleMicroprocessors and Microsystems: Embedded Hardware Design , 2017, 53, pp.68 - 80. ⟨10.1016/j.micpro.2017.06.019⟩
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Power Modeling and Exploration of Dynamic and Partially Reconfigurable SystemsJournal of Low Power Electronics, 2016, 12 (3), pp.172-185. ⟨10.1166/jolpe.2016.1448⟩
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FoRTReSS: a flow for design space exploration of partially reconfigurable systemsDesign Automation for Embedded Systems, 2015, 19 (3), pp.301-326. ⟨10.1007/s10617-015-9160-2⟩
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Power Consumption Models for the Use of Dynamic and Partial ReconfigurationMicroprocessors and Microsystems: Embedded Hardware Design , 2014, 38 (8), pp.860-872. ⟨10.1016/j.micpro.2014.01.002⟩
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Effectiveness of Power Strategies for Video Applications: A Practical StudyJournal of Real-Time Image Processing, 2014, 12 (1), pp.123-132. ⟨10.1007/s11554-013-0394-6⟩
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Fast Prototyping H.264 Deblocking Filter Using ESL ToolsShaker-Verlag Transactions on Systems, Signals and Devices, 2013, 8 (3), pp.345-362. ⟨10.1109/SSD.2011.5767375⟩
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Exploitation of EDF scheduling in Wireless Sensor NetworksInternational Journal on Measurement Technologies and Instrumentation Engineering (IJMTIE), 2011, 1 (2), pp.14-27
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AADL Extension to Model Classical FPGA and FPGA Embedded within a SoCInternational Journal of Reconfigurable Computing, 2011, Article ID 425401, 15 p. ⟨10.1155/2011/425401⟩
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Implantation d'un décodeur H.264 sur plateforme multiprocesseur avec gestion énergétiqueRevue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, 2010, 29/2, pp.201-224
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UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs)The Journal of Object Technology, 2009, 8 (1), pp.135-157
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UML for Modelling and Performance Estimation of Embedded SystemsThe Journal of Object Technology, 2009, 8 (2), pp.95-118
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Rewriting logic semantics for SystemC schedulerInternational Review on Computers and Software (IRECOS), 2009
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EPICURE: A partitioning and co-design framework for reconfigurable computingMicroprocessors and Microsystems: Embedded Hardware Design , 2006, 30, pp.367-387. ⟨10.1016/j.micpro.2006.02.015⟩
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Design space pruning through early estimations of area / delay trade-offs for FPGA implementationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25, N° 10, p. 1950-1968
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Processor Enhancements for Media Streaming ApplicationsJournal of VLSI Signal Processing Systems, 2005, 41 (2), pp.225-234
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Control Enhancement of Traction Electric Drives Using Neural Network Predictive ControllerInternational Conference on Control, Automatisation and Diagnosis 2024 ( ICCAD 24), IEEE, May 2024, Paris, France
Communication dans un congrès
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Improving the Energy Efficiency of CNN Inference on FPGA using Partial ReconfigurationDesign and Architectures for Signal and Image Processing (DASIP 2024), Jan 2024, Munich, Germany. pp.1-12
Communication dans un congrès
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An FPGA-based Hybrid Neural Network accelerator for embedded satellite image classificationIEEE International Symposium on Circuit and Systems (ISCAS 2020), May 2020, Seville, Spain. pp.5, ⟨10.1109/ISCAS45731.2020.9180625⟩
Communication dans un congrès
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Efficiency Modeling and Analysis of 64-bit ARM Clusters for HPCEuromicro Conference on Digital System Design (DSD), Aug 2016, Limassol, Cyprus. pp.342-347, ⟨10.1109/DSD.2016.74⟩
Communication dans un congrès
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HLS and manual design methodology for H.264/AVC deblocking filter2015 World Congress on Information Technology and Computer Applications Congress (WCITCA), Jun 2015, Hammamet, France. ⟨10.1109/WCITCA.2015.7367060⟩
Communication dans un congrès
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An Energy-Aware Scheduler for Dynamically Reconfigurable Multi-Core Systems6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2015, Jun 2015, Bremen, Germany. pp.1-6, ⟨10.1109/ReCoSoC.2015.7238084⟩
Communication dans un congrès
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HLS based design of a mixed architecture for H.264/AVC CAVLD12th International Multi-Conference on Systems, Signals and Devices Program, SSD 2015, Mar 2015, Mahdia, Tunisia. pp.1-4, ⟨10.1109/SSD.2015.7348095⟩
Communication dans un congrès
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Energy Analysis of a Real-Time Multiprocessor Control of Idle States on ARM platforms3rd International Conference on Pervasive and Embedded Computing and Communication Systems (PECCS 2013), Feb 2013, Barcelone, Spain. Session Mobile and Pervasive Computing. Paper 39
Communication dans un congrès
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Power Consumption Model for Partial Dynamic ReconfigurationInternational Conference on ReConFigurable Computing and FPGA (RECONFIG'2012), Dec 2012, Cancun, Mexico. pp.1-8, ⟨10.1109/ReConFig.2012.6416772⟩
Communication dans un congrès
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Impact of Operating Points on DVFS Power Management7th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS'12), May 2012, Gammarth, Tunisia. pp.1-6
Communication dans un congrès
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Energy Analysis of a DVFS Power Strategy on ARM platformsIEEE Faible Tension Faible Consommation (FTFC 2012), Jun 2012, Paris, France. pp.1-4
Communication dans un congrès
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Open-People: Open Power and Energy Optimization PLatform and EstimatorDSD 2012 - 15th Euromicro Conference on Digital System Design, Sep 2012, Çeşme, Izmir, Turkey. pp.668-675, ⟨10.1109/DSD.2012.98⟩
Communication dans un congrès
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Exploitation of power management techniquesWorkshop on Ultra-Low Power Sensor Networks (WUPS), co-located with Int. Conf. on Architecture of Computing Systems (ARCS), Feb 2011, Como, Italy
Communication dans un congrès
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Towards a power and energy efficient use of partial dynamic reconfigurationReconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Workshop, Jun 2011, Montpellier, France. ⟨10.1109/ReCoSoC.2011.5981540⟩
Communication dans un congrès
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FPGA modeling for SoC design explorationHEART (International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies, Imperial college, Jun 2011, London, United Kingdom
Communication dans un congrès
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Parallelism Level Impact on Energy Consumption in Reconfigurable DevicesHEART (International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies), Imperial college, Jun 2011, London, United Kingdom. pp.104-105
Communication dans un congrès
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Open-People: Open-Power and Energy Optimization Platform and EstimatorForum SAME 2011 - Sophia Antipolis Microelectronics, Oct 2011, Sophia Antipolis, France
Communication dans un congrès
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Embedded Operating Systems Energy OverheadInternational Conference on Design & Architectures for Signal & Image Processing (DASIP), Nov 2011, Tampere, Finland. pp.Session "Low Power Design & Methodologies"
Communication dans un congrès
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Fast Prototyping H.264 Deblocking filter using ESL tools8th International Multi-Conference on Systems, Signals & Devices (SSD'11), Conference on Communication & Signal Processing, Mar 2011, Sousse, Tunisia. ⟨10.1109/SSD.2011.5767375⟩
Communication dans un congrès
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A Video Monitoring Application for Wireless Sensor Networks using IEEE 802.15.42nd Work shop on Ultra-Low Power Sensor Networks, (WUPS 2011), Feb 2011, Como, Italy
Communication dans un congrès
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Towards a Power and energy Efficient Use of Partial Dynamic ReconfigurationColloque GDR SoC/SiP (System On Chip - System In Package), Jun 2011, Lyon, France
Communication dans un congrès
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EDF scheduler technique for wireless sensor networks: case study4th International Conference on Sensing Technology (ICST 2010), Jun 2010, Lecce, Italy. Session Wireless Sensors Network II, Paper 093
Communication dans un congrès
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Power consumption modeling for DVFS exploitation13th Euromicro Conference on Digital System Design, DSD 2010, Sep 2010, Lille, France
Communication dans un congrès
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Power Consumption Modeling for DVFS Exploitation 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Sep 2010, Lille, France. pp.579-586, ⟨10.1109/DSD.2010.55⟩
Communication dans un congrès
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Embedded Multicore Implementation of H.264 Decoder with Power Management ConsiderationsDSD 2008, Sep 2008, Parma, Italy
Communication dans un congrès
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Une Analyse de Performances et de Consommation du Décodage H.264 sur ARM MPCoreSympA'2008, Feb 2008, Fribourg, Switzerland. 08.pdf
Communication dans un congrès
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UML profile for Estimating Application Worst Case Execution Time on System-On-ChipSOC 2008, Nov 2008, Tampere, Netherlands
Communication dans un congrès
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Design Space Exploration for Rapid Development of DSP Applications5th International Conference on Information, Communications and Signal Processing, 2005, Bangkok, Thailand
Communication dans un congrès
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Fast system-level design of wireless applications8th Wireless Personal Multimedia Communications, 2005, Aalborg, Denmark
Communication dans un congrès
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Reconfigurable Coprocessor for Media StreamingJun 2004
Communication dans un congrès
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Fast Prototyping of Reconfigurable Architectures: An Estimation And Exploration Methodology from System-Level Specifications2003, pp.XX
Communication dans un congrès
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Fast Prototyping of Reconfigurable Architectures From a C Program2003, pp.XX
Communication dans un congrès
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Estimation de performances à un niveau comportemental pour l'implantation sur composants FPGAs7ème Symposium en Architectures Nouvelles de Machines, 2001, Paris, France
Communication dans un congrès
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FPGA area time power estimation for DSP applicationsInternational Conference on Signal Processing Applications and Technologies, 2000, Dallas, United States
Communication dans un congrès
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Méthode de conception d'architectures hétérogènes pour les applications de traitement numérique du signal3ème Journées Nationales du Réseau Doctoral de Microélectronique, 2000, Montpellier, France
Communication dans un congrès
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Area time power estimation for FPGA based designs at a behavioral levelIEEE International Conference on Electronics, Circuits and Systems, 2000, Beirut, Lebanon. ⟨10.1109/ICECS.2000.911593⟩
Communication dans un congrès
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Estimation d'architectures hétérogènes pour les applications de traitement numérique du signal2ème Colloque du GDR CAO de Circuits Int égrés et Syst èmes, 1999, Aix-en-Provence, France
Communication dans un congrès
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A hardware software co design methodology for heterogeneous architecture estimationInternational Conference on Signal Processing Applications and Technologies, 1999, Orlando, United States
Communication dans un congrès
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Enhancing FPGA-based CNN Inference Energy Efficiency through Partial ReconfigurationPoster de conférence hal-04135668v1 |
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Optimisation de l'efficacité énergétique pour l'IA embarquéePoster de conférence hal-04140688v1 |
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Linux Embarqué - Développement de pilotes périphériques13èmes journées pédagogiques du CNFM, Nov 2014, Saint-Malo, France. 2014
Poster de conférence
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Space Use-Case: Onboard Satellite Image Classificationspringer. Towards Ubiquitous, Low-power Image Processing Platforms, , pp.199-218, 2020, 978-3-030-53532-2. ⟨10.1007/978-3-030-53532-2_12⟩
Chapitre d'ouvrage
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Power models and strategies for multiprocessor platformsDesign Technology for Heterogeneous Embedded Systems, Edité par I. O'CONNOR, G. NICOLESCU, C. PIGUET, Springer, pp.411-436, 2011
Chapitre d'ouvrage
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Method for scheduling with deadline constraints, in particular in linux, carried out in user spaceFrance, Patent n° : International Application No PCT/IB2013/059916. MCSOC. 2014
Brevet
hal-01104569v1
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Power Modeling and Exploration of Dynamically Reconfigurable Multicore Designs2013
Pré-publication, Document de travail
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Hardware Acceleration of Real-Life Applications: from Theory to Implementation2012
Pré-publication, Document de travail
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Exploration Architecturale au Niveau Comportemental - Application aux FPGAsArchitectures Matérielles [cs.AR]. Université de Bretagne Sud (Lorient Vannes), 2002. Français. ⟨NNT : ⟩
Thèse
tel-01886615v1
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Modélisation, Conception Système d'Architectures Hétérogènes pour les Applications EmbarquéesArchitectures Matérielles [cs.AR]. Université de Nice Sophia-Antipolis (UNS), 2018
HDR
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