Nombre de documents

46

Publications de Roselyne CHOTIN-AVOT


Article dans une revue6 documents

  • Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations. Journal of Signal Processing Systems, Springer, 2016, pp.1-12. <10.1007/s11265-016-1104-y>. <hal-01259067>
  • Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. Low cost Solutions for Secure Remote Reconfiguration of FPGAs. International Journal of Embedded Systems, Inderscience, 2014, 6 (2-3), pp.257-265. <10.1504/ijes.2014.063824>. <hal-01017873>
  • Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. Authenticated Encryption on FPGAs from the Static Part to the Reconfigurable Part. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2014, 38 (6), pp.526-538. <10.1016/j.micpro.2014.03.006>. <hal-01017913>
  • Sophie Belloeil-Dupuis, Roselyne Chotin-Avot, Habib Mehrez. Exploring redundant arithmetics in computer-aided design of arithmetic datapaths. Integration, the VLSI Journal, Elsevier, 2013, 46 (2), pp.104-118. <10.1016/j.vlsi.2012.02.002>. <hal-01197289>
  • Zied Guitouni, Roselyne Chotin-Avot, Mohsen Machhout, Habib Mehrez, Rached Tourki. High Performances ASIC Based Elliptic Curve Cryptographic Processor over GF(2m). International Journal of Computer Applications, IJCA, 2011, Special Issue on Network Security and Cryptography (NSC) (4), pp.1-10. <10.5120/4342-039>. <hal-01197278>
  • Roselyne Chotin-Avot, Habib Mehrez. Hardware implementation of discrete stochastic arithmetic. Numerical Algorithms, Springer Verlag, 2004, 37 (1-4), pp.21-33. <10.1023/B:NUMA.0000049455.07441.ee>. <hal-01195967>

Communication dans un congrès38 documents

  • Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs. Cryptography and Security in Computing Systems, Jan 2016, Prague, Czech Republic. ACM, Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, pp.37-40, <10.1145/2858930.2858937>. <hal-01259069>
  • Umer Farooq, Roselyne Chotin-Avot, Moazam Azeem, Zouha Cherif, Maminionja Ravoson, et al.. Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration. Euromicro Conference on Digital System Design (DSD), Aug 2016, Limassol, Cyprus. IEEE, pp.641-645, <10.1109/DSD.2016.93>. <hal-01406787>
  • Umer Farooq, Roselyne Chotin-Avot, Moazzam Azeem, Maminionja Ravoson, Habib Mehrez. Inter-FPGA Routing Environment for Performance Exploration of Multi-FPGA Systems. Rapid System Prototyping (RSP), Oct 2016, Pittsburgh, United States. pp.1-6. <hal-01406803>
  • Jung Kyu Chae, Paul Mougeat, Jean-Arnaud François, Roselyne Chotin-Avot, Habib Mehrez. A reference-based specification tool for creating reliable library development specifications. 12th International New Circuits and Systems Conference, NEWCAS 2014, Jun 2014, Trois-Rivieres, QC, Canada. IEEE, pp.133-136, <10.1109/NEWCAS.2014.6934001>. <hal-01217236>
  • Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm. 10th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications, ARC 2014, Apr 2014, Vilamoura, Portugal. Springer, 8405, pp.13-24, Lecture Notes in Computer Science. <10.1007/978-3-319-05960-0_2>. <hal-01219833>
  • Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri. Impact of defect tolerance techniques on the criticality of a SRAM-based Mesh of Cluster FPGA. ReConFig 2014 - International Conference on ReConFigurable Computing and FPGAs, Dec 2014, Cancun, Mexico. IEEE, pp.1-6, 2014, <10.1109/ReConFig.2014.7032508>. <hal-01162066>
  • Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri. Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy. FPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. IEEE, pp.1-4, 2014, <10.1109/FPL.2014.6927389>. <hal-01162011>
  • Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, et al.. Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), Jul 2014, Tampa, FL, United States. IEEE, pp.553-558, <10.1109/ISVLSI.2014.66>. <hal-01400630>
  • Jung Kyu Chae, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez. A formalism of the specifications for library development. IEEE International System-on-Chip Conference, Sep 2013, Erlangen, Germany. IEEE, pp.307-312, 2014, <10.1109/SOCC.2013.6749706>. <hal-00953500>
  • Jung Kyu Chae, Severine Bertrand, Pierre-Francois Ollagnon, Paul Mougeat, Jean-Arnaud Francois, et al.. Efficient State-Dependent Power Model for Multi-bit Flip-Flop Banks. IEEE International Midwest Symposium on Circuits and Systems, Aug 2013, Columbus, United States. IEEE, pp.461-464, 2013, <10.1109/MWSCAS.2013.6674685>. <hal-00913885>
  • Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. Lightweight and Compact Solutions for Secure Reconfiguration of FPGAs. International Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. IEEE, pp.1-4, <10.1109/ReConFig.2013.6732304>. <hal-01216543>
  • Jung Kyu Chae, Paul Mougeat, Jean-Arnaud François, Roselyne Chotin-Avot, Habib Mehrez. Formalisme de la spécification de la plateforme de conception pour le développement de la bibliothèque. Journees Nationales du Reseau Doctoral de Micro-electronique, 2013, Grenoble, France. pp.1-4. <hal-01215668>
  • Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. Improved Method for Parallel AES-GCM Cores Using FPGAs. ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. IEEE, pp.1-4, 2013, <10.1109/ReConFig.2013.6732299>. <hal-01160904>
  • Emna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Zied Marrakchi. Efficient Multilevel Interconnect Topology for Cluster-based Mesh FPGA Architecture. ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. IEEE, pp.1-6, 2013, <10.1109/ReConFig.2013.6732282>. <hal-00987368v2>
  • Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. Protecting FPGA Bitstreams Using Authenticated Encryption. 11th IEEE International Conference of New Circuits and Systems (NEWCAS), Jun 2013, Paris, France. IEEE, pp.1-4, 2013, <10.1109/NEWCAS.2013.6573635>. <hal-01017823v2>
  • Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. High Speed Authenticated Encryption for Slow Changing Key Applications Using Reconfigurable Devices. Wireless Days (WD), 2013 IFIP, Nov 2013, Valencia, Spain. pp.1 - 6, 2013, <10.1109/WD.2013.6686460>. <hal-01017858v2>
  • Arwa Ben Dhia, Saif Ur Rehman, Adrien Blanchardon, Lirida Naviner, Mounir Benabdenbi, et al.. A Defect-tolerant Cluster in a Mesh SRAM-based FPGA. International Conference on Field-Programmable Technology (FPT), Dec 2013, Kyoto, Japan. IEEE Computer Society, pp.434-437, 2013, <10.1109/FPT.2013.6718407>. <hal-00987365>
  • Fatma Hamzaoui, Roselyne Chotin-Avot, Patricia Renault, Habib Mehrez, Hafedh Belmabrouk, et al.. Synthesis and Optimization of Quantum Boolean Circuit Using the Truth Table Method. International Workshop on Number Theory, Codes, Cryptography and Communication Systems (NTCCCS), Apr 2012, Oujda, Morocco. pp.192-197, 2012. <hal-01265626>
  • Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. The Effect of S-box Design on Pipelined AES Using FPGAs. Colloque GDR SOC-SIP, Jun 2012, Paris, France. pp.1-4, 2012. <hal-01265624>
  • Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez. Générateur d'Architecture de FPGA. Colloque GDR SOC-SIP, Jun 2012, Paris, France. Colloque GDR SOC-SIP, pp.1-3, 2012. <hal-00987369>
  • Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. Efficient Parallel-Pipelined GHASH for Message Authentication. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2012), Dec 2012, Cancun, Mexico. pp.1 - 6, 2012, <10.1109/ReConFig.2012.6416742>. <hal-01017807>
  • Sophie Belloeil-Dupuis, Roselyne Chotin-Avot, Habib Mehrez. Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools. ISQED 2011 - 12th International Symposium on Quality Electronic Design, Mar 2011, Santa Clara, CA, United States. IEEE, pp.502-507, 2011, <10.1109/ISQED.2011.5770774>. <hal-01265627>
  • Fatma Hamzaoui, Roselyne Chotin-Avot, Mohsen Machhout, Habib Mehrez, Hafedh Belmabrouk. Quantum circuits design and simulation. The First International Conference on "Research to Applications & Markets" (RAM 2011), Jun 2011, Monastir, Tunisia. pp.115-115, 2011. <hal-01265628>
  • Fatma Hamzaoui, Besma Othmani, Roselyne Chotin-Avot, Mohsen Machhout, Hafedh Belmabrouk, et al.. Modélisation et simplification de circuits quantiques. Materiaux 2010, Nov 2010, Mahdia, Tunisia. pp.2-2, 2010. <hal-01265629>
  • Zied Guitouni, Roselyne Chotin-Avot, Mohsen Machhout, Habib Mehrez, Rached Tourki. Design and FPGA Implementation of Modular Multiplication Methods Using Cellular Automata. DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Mar 2010, Hammamet, Tunisia. IEEE, pp.1-5, 2010, <10.1109/DTIS.2010.5487586>. <hal-01265630>
  • Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez, Alix Munier-Kordon. Automatic Allocation of Redundant Operators in Arithmetic Data path Optimization. DASIP IEEE International Conference on Design and Architectures for Signal and Image Processing, Nov 2008, Bruxelles, Belgium. pp.176-183, 2008. <hal-01265631>
  • Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez. Arithmetic Data path Optimization using Borrow-Save Representation. ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI, Apr 2008, Montpellier, France. IEEE, pp.4-9, 2008, <10.1109/ISVLSI.2008.29>. <hal-01265632>
  • Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez. Data Path Optimization using Redundant Arithmetic and Pattern Matching. Workshop on Design and Architectures for Signal and Image Processing (DASIP'2007), 2007, Grenoble, France. pp.281-288, 2007. <hal-01265633>
  • Sophie Belloeil, Jean-Paul Chaput, Roselyne Chotin-Avot, Christian Masson, Habib Mehrez. Stratus : Un environnement de développement de circuits. JP CNFM Journées pédagogiques du CNFM, 2006, Unknown, Unknown or Invalid Region. pp.57-61, 2006. <hal-01265634>
  • Alain Greiner, Frédéric Pétrot, Mathieu Carrier, Mounir Benabdenbi, Roselyne Chotin-Avot, et al.. Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chip. IV 2006 - IEEE Intelligent Vehicles Symposium, Jun 2006, Tokyo, Japan. IEEE, pp.370-376, 2006, <10.1109/IVS.2006.1689656>. <hal-00103535>
  • Roselyne Chotin-Avot, Habib Mehrez. Hardware implementation of discrete stochastic arithmetic. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2003, Poznan, Poland. pp.57-64, 6th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'03). <hal-01267471>
  • Roselyne Chotin-Avot, Jean-Marie Chesneaux, Jean-Luc Lamotte. On the computation of the CESTAC function. Proceedings of Real Numbers and Computers 5 (RNC5), 2003, Lyon, France. pp.247-260, 2003. <hal-01265635>
  • Roselyne Chotin, Habib Mehrez. Hardware implementation of a method to control round-off errors. 6th WSEAS International Multiconference on Circuits Systems Communications and Computers (CSCC'2002), 2002, Rethymnon, Greece. pp.157-162, 2002. <hal-01265639>
  • Roselyne Chotin, Habib Mehrez. Hardware implementation of the CESTAC method. 10th GAMM - IMACS International Symposium on Scientific Computing Computer Arithmetic and Validated Numerics (SCAN'2002), 2002, Paris, France. pp.162-162, 2002. <hal-01265638>
  • Roselyne Chotin, Habib Mehrez. Une unité de calcul flottant utilisant l'arithmétique stochastique. Vèmes Journées Nationales du Réseau Doctoral de Micro-électronique (JNRDM'2002), 2002, Grenoble, France. pp.217-218, 2002. <hal-01265637>
  • Roselyne Chotin, Habib Mehrez. Implantation matérielle d'une méthode de contrôle des erreurs d'arrondi de calcul. Troisième colloque du GDR CAO de circuits et systèmes intégrés, 2002, Paris, France. pp.63-66, 2002. <hal-01265636>
  • Roselyne Chotin, Habib Mehrez. A Floating-Point Unit using stochastic arithmetic compliant with the IEEE-754 standard. 9th IEEE International Conference on Electronics Circuits and Systems (ICECS'2002), 2002, Dubrovnik, Costa Rica. pp.603-606, 2002, <10.1109/ICECS.2002.1046241>. <hal-01265640>
  • Roselyne Chotin, Yannick Dumonteix, Habib Mehrez. Use of Redundant Arithmetic on Architecture and Design of a High Performance DCT Macro-bloc Generator. 15th Design of Circuits and Integrated Systems Conference (DCIS), 2000, Montpellier, France. pp.428-433, 2000. <hal-01265641>

Thèse1 document

  • Roselyne Chotin-Avot. Architectures matérielles pour l'arithmétique stochastique discrète. Arithmétique des ordinateurs. Université Pierre et Marie Curie (Paris, France), 2003. Français. <tel-01267458>

Poster1 document

  • Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang. Towards high performance GHASH for pipelined AES-GCM using FPGAs. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Feb 2014, Monterey, CA, United States. ACM, pp.242-242, 2014, <10.1145/2554688.2554709>. <hal-00969267>