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Directed Acyclic Graph Scheduling for Mixed-Criticality Systems

 Roberto Medina , Etienne Borde , Laurent Pautet
Reliable Software Technologies, Jun 2017, Vienne, Austria. pp.217-232
Communication dans un congrès hal-01995010v1
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Work-in-Progress: System-wide DVFS for real-time systems with probabilistic parameters

 Roberto Medina , Liliana Cucu-Grosjean
2019 IEEE Real-Time Systems Symposium (RTSS), Dec 2019, Hong Kong, Hong Kong SAR China. pp.508-511
Communication dans un congrès hal-02421157v1

Availability enhancement and analysis for mixed-criticality systems on multi-core

 Roberto Medina , Etienne Borde , Laurent Pautet
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2018, Dresden, France. pp.1271-1276
Communication dans un congrès hal-01994643v1
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Scheduling Multi-Periodic Mixed-Criticality DAGs on Multi-Core Architectures

 Roberto Medina , Etienne Borde , Laurent Pautet
39th IEEE Real-Time Systems Symposium (RTSS 2018), Dec 2018, Nashville, TN, United States. ⟨10.1109/RTSS.2018.00042⟩
Communication dans un congrès hal-01994627v1
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