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93 résultats
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ECRINS un laboratoire de preuve pour les calculs de processus[Rapport de recherche] RR-0672, INRIA. 1987
Rapport
inria-00075881v1
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Static mapping of real-time applications onto massively parallel processor arrays14th International Conference on Application of Concurrency to System Design, Jun 2014, Hammamet, Tunisia
Communication dans un congrès
hal-01095130v1
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Deterministic execution of synchronous programs in an asynchronous environment. A compositional necessary and sufficient condition[Research Report] RR-6656, INRIA. 2008, pp.20
Rapport
inria-00322563v1
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From concurrent multi-clock programs to concurrent multi-threaded implementations[Research Report] RR-7577, INRIA. 2011, pp.22
Rapport
inria-00578585v2
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LID: Retry Relay Station and Fusion Shell[Research Report] RR-7293, INRIA. 2009
Rapport
inria-00484185v1
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On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling2015
Pré-publication, Document de travail
hal-01179489v1
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Modeling and Analyzing Dataflow Applications on NoC-Based Many-Core ArchitecturesACM Transactions on Embedded Computing Systems (TECS), 2015, Special Issue on Embedded Platforms for Crypto and Regular Papers, 14 (3), pp.article 46. ⟨10.1145/2700081⟩
Article dans une revue
hal-01097315v1
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MARTE vs. AADL for Discrete-Event and Discrete-Time DomainsMartin Radetzki. Languages for Embedded Systems and their Applications, 36, Springer, pp.27-41, 2009, Lecture Notes in Electrical Engineering, 978-1-4020-9713-3. ⟨10.1007/978-1-4020-9714-0_2⟩
Chapitre d'ouvrage
istex
inria-00416656v1
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Petri nets and algebraic calculi of processes[Research Report] RR-0410, INRIA. 1985
Rapport
inria-00076146v1
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Another glance at Relay Stations in Latency-Insensitive Designs[Research Report] RR-5557, INRIA. 2005, pp.19
Rapport
inria-00070449v1
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UML MARTE Time Model and Its Clock Constraint Specification LanguageAlessandra Bagnato; Leandro Soares Indrusiak; Imran Rafiq Quadri; Matteo Rossi. Embedded Systems Design, IGI Global, 2014, Handbook of Research on, 9781466661943. ⟨10.4018/978-1-4666-6194-3.ch002⟩
Chapitre d'ouvrage
hal-01079039v1
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Logical Time: observation vs. implementationSoftware Engineering Notes, 2011, 36 (1), pp.1--8. ⟨10.1145/1921532.1921554⟩
Article dans une revue
inria-00576647v1
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Clock-Driven Distributed Real-Time Implementation of Endochronous Synchronous ProgramsInternational conference on Embedded software - EMSOFT 2009, Oct 2009, Grenoble, France. ⟨10.1145/1629335.1629356⟩
Communication dans un congrès
inria-00485007v1
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Explicit Control of Dataflow Graphs with MARTE/CCSLMODELSWARD 2017 - 5th International Conference on Model-Driven Engineering and Software Development, MODELSWARD 2017, Feb 2017, Porto, Portugal. pp.542-549, ⟨10.5220/0006269505420549⟩
Communication dans un congrès
hal-01644294v1
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Execution of Heterogeneous Models for Thermal Analysis with a Multi-view ApproachFDL 2014 : Forum on specification and Design Languages, Oct 2014, Munich, Germany
Communication dans un congrès
hal-01060309v1
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The Time Model of Logical Clocks available in the OMG MARTE profileSandeep K. Shukla and Jean-Pierre Talpin. Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, Springer Science+Business Media, LLC 2010, pp.28, 2010, 978-1-4419-6399-4
Chapitre d'ouvrage
inria-00495664v1
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Time in SCChartsLanguage, Design Methods, and Tools for Electronic System Design, Springer, pp.1-25, 2019, ⟨10.1007/978-3-030-31585-6_1⟩
Chapitre d'ouvrage
hal-02434885v1
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Programming and verifying real-time design using logical timeFDL 2021 - Forum on specification & Design Languages, Sep 2021, Antibes, France
Communication dans un congrès
hal-03537976v1
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Application Architecture Adequacy through an FFT case studyJRWRTC2013 - 7th Junior Researcher Workshop on Real-Time Computing, Sebastian Altmeyer, Oct 2013, Sophia Antipolis, France. pp.4
Communication dans un congrès
hal-00950533v1
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Synchronous hypothesis and polychronous languagesRichard Zurawski. Embedded Systems Design and Verification, CRC Press, pp.6-1-6-27, 2009, 978-1-4398-0755-2. ⟨10.1201/9781439807637.ch6⟩
Chapitre d'ouvrage
hal-00788473v1
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Correctness Issues on MARTE/CCSL constraintsScience of Computer Programming, 2015, 106, pp.78-92. ⟨10.1016/j.scico.2015.03.001⟩
Article dans une revue
hal-01257978v1
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Modeling of Immediate vs. Delayed Data Communications: from AADL to UML MARTEECSI Forum on specification & Design Languages (FDL), ECSI, Sep 2007, Barcelona, Spain. pp.249-254
Communication dans un congrès
inria-00204484v1
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Semantics foundations of PsyC based on synchronous Logical Execution TimeCPS-IoT Week 2023 - Cyber-Physical Systems and Internet of Things Week 2023, May 2023, San Antonio TX USA, France. pp.319-324, ⟨10.1145/3576914.3587495⟩
Communication dans un congrès
hal-04355453v1
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Periodic scheduling of marked graphs using balanced binary words[Research Report] RR-7891, INRIA. 2012, pp.33
Rapport
hal-00672606v1
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Modeling Time(s)ACM/IEEE Int. Conf. on Model Driven Engineering Languages and Systems (MoDELS/UML), Oct 2007, Nashville, TN, United States. pp. 559-573, ⟨10.1007/978-3-540-75209-7_38⟩
Communication dans un congrès
inria-00204489v1
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Tailored Protocol Development Using ESTEREL[Research Report] RR-2374, INRIA. 1994
Rapport
inria-00074302v1
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Marte: A new profile rfp for the modeling and analysis of real-time embedded systemsDac Workshop - UML-SoC05, Jun 2005, Anaheim CA, United States
Communication dans un congrès
hal-01071285v1
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Formal Semantics of the PsyC languageRR-9506, Inria - Sophia Antipolis. 2023, pp.32
Rapport
hal-04088177v1
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Introduction to special issue: papers from UML&FM'2009Innovations in Systems and Software Engineering: A NASA Journal, 2010, 6 (1-2), pp.1-3
Article dans une revue
hal-02286673v1
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Petri nets and algebraic calculi of processes[Research Report] RR-0292, INRIA. 1984
Rapport
inria-00076266v1
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