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93 résultats
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Petri nets and algebraic calculi of processes[Research Report] RR-0410, INRIA. 1985
Rapport
inria-00076146v1
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Another glance at Relay Stations in Latency-Insensitive Designs[Research Report] RR-5557, INRIA. 2005, pp.19
Rapport
inria-00070449v1
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UML MARTE Time Model and Its Clock Constraint Specification LanguageAlessandra Bagnato; Leandro Soares Indrusiak; Imran Rafiq Quadri; Matteo Rossi. Embedded Systems Design, IGI Global, 2014, Handbook of Research on, 9781466661943. ⟨10.4018/978-1-4666-6194-3.ch002⟩
Chapitre d'ouvrage
hal-01079039v1
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Logical Time: observation vs. implementationSoftware Engineering Notes, 2011, 36 (1), pp.1--8. ⟨10.1145/1921532.1921554⟩
Article dans une revue
inria-00576647v1
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Clock-Driven Distributed Real-Time Implementation of Endochronous Synchronous ProgramsInternational conference on Embedded software - EMSOFT 2009, Oct 2009, Grenoble, France. ⟨10.1145/1629335.1629356⟩
Communication dans un congrès
inria-00485007v1
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Explicit Control of Dataflow Graphs with MARTE/CCSLMODELSWARD 2017 - 5th International Conference on Model-Driven Engineering and Software Development, MODELSWARD 2017, Feb 2017, Porto, Portugal. pp.542-549, ⟨10.5220/0006269505420549⟩
Communication dans un congrès
hal-01644294v1
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Execution of Heterogeneous Models for Thermal Analysis with a Multi-view ApproachFDL 2014 : Forum on specification and Design Languages, Oct 2014, Munich, Germany
Communication dans un congrès
hal-01060309v1
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The Time Model of Logical Clocks available in the OMG MARTE profileSandeep K. Shukla and Jean-Pierre Talpin. Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, Springer Science+Business Media, LLC 2010, pp.28, 2010, 978-1-4419-6399-4
Chapitre d'ouvrage
inria-00495664v1
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Time in SCChartsLanguage, Design Methods, and Tools for Electronic System Design, Springer, pp.1-25, 2019, ⟨10.1007/978-3-030-31585-6_1⟩
Chapitre d'ouvrage
hal-02434885v1
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Programming and verifying real-time design using logical timeFDL 2021 - Forum on specification & Design Languages, Sep 2021, Antibes, France
Communication dans un congrès
hal-03537976v1
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ECRINS un laboratoire de preuve pour les calculs de processus[Rapport de recherche] RR-0672, INRIA. 1987
Rapport
inria-00075881v1
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Static mapping of real-time applications onto massively parallel processor arrays14th International Conference on Application of Concurrency to System Design, Jun 2014, Hammamet, Tunisia
Communication dans un congrès
hal-01095130v1
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Deterministic execution of synchronous programs in an asynchronous environment. A compositional necessary and sufficient condition[Research Report] RR-6656, INRIA. 2008, pp.20
Rapport
inria-00322563v1
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From concurrent multi-clock programs to concurrent multi-threaded implementations[Research Report] RR-7577, INRIA. 2011, pp.22
Rapport
inria-00578585v2
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LID: Retry Relay Station and Fusion Shell[Research Report] RR-7293, INRIA. 2009
Rapport
inria-00484185v1
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On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling2015
Pré-publication, Document de travail
hal-01179489v1
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Modeling and Analyzing Dataflow Applications on NoC-Based Many-Core ArchitecturesACM Transactions on Embedded Computing Systems (TECS), 2015, Special Issue on Embedded Platforms for Crypto and Regular Papers, 14 (3), pp.article 46. ⟨10.1145/2700081⟩
Article dans une revue
hal-01097315v1
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MARTE vs. AADL for Discrete-Event and Discrete-Time DomainsMartin Radetzki. Languages for Embedded Systems and their Applications, 36, Springer, pp.27-41, 2009, Lecture Notes in Electrical Engineering, 978-1-4020-9713-3. ⟨10.1007/978-1-4020-9714-0_2⟩
Chapitre d'ouvrage
istex
inria-00416656v1
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Aboard AUTO[Research Report] RT-0111, INRIA. 1989, pp.24
Rapport
inria-00070055v1
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Vérification d'applications temps-réel basées sur le paradigme de Logical Execution Time (LET)École d’Été Temps Réel 2021, Sep 2021, Poitiers, France
Communication dans un congrès
hal-03545758v1
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A formal approach to the mapping of tasks on an heterogenous multicore, energy-aware architectureMEMOCODE'16 - 14th ACM-IEEE International Conference on Formal Methods and Models for System Design, Nov 2016, Kanpur, India. pp.10
Communication dans un congrès
hal-01412790v1
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Time in SCChartsForum on specification & Design Languages, Sep 2018, Munich, Germany. pp.5-16, ⟨10.1109/FDL.2018.8524111⟩
Communication dans un congrès
hal-01898285v1
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Formal Methods for Scheduling of Latency-Insensitive DesignsEURASIP Journal on Embedded Systems, 2007, 2007 (1), pp.039161. ⟨10.1155/2007/39161⟩
Article dans une revue
hal-00784464v1
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Event-based vs. Time-Triggered Communications with UML MarteForum on specification, verification & Design Languages (FDL'08), ECSI, Sep 2008, Stuttgart, Germany. pp.154-159, ⟨10.1109/FDL.2008.4641438⟩
Communication dans un congrès
inria-00371392v1
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MARTE: A Profile for RT/E Systems Modeling, Analysis (and Simulation?)First International Conference on Simulation Tools and Techniques for Communications, Networks and Systems SIMUTools'08, ICST, Mar 2008, Marseille, France. pp.1-8
Communication dans un congrès
inria-00371397v1
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Dealing with AADL end-to-end Flow Latency with UML Marte.ICECCS - UML&AADL, Apr 2008, Belfast, Ireland. pp.228-233, ⟨10.1109/ICECCS.2008.14⟩
Communication dans un congrès
inria-00371400v1
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Modeling with logical time in UML for real-time embedded system design[Research Report] RR-5895, INRIA. 2006
Rapport
inria-00071373v1
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Schedulability analysis by exhaustive state space construction: translating CCSL to transition-based Generalized Buchi Automata[Research Report] RR-8102, 2012, pp.22
Rapport
hal-00743874v1
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From Synchronous Specifications to Statically-Scheduled Hard Real-Time ImplementationsSandeep K. Shukla and Jean-Pierre Talpin. Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, Springer Science+Business Media, LLC 2010, pp.34, 2010, 978-1-4419-6399-4
Chapitre d'ouvrage
inria-00495666v1
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Normal Forms and Equivalence of K-periodically Routed Graphs[Research Report] RR-7286, INRIA. 2010
Rapport
inria-00485609v2
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