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Number of documents

32


Journal articles7 documents

  • Nicolas Belleville, Damien Couroussé, Karine Heydemann, Quentin Meunier, Inès Ben El Ouahma. Maskara: Compilation of a Masking Countermeasure with Optimised Polynomial Interpolation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2020, pp.1-1. ⟨10.1109/TCAD.2020.3012237⟩. ⟨hal-02931632⟩
  • Inès Ben el ouahma, Quentin Meunier, Karine Heydemann, Emmanuelle Encrenaz. Side-channel robustness analysis of masked assembly codes using a symbolic approach. Journal of Cryptographic Engineering, Springer, 2019, pp.1-12. ⟨10.1007/s13389-019-00205-7⟩. ⟨hal-02102873⟩
  • Clément Dévigne, Jean-Baptiste Bréjon, Quentin L. Meunier, Franck Wajsbürt. Executing Secured Virtual Machines within a Manycore Architecture. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, ⟨10.1016/j.micpro.2016.09.008⟩. ⟨hal-01382444⟩
  • Mohamed Lamine Karaoui, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner. GECOS : Mécanisme de synchronisation passant à l’échelle à plusieurs lecteurs et un écrivain pour structures chaînées. Technique et Science Informatiques, Hermès-Lavoisier, 2015, 34, pp.53-78. ⟨10.3166/tsi.34.53-78⟩. ⟨hal-01340603⟩
  • Quentin L. Meunier, Frédéric Pétrot. Systèmes de mémoire transactionnelle pour les architectures à base de NoC Conception, implémentation et comparaison de deux politiques. Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, Lavoisier, 2011, 30 (9), pp.1061-1087. ⟨10.3166/tsi.30.1061-1087⟩. ⟨hal-00680463⟩
  • Quentin L. Meunier, Frédéric Pétrot, Jean-Louis Roch. Hardware/software support for adaptive work-stealing in on-chip multiprocessor. Journal of Systems Architecture, Elsevier, 2010, 56 (08), pp.392-406. ⟨10.1016/j.sysarc.2010.06.007⟩. ⟨hal-00551685⟩
  • Quentin L. Meunier, Frédéric Pétrot. Lightweight Transactional Memory systems for NoCs based architectures: Design, implementation and comparison of two policies. Journal of Parallel and Distributed Computing, Elsevier, 2010, 70 (10), pp.1024-1041. ⟨10.1016/j.jpdc.2010.02.007⟩. ⟨hal-00551686⟩

Conference papers23 documents

  • Andrea Petreto, Thomas Romera, Florian Lemaitre, Manuel Bouyer, Boris Gaillard, et al.. Real-time embedded video denoiser prototype. 9th International Symposium - Optronics in Defense and Security (Optro), Jan 2020, Paris, France. ⟨hal-02469914⟩
  • Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, et al.. A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm 2 Inter-Chiplet Interconnects and 156mW/mm 2 @ 82%-Peak-Efficiency DC-DC Converters. 2020 IEEE International Solid- State Circuits Conference - (ISSCC), Feb 2020, San Francisco, United States. pp.46-48, ⟨10.1109/ISSCC19947.2020.9062927⟩. ⟨hal-02985945⟩
  • Quentin L. Meunier, Inès Ben El Ouahma, Karine Heydemann. SELA: a Symbolic Expression Leakage Analyzer. International Workshop on Security Proofs for Embedded Systems, Sep 2020, Visioconference, France. ⟨hal-02983213⟩
  • Andrea Petreto, Thomas Romera, Ian Masliah, Boris Gaillard, Manuel Bouyer, et al.. A New Real-Time Embedded Video Denoising Algorithm. DASIP 2019 - The Conference on Design and Architectures for Signal and Image Processing, Oct 2019, Montréal, Canada. ⟨hal-02343597⟩
  • Andrea Petreto, Thomas Romera, Florian Lemaitre, Ian Masliah, Boris Gaillard, et al.. Débruitage temps réel embarqué pour vidéos fortement bruitées. COMPAS 2019, Jun 2019, Anglet, France. ⟨hal-02268005⟩
  • Jean-Baptiste Bréjon, Karine Heydemann, Emmanuelle Encrenaz, Quentin L. Meunier, Son Tuan Vu. Fault attack vulnerability assessment of binary code. Cryptography and Security in Computing Systems (CS2’19), Jan 2019, Valencia, Spain. pp.13-18, ⟨10.1145/3304080.3304083⟩. ⟨hal-02163152⟩
  • Quentin L. Meunier. FastCPA: Efficient Correlation Power Analysis Computation with a Large Number of Traces. 6th Cryptography and Security in Computing Systems (CS2’19), Jan 2019, Valence, Spain. ⟨10.1145/3304080.3304082⟩. ⟨hal-02172200⟩
  • Andrea Petreto, Arthur Hennequin, Thomas Koehler, Thomas Romera, Yohan Fargeix, et al.. Comparaison de la consommation énergétique et du temps d'exécution d'un algorithme de traitement d'images optimisé sur des architectures SIMD et GPU. Conférence d’informatique en Parallélisme, Architecture et Système (COMPAS 2018), Jul 2018, Toulouse, France. ⟨hal-01835219⟩
  • E. Guthmuller, C. Fuguet, P. Vivet, C. Bernard, I. Miro-Panades, et al.. A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Sep 2018, Dresden, Germany. pp.318-321, ⟨10.1109/ESSCIRC.2018.8494275⟩. ⟨hal-02985969⟩
  • Quentin L. Meunier, Yann Thierry Mieg, Emmanuelle Encrenaz. Modeling a Cache Coherence Protocol with the Guarded Action Language. Workshop on Models for Formal Analysis of Real Systems, Apr 2018, Thessaloniki, Greece. ⟨10.4204/EPTCS.268.3⟩. ⟨hal-02172237⟩
  • Arthur Hennequin, Lionel Lacassagne, Laurent Cabaret, Quentin Meunier. A new Direct Connected Component Labeling and Analysis Algorithms for GPUs. 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2018, Porto, Portugal. ⟨10.1109/dasip.2018.8596835⟩. ⟨hal-01923784⟩
  • Andrea Petreto, Arthur Hennequin, Thomas Koehler, Thomas Romera, Yohan Fargeix, et al.. Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU Architectures. Conference on Design and Architectures for Signal and Image Processing (Dasip 2018), Oct 2018, Porto, Portugal. ⟨hal-01925886⟩
  • Hao Liu, Quentin L. Meunier, Alain Greiner. Decoupling Translation Lookaside Buffer Coherence from Cache Coherence. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), Jul 2017, Bochum, Germany. pp.92 - 97, ⟨10.1109/ISVLSI.2017.25⟩. ⟨hal-01585880⟩
  • Inès Ben El Ouahma, Quentin L. Meunier, Karine Heydemann, Emmanuelle Encrenaz. Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes. Security Proofs for Embedded Systems, Sep 2017, Taipei, China. ⟨hal-01612463⟩
  • Mohamed Lamine Karaoui, Pierre-Yves Péneau, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner. Exploiting Large Memory using 32-bit Energy-Efficient Manycore Architectures. MCSoC: Many-core Systems-on-Chip, Sep 2016, Lyon, France. pp.61-68, ⟨10.1109/MCSoC.2016.44⟩. ⟨hal-01362760⟩
  • Clément Dévigne, Jean-Baptiste Bréjon, Quentin L. Meunier, Franck Wajsbürt. Executing secured virtual machines within a manycore architecture. IEEE Nordic Circuits and Systems Conference (NORCAS), Oct 2015, Oslo, Norway. ⟨10.1109/NORCHIP.2015.7364380⟩. ⟨hal-01363066⟩
  • Hao Liu, Clément Dévigne, Lucas Garcia, Quentin L. Meunier, Franck Wajsbürt, et al.. RWT: Suppressing Write-Through Cost When Coherence is Not Needed. 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul 2015, Montpellier, France. pp.434-439, ⟨10.1109/ISVLSI.2015.35⟩. ⟨hal-01362872⟩
  • Mohamed Lamine Karaoui, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner. Mécanisme de synchronisation scalable à plusieurs lecteurs et un écrivain. Conférence en Parallélisme, Architecture et Systèmes, ComPAS 2014, Apr 2014, Neuchâtel, Suisse. ⟨hal-01219760⟩
  • Jean-Charles Naud, Quentin L. Meunier, Daniel Ménard, Olivier Sentieys. Fixed-point Accuracy Evaluation in the Context of Conditional Structures. 19th European Signal Processing Conference (EUSIPCO), Sep 2011, Barcelona, Spain. ⟨hal-00747610⟩
  • Naud Jean-Charles, Daniel Menard, Quentin L. Meunier, Olivier Sentieys. Evaluation de la précision en virgule fixe dans le cas des structures conditionnelles. 14th Symposium en Architecture (SympA'11), May 2011, Saint Malo, France. ⟨inria-00617720⟩
  • Quentin L. Meunier, Frédéric Pétrot. LightTM : Une Mémoire Transactionnelle conçue pour les MPSoCs. Symposium en Architecture de machines (SympA'13), Sep 2009, Toulouse, France. pp.1-12. ⟨hal-00419309⟩
  • Quentin L. Meunier, Frédéric Pétrot. Lightweight Transactional Memory Systems for Large Scale Shared Memory MPSoCs. NEWCAS – TAISA'09 Conference, Jun 2009, Toulouse, France. pp.432 - 435. ⟨hal-00419304⟩
  • Frédéric Pétrot, Quentin L. Meunier. Design and Use of Transactional Memory in MPSoCs. 9th International Seminar on Application Specific Multiprocessor SoC, Aug 2009, Savanah, Georgia, United States. ⟨hal-00560474⟩

Poster communications1 document

  • Andrea Petreto, Arthur Hennequin, Thomas Koehler, Thomas Romera, Yohan Fargeix, et al.. Comparaison de la consommation énergétique et du temps d'exécution d'un algorithme de traitement d'images optimisé sur des architectures SIMD et GPU. GdR SOC2, Jun 2018, Paris, France. ⟨hal-01835240⟩

Theses1 document

  • Quentin L. Meunier. Étude de deux solutions pour le support matériel de la programmation parallèle dans les multiprocesseurs intégrés : vol de travail et mémoires transactionnelles. Autre [cs.OH]. Institut National Polytechnique de Grenoble - INPG, 2010. Français. ⟨tel-00532794⟩