Filtrer vos résultats
- 48
- 2
- 25
- 13
- 11
- 1
- 23
- 1
- 50
- 1
- 1
- 2
- 1
- 1
- 2
- 5
- 3
- 3
- 4
- 3
- 3
- 2
- 4
- 1
- 3
- 3
- 1
- 1
- 1
- 2
- 1
- 2
- 50
- 50
- 50
- 6
- 3
- 2
- 2
- 2
- 1
- 1
- 1
- 1
- 50
- 19
- 5
- 3
- 3
- 3
- 2
- 2
- 2
- 2
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
50 résultats
|
|
|
triés par
|
|
|
Selecting Benchmark Combinations for the Evaluation of Multicore ThroughputInternational Symposium on Performance Analysis of Systems and Software, Apr 2013, Austin, United States. ⟨10.1109/ISPASS.2013.6557168⟩
Communication dans un congrès
hal-00788824v1
|
||
|
|
A PPM-like, tag-based branch predictorThe Journal of Instruction-Level Parallelism, 2005, 7, pp.10
Article dans une revue
hal-03406188v1
|
||
|
|
Periodic activity migration for fast sequential execution in future heterogeneous multicore processors[Research Report] RR-6735, INRIA. 2008, pp.17
Rapport
inria-00341851v1
|
||
|
|
Hardware acceleration of sequential loops[Research Report] RR-7802, INRIA. 2011
Rapport
hal-00641350v1
|
||
|
|
Scheduling Issues on Thermally-Constrained Processors[Research Report] RR-6006, INRIA. 2006
Rapport
inria-00110085v2
|
||
|
|
Constant-work multiprogram throughput metrics for microarchitecture studies[Research Report] RR-8150, INRIA. 2012
Rapport
hal-00758195v1
|
||
|
|
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors[Research Report] RR-3604, INRIA. 1999
Rapport
inria-00077111v1
|
||
|
|
Selecting Benchmarks Combinations for the Evaluation of Multicore Throughput[Research Report] 2012, pp.23
Rapport
hal-00737446v2
|
||
|
|
A Best-Offset Prefetcher2nd Data Prefetching Championship, Jun 2015, Portland, United States
Communication dans un congrès
hal-01165600v1
|
||
|
|
Exploiting Thermal Transients With Deterministic Turbo Clock FrequencyIEEE Computer Architecture Letters, 2020, 19 (1), pp.43-46. ⟨10.1109/LCA.2020.2983920⟩
Article dans une revue
hal-02562105v1
|
||
|
|
An Alternative TAGE-like Conditional Branch PredictorACM Transactions on Architecture and Code Optimization, 2018, 15 (3), pp.1-24. ⟨10.1145/3226098⟩
Article dans une revue
hal-01799442v1
|
||
|
|
Multiprogram Throughput Metrics: A Systematic ApproachACM Transactions on Architecture and Code Optimization, 2014, 11 (3), pp.26. ⟨10.1145/2663346⟩
Article dans une revue
hal-01087743v1
|
||
|
|
BADCO: Behavioral Application-Dependent superscalar Core Models[Research Report] RR-7795, INRIA. 2011, pp.21
Rapport
hal-00641446v1
|
||
|
|
Defining metrics for multicore throughput on multiprogrammed workloads[Research Report] RR-8401, INRIA. 2013
Rapport
hal-00908864v1
|
||
|
|
Online compression of cache-filtered address tracesIEEE International Symposium on Performance Analysis of Systems and Software, Apr 2009, Boston, United States
Communication dans un congrès
hal-00780914v1
|
||
|
|
An Analytical Model of Temperature in Microprocessors[Research Report] RR-5744, INRIA. 2005, pp.32
Rapport
inria-00070275v1
|
||
|
|
Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue ClustersACM Transactions on Architecture and Code Optimization, 2015, 13 (3), pp.22. ⟨10.1145/2800787⟩
Article dans une revue
hal-01193178v1
|
||
|
|
A Simple Model of Processor Temperature for Deterministic Turbo Clock Frequency[Research Report] RR-9308, Inria. 2019
Rapport
hal-02391970v2
|
||
|
|
Proposition for a sequential accelerator in future general-purpose manycore processors[Research Report] RR-7106, INRIA. 2009
Rapport
inria-00433234v3
|
||
|
|
Best-Offset Hardware PrefetchingInternational Symposium on High-Performance Computer Architecture, Mar 2016, Barcelona, Spain. ⟨10.1109/HPCA.2016.7446087⟩
Communication dans un congrès
hal-01254863v1
|
||
|
|
Replacement policies for shared caches on symmetric multicores: a programmer-centric point of view[Research Report] RR-6734, INRIA. 2008, pp.22
Rapport
inria-00341843v1
|
||
|
|
Replacement policies for shared caches on symmetric multicores : a programmer-centric point of view[Research Report] PI 1908, 2008, pp.25
Rapport
inria-00340545v1
|
||
|
|
Analysis of a tag-based branch predictor[Research Report] RR-5366, INRIA. 2004, pp.21
Rapport
inria-00070637v1
|
||
|
|
Revisiting Symbiotic Job SchedulingIEEE International Symposium on Performance Analysis of Systems and Software, Mar 2015, Philadelphia, United States. ⟨10.1109/ISPASS.2015.7095791⟩
Communication dans un congrès
hal-01139807v1
|
||
|
|
Pushing the branch predictability limits with the multi-poTAGE+SC predictor4th JILP Workshop on Computer Architecture Competitions (JWAC-4): Championship Branch Prediction (CBP-4), Jun 2014, Minneapolis, United States
Communication dans un congrès
hal-01087719v1
|
||
|
|
Five poTAGEs and a COLT for an unrealistic predictor4th JILP Workshop on Computer Architecture Competitions (JWAC-4): Championship Branch Prediction (CBP-4), Jun 2014, Minneapolis, United States
Communication dans un congrès
hal-01087692v1
|
||
|
|
The 3P and 4P cache replacement policiesJWAC 2010 - 1st JILP Worshop on Computer Architecture Competitions: cache replacement Championship, Jun 2010, Saint Malo, France
Communication dans un congrès
inria-00492968v1
|
||
|
|
An analytical model of temperature in microprocessors[Research Report] PI 1760, 2005, pp.32
Rapport
inria-00000613v1
|
||
We had 64-bit, yes. What about second 64-bit?RISC-V Summit Europe 2023, Jun 2023, Barcelona, Spain. 2023
Poster de conférence
hal-04161612v1
|
|||
|
|
A case for (partially) tagged geometric history length branch predictionThe Journal of Instruction-Level Parallelism, 2006, 8, pp.23
Article dans une revue
hal-03408381v1
|
- 1
- 2