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48 résultats
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triés par
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FPGA Configuration of Intensive Multimedia Processing Tasks Modeled in UML[Research Report] RR-5810, INRIA. 2006, pp.13
Rapport
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MDA for SoC Design, Intensive Signal Processing ExperimentFDL'03, ECSI, 2003, Frankfurt, Germany
Communication dans un congrès
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Une analyse des exercices d'algorithmique et de programmation des DNBCommission inter-IREM informatique. 2023
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hal-03996891v2
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FPGA-based many-core System-on-Chip designMicroprocessors and Microsystems: Embedded Hardware Design , 2015, pp.38. ⟨10.1016/j.micpro.2015.03.007⟩
Article dans une revue
hal-01144977v1
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Informatique - Support d'enseignement 1re année de licence, Univ. LilleLicence. Informatique, Université de Lille, Villeneuve d'Ascq, France. 2022, pp.211
Cours
hal-04131704v1
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Gaspard2: from MARTE to SystemC SimulationProceeedings of the DATE'08 workshop on Modeling and Analyzis of Real-Time and Embedded Systems with the MARTE UML profile, Mar 2008, Washington, United States
Communication dans un congrès
inria-00524373v1
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ARTiS, an Asymmetric Real-Time Scheduler for Linux on Multi-Processor Architectures[Research Report] RR-5781, INRIA. 2005, pp.32
Rapport
inria-00070240v1
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A High Level Synthesis Flow Using Model Driven EngineeringGogniat, G.; Milojevic, D.; Morawiec, A.; Erdogan, A. Algorithm-Architecture Matching for Signal and Image Processing, 73, Springer, pp.253-274, 2010, Lecture Notes in Electrical Engineering, 978-90-481-9964-8
Chapitre d'ouvrage
inria-00524821v1
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Why to do Without Model Driven Architecture in Embedded System Codesign?The first annual IEEE BENELUX/DSP Valley Signal Processing Symposium, (SPS-DARTS 2005), 2005, Antwerp, Belgium
Communication dans un congrès
inria-00565174v1
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Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip6th International Symposium on Applied Reconfigurale Computing, ARC 2010, Mar 2010, Bangkok, Thailand. pp.110-121, ⟨10.1007/978-3-642-12133-3_12⟩
Communication dans un congrès
inria-00524987v1
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How to make teenage girls love coding ?womENcourage2017 - 4th ACM Europe Celebration of Women in Computing, ACM, Sep 2017, Barcelona, Spain
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hal-01552490v1
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Dispositifs pour favoriser la venue des adolescentes dans les filières informatiques.Diversité, Réussite[s] dans l’Enseignement Supérieur (2024), Nantes Université [Nantes Univ], Apr 2024, Nantes, France
Communication dans un congrès
hal-04557120v1
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L’informatique, objets d’enseignements enjeux épistémologiques, didactiques et de formation2020
Proceedings/Recueil des communications
hal-02474983v1
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L'informatique, objets d'enseignements -enjeux epistémologiques, didactiques et de formation. Editorial des actes du colloqueColloque Didapro-Didastic 8, Feb 2020, Lille, France
Communication dans un congrès
hal-02462392v1
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Model Driven Engineering Benefits for High Level Synthesis[Research Report] RR-6615, INRIA. 2008, pp.46
Rapport
inria-00311300v1
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SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively parallel SoCPDP 2016 - 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, Feb 2016, Héraklion, Greece. pp.759-762, ⟨10.1109/PDP.2016.94⟩
Communication dans un congrès
hal-01246680v1
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Master-Slave Control structure for massively parallel System on ChipDSD SEAA - 16th Euromicro Conference on Digital System Design, Sep 2013, Santander, Spain
Communication dans un congrès
hal-00906906v1
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Une analyse des exercices d’algorithmique et de programmation du brevet 2017Repères IREM, 2019, 116, pp.47-81
Article dans une revue
hal-02077738v2
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FPGA Implementation of Embedded Cruise Control and Anti-Collision RadarEUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, Sep 2006, Dubrovnik, Croatia
Communication dans un congrès
inria-00079057v1
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Scalable mpNoC for massively parallel systems - Design and implementation on FPGAJournal of Systems Architecture, 2010, 56 (7), pp.278 - 292. ⟨10.1016/j.sysarc.2010.04.001⟩
Article dans une revue
inria-00525343v1
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Communication-Computation overlap in massively parallel System on Chip2014
Autre publication scientifique
hal-01104157v1
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A Model Driven Design Framework for High Performance Embedded Systems[Research Report] RR-6614, INRIA. 2008, pp.47
Rapport
inria-00311115v1
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Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies - A partial answer to the MARTE RFPMoDELS/UML 2005, ACM/IEEE 8th International Conference on Model Driven Engineering Languages and Systems, 2005, Montego Bay, Jamaica. pp.445-459
Communication dans un congrès
inria-00565168v1
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Sophocles: Cyber-Enterprise for System-on-Chip Distributed Simulation -- Model UnificationIFIP International Workshop on IP Based System-on-Chip Design, 2003, Grenoble, France
Communication dans un congrès
inria-00565177v1
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Visual Data-parallel Programming for Signal Processing Applications9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001, 2001, Mantova, Italy. pp.105--112
Communication dans un congrès
inria-00565183v1
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Gaspard2 UML profile documentation[Technical Report] RT-0342, INRIA. 2007, pp.45
Rapport
inria-00171137v2
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How to make teenage girls love coding using Python and the visual arts orienting language Processing ?PyParis2017, Systematic Paris Region, Jun 2017, Paris, La Défense, France
Communication dans un congrès
hal-01552487v1
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Repetitive Allocation Modeling with MARTEForum on specification and design languages (FDL'07), 2007, Barcelona, Spain
Communication dans un congrès
inria-00565160v1
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Model Driven Architecture for Intensive Embedded SystemsSébastien Gérard and Jean-Philippe Babeau and Joël Champeau. Model Driven Engineering for Distributed Embedded Real-Time Systems, ISTE, Hermes science and Lavoisier, 2005, 1-905209-32-0
Chapitre d'ouvrage
inria-00565171v1
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MDA for SoC Embedded Design, Intensive Signal Processing ExperimentSIVOES-MDA, 2003, San Francisco, United States
Communication dans un congrès
inria-00565178v1
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