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PP
Philippe POURE
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Documents
Identifiants chercheurs
- philippe-poure
- 0000-0002-1849-4868
- Google Scholar : https://scholar.google.com/citations?user=hKni3IIAAAAJ&hl=fr&oi=ao
- IdRef : 070741395
Présentation
**Personal information**
**Philippe POURE**
Nationality: French – Birthdate: September 9th 1968 – Married – 2 children
Status: Full Professor at Université de Lorraine – Faculté des Sciences et Technologies, Nancy, France
Research unit: Institut Jean Lamour (IJL), CNRS UMR 7198 - <https://ijl.univ-lorraine.fr/>
Google Scholar identifier : [https://scholar.google.com/citations?user=hKni3IIAAAAJ&hl=fr&oi=ao](https://scholar.google.com/citations?user=hKni3IIAAAAJ&hl=fr&oi=ao)
**Education**
· 2010 – French Accreditation to supervise research and PhD students - French “Habilitation Diploma” - Université Henri Poincaré – Nancy 1 (France)
· 1995 – PhD in Electrical Engineering, Institut National Polytechnique de Lorraine, Nancy, France.
· 1991 – Diplôme d’études Approfondies (DEA), Procédés et Traitement de l’énergie électrique (PROTEE), Institut National Polytechnique de Lorraine, Nancy, France.
· 1991 – Engineer Diploma – Ecole Nationale Supérieure d’Electricité et de Mécanique (ENSEM) - Institut National Polytechnique de Lorraine, Nancy, France.
**Positions**
· 2020 – Full Professor at the Faculty of Sciences and Technologies of the Université de Lorraine.
· 2004-2020 – Associate professor at the Faculty of Sciences and Technologies of the Université de Lorraine.
· 1995-2004 – Associate professor at Université de Strasbourg 1.
· 1992-1995 – Research and Teaching assistant at the Institut National Polytechnique de Lorraine, Nancy, France.
Publications
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Design methodology of VLSI power electronics digital controller based on Matlab-Modelsim co-simulation2008 IEEE International Symposium on Industrial Electronics (ISIE 2008), Jun 2008, Cambridge, United Kingdom. pp.1751-1756, ⟨10.1109/ISIE.2008.4676983⟩
Communication dans un congrès
hal-03565776v1
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FPGA-based hardware in the loop validation for fault tolerant three-phase active filter2008 IEEE International Symposium on Industrial Electronics (ISIE 2008), Jun 2008, Cambridge, United Kingdom. pp.2189-2194, ⟨10.1109/ISIE.2008.4676980⟩
Communication dans un congrès
hal-03565790v1
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High performances reference current generation for shunt active filter under distorted and unbalanced conditions2008 IEEE Power Electronics Specialists Conference - PESC 2008, Jun 2008, Rhodes, Greece. pp.195-201, ⟨10.1109/PESC.2008.4591924⟩
Communication dans un congrès
hal-03565799v1
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A fault tolerant three-leg shunt active filter using FPGA for fast switch failure detection2008 IEEE Power Electronics Specialists Conference - PESC 2008, Jun 2008, Rhodes, Greece. pp.3342-3347, ⟨10.1109/PESC.2008.4592471⟩
Communication dans un congrès
hal-03565812v1
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Reference current generation without PLL for shunt active filter under distorted and unbalanced conditions2008 IEEE International Symposium on Industrial Electronics (ISIE 2008), Jun 2008, Cambridge, United Kingdom. pp.363-368, ⟨10.1109/ISIE.2008.4676985⟩
Communication dans un congrès
hal-03565792v1
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