- 13
- 1
- 1
- 1
Philippe Maurine
16
Documents
Identifiants chercheurs
- philippe-maurine
- Google Scholar : https://scholar.google.fr/citations?hl=fr&user=VduRIsgAAAAJ&view_op=list_works&sortby=pubdate
- IdRef : 144880717
- 0000-0002-9706-5710
- Google Scholar : https://scholar.google.fr/citations?user=VduRIsgAAAAJ&hl=fr
Présentation
Publications
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 16
- 16
- 15
- 11
- 2
- 2
- 2
- 16
- 1
- 3
- 3
- 7
- 3
Delay Bounds Based Constraint Distribution MethodIEE Proceedings - Computers and Digital Techniques (1994-2006), 2005, 152 (6), pp.765-770. ⟨10.1049/ip-cdt:20050026⟩
Article dans une revue
lirmm-00105370v1
|
|
Low Power Oriented CMOS Circuit Optimization ProtocolDATE 2005 - 8th Design, Automation and Test in Europe Conference and Exhibition, Mar 2005, Munich, Germany. pp.640-645, ⟨10.1109/DATE.2005.202⟩
Communication dans un congrès
lirmm-00106452v1
|
Protocole d'Optimisation de Circuit CMOS Orienté Basse PuissanceFTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.17-22
Communication dans un congrès
lirmm-00106002v1
|
|
|
Optimization Protocol Based on Performance MetricDCIS 2004 - 19th International Conference on Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.964-968
Communication dans un congrès
lirmm-00108935v1
|
|
Delay Bound Based CMOS Gate Sizing TechniqueISCAS: International Symposium on Circuits and Systems, May 2004, Vancouver, BC, Canada. pp.189-192, ⟨10.1109/ISCAS.2004.1329494⟩
Communication dans un congrès
lirmm-00108856v1
|
|
Performance Metric Based Optimization ProtocolPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.100-109, ⟨10.1007/978-3-540-30205-6_12⟩
Communication dans un congrès
lirmm-00108892v1
|
|
CMOS Gate Sizing under Delay ConstraintPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Torino, Italy. pp.60-69, ⟨10.1007/978-3-540-39762-5_8⟩
Communication dans un congrès
lirmm-00244021v1
|
|
Dimensionnement de Portes CMOS Sous Contrainte de DélaiFTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.111-117
Communication dans un congrès
lirmm-00269522v1
|
Timing Performance Representation of a CMOS Standard Cell LibraryDCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. pp.83-88
Communication dans un congrès
lirmm-00239460v1
|
|
Metric Definition for Circuit Speed OptimizationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. pp.451-460
Communication dans un congrès
lirmm-00269568v1
|
|
Metric Definition for Circuit Speed OptimizationIWLS: International Workshop on Logic Synthesis, May 2003, Laguna Beach, CA, United States
Communication dans un congrès
lirmm-00269689v1
|
|
|
Définition d'une Métrique d'Insertion de BuffersFTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.131-136
Communication dans un congrès
lirmm-00269520v1
|
|
Continuous Representation of the Performance of a CMOS LibraryESSCIRC: European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal. pp.595-598, ⟨10.1109/ESSCIRC.2003.1257205⟩
Communication dans un congrès
lirmm-00239459v1
|
|
Evaluation et Optimisation de Chemins CombinatoiresColloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.173-176
Communication dans un congrès
lirmm-00269329v1
|
Gate Speed Improvement at Minimal Power DissipationAPPCAS: Asia-Pacific Conference on Circuits and Systems, Oct 2002, Denpasar, Bali, pp.278-282
Communication dans un congrès
lirmm-00239453v1
|
|
Metric Definition for Buffer InsertionDCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.307-312
Communication dans un congrès
lirmm-00239458v1
|