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Philippe Maurine
12
Documents
Identifiants chercheurs
- philippe-maurine
- Google Scholar : https://scholar.google.fr/citations?hl=fr&user=VduRIsgAAAAJ&view_op=list_works&sortby=pubdate
- IdRef : 144880717
- 0000-0002-9706-5710
- Google Scholar : https://scholar.google.fr/citations?user=VduRIsgAAAAJ&hl=fr
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On-Chip Process Variability Monitoring FlowJournal of Low Power Electronics, 2010, 6 (4), pp.601-606. ⟨10.1166/jolpe.2010.1109⟩
Article dans une revue
lirmm-00546368v1
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Timing Margin Evaluation with a Simple Statistical Timing Analysis FlowJournal of Embedded Computing, 2009, 3 (3), pp.221-229. ⟨10.3233/JEC-2009-0094⟩
Article dans une revue
lirmm-00371162v1
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On-Chip Process Variability MonitoringVARI: Workshop on CMOS Variability, May 2010, Montpellier, France
Communication dans un congrès
lirmm-00546337v1
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Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPCICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.82-85, ⟨10.1109/ICICDT.2010.5510289⟩
Communication dans un congrès
lirmm-00546316v1
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On-Chip Process Variability MonitoringDATE: Design, Automation and Test in Europe, Apr 2009, Nice, France
Communication dans un congrès
lirmm-00374368v1
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Product On-Chip Process Compensation for Low Power and Yield EnhancementPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.247-255, ⟨10.1007/978-3-642-11802-9_29⟩
Communication dans un congrès
lirmm-00433504v1
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Temperature and Voltage Aware Timing Analysis: Application to Voltage DropsDATE: Design, Automation and Test in Europe, Mar 2007, Nice, France. ⟨10.1109/DATE.2007.364426⟩
Communication dans un congrès
lirmm-00178525v1
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Timing Analysis in Presence of Voltage Drops and Temperature GradientsTAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. pp.28-34
Communication dans un congrès
lirmm-00106705v1
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Timing Analysis in Presence of Supply Voltage and Temperature VariationsISPD: International Symposium on Physical Design, Apr 2006, San Jose, CA, United States. pp.10-16, ⟨10.1145/1123008.1123012⟩
Communication dans un congrès
lirmm-00102760v1
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Temperature Dependency in UDSM ProcessPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.693-703, ⟨10.1007/11556930_71⟩
Communication dans un congrès
lirmm-00106077v1
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Physical Extension of the Logical Effort ModelPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.838-848, ⟨10.1007/978-3-540-30205-6_86⟩
Communication dans un congrès
lirmm-00108895v1
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Temperature Dependence in Low Power CMOS UDSM ProcessPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.111-118, ⟨10.1007/978-3-540-30205-6_13⟩
Communication dans un congrès
lirmm-00108893v1
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