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Philippe Maurine

12
Documents
Identifiants chercheurs
  • IdHAL philippe-maurine
  • Google Scholar : https://scholar.google.fr/citations?hl=fr&user=VduRIsgAAAAJ&view_op=list_works&sortby=pubdate
  • IdRef : 144880717
  • ORCID 0000-0002-9706-5710
  • Google Scholar : https://scholar.google.fr/citations?user=VduRIsgAAAAJ&hl=fr

Présentation

Publications

884985

On-Chip Process Variability Monitoring

Nabila Moubdi , Philippe Maurine , Robin M. Wilson , Nadine Azemard , Vincent Dumettier
VARI: Workshop on CMOS Variability, May 2010, Montpellier, France
Communication dans un congrès lirmm-00546337v1

Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPC

Nabila Moubdi , Philippe Maurine , Nadine Azemard , Robin M. Wilson , Sylvain Engels
ICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.82-85, ⟨10.1109/ICICDT.2010.5510289⟩
Communication dans un congrès lirmm-00546316v1

On-Chip Process Variability Monitoring

Nabila Moubdi , Robin M. Wilson , Sylvain Engels , Nadine Azemard , Philippe Maurine
DATE: Design, Automation and Test in Europe, Apr 2009, Nice, France
Communication dans un congrès lirmm-00374368v1
Image document

Product On-Chip Process Compensation for Low Power and Yield Enhancement

Nabila Moubdi , Philippe Maurine , Robin M. Wilson , Nadine Azemard , Vincent Dumettier
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.247-255, ⟨10.1007/978-3-642-11802-9_29⟩
Communication dans un congrès lirmm-00433504v1

Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops

Benoit Lasbouygues , Robin M. Wilson , Nadine Azemard , Philippe Maurine
DATE: Design, Automation and Test in Europe, Mar 2007, Nice, France. ⟨10.1109/DATE.2007.364426⟩
Communication dans un congrès lirmm-00178525v1

Timing Analysis in Presence of Voltage Drops and Temperature Gradients

Benoit Lasbouygues , Robin M. Wilson , Nadine Azemard , Philippe Maurine
TAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. pp.28-34
Communication dans un congrès lirmm-00106705v1

Timing Analysis in Presence of Supply Voltage and Temperature Variations

Benoit Lasbouygues , Robin M. Wilson , Nadine Azemard , Philippe Maurine
ISPD: International Symposium on Physical Design, Apr 2006, San Jose, CA, United States. pp.10-16, ⟨10.1145/1123008.1123012⟩
Communication dans un congrès lirmm-00102760v1
Image document

Temperature Dependency in UDSM Process

Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.693-703, ⟨10.1007/11556930_71⟩
Communication dans un congrès lirmm-00106077v1
Image document

Physical Extension of the Logical Effort Model

Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.838-848, ⟨10.1007/978-3-540-30205-6_86⟩
Communication dans un congrès lirmm-00108895v1
Image document

Temperature Dependence in Low Power CMOS UDSM Process

Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.111-118, ⟨10.1007/978-3-540-30205-6_13⟩
Communication dans un congrès lirmm-00108893v1