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Philippe Maurine
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Documents
Identifiants chercheurs
philippe-maurine- Google Scholar : https://scholar.google.fr/citations?hl=fr&user=VduRIsgAAAAJ&view_op=list_works&sortby=pubdate
- IdRef : 144880717
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0000-0002-9706-5710
- Google Scholar : https://scholar.google.fr/citations?user=VduRIsgAAAAJ&hl=fr
Présentation
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On-Chip Process Variability Monitoring FlowJournal of Low Power Electronics, 2010, 6 (4), pp.601-606. ⟨10.1166/jolpe.2010.1109⟩
Article dans une revue
lirmm-00546368v1
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Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPCICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.82-85, ⟨10.1109/ICICDT.2010.5510289⟩
Communication dans un congrès
lirmm-00546316v1
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On-Chip Process Variability MonitoringVARI: Workshop on CMOS Variability, May 2010, Montpellier, France
Communication dans un congrès
lirmm-00546337v1
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Product On-Chip Process Compensation for Low Power and Yield EnhancementPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.247-255, ⟨10.1007/978-3-642-11802-9_29⟩
Communication dans un congrès
lirmm-00433504v1
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On-Chip Process Variability MonitoringDATE: Design, Automation and Test in Europe, Apr 2009, Nice, France
Communication dans un congrès
lirmm-00374368v1
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