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Philippe Maurine
14
Documents
Identifiants chercheurs
- philippe-maurine
- Google Scholar : https://scholar.google.fr/citations?hl=fr&user=VduRIsgAAAAJ&view_op=list_works&sortby=pubdate
- IdRef : 144880717
- 0000-0002-9706-5710
- Google Scholar : https://scholar.google.fr/citations?user=VduRIsgAAAAJ&hl=fr
Présentation
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On-Chip Process Variability Monitoring FlowJournal of Low Power Electronics, 2010, 6 (4), pp.601-606. ⟨10.1166/jolpe.2010.1109⟩
Article dans une revue
lirmm-00546368v1
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Timing Margin Evaluation with a Simple Statistical Timing Analysis FlowJournal of Embedded Computing, 2009, 3 (3), pp.221-229. ⟨10.3233/JEC-2009-0094⟩
Article dans une revue
lirmm-00371162v1
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A Comprehensive Performance Macro-Modeling of on-Chip RC Interconnects Considering Line Shielding EffectsIntegration, the VLSI Journal, 2006, 39 (4), pp.433-456. ⟨10.1016/j.vlsi.2005.08.007⟩
Article dans une revue
lirmm-00106854v1
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Logical Effort Model Extension to Propagation Delay RepresentationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25 (9), pp.1677-1684. ⟨10.1109/TCAD.2005.857400⟩
Article dans une revue
lirmm-00104315v1
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On-Chip Process Variability MonitoringVARI: Workshop on CMOS Variability, May 2010, Montpellier, France
Communication dans un congrès
lirmm-00546337v1
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Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPCICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.82-85, ⟨10.1109/ICICDT.2010.5510289⟩
Communication dans un congrès
lirmm-00546316v1
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On-Chip Process Variability MonitoringDATE: Design, Automation and Test in Europe, Apr 2009, Nice, France
Communication dans un congrès
lirmm-00374368v1
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Product On-Chip Process Compensation for Low Power and Yield EnhancementPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.247-255, ⟨10.1007/978-3-642-11802-9_29⟩
Communication dans un congrès
lirmm-00433504v1
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A Simple Statistical Timing Analysis Flow and its Application to Timing Margin EvaluationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.138-147, ⟨10.1007/978-3-540-74442-9_14⟩
Communication dans un congrès
lirmm-00175076v1
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A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin EvaluationFTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.19-25
Communication dans un congrès
lirmm-00178454v1
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Statistical Characterization of Library Timing PerformancePATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2006, Montpellier, France. pp.468-476, ⟨10.1007/11847083_45⟩
Communication dans un congrès
lirmm-00093233v1
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Timing Performance Representation of a CMOS Standard Cell LibraryDCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. pp.83-88
Communication dans un congrès
lirmm-00239460v1
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Continuous Representation of the Performance of a CMOS LibraryESSCIRC: European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal. pp.595-598, ⟨10.1109/ESSCIRC.2003.1257205⟩
Communication dans un congrès
lirmm-00239459v1
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Représentation Unifiée des Performances Temporelles d'une Bibliothèque de Cellules StandardsFTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.119-124
Communication dans un congrès
lirmm-00269519v1
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