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Philippe Maurine
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Documents
Identifiants chercheurs
- philippe-maurine
- Google Scholar : https://scholar.google.fr/citations?hl=fr&user=VduRIsgAAAAJ&view_op=list_works&sortby=pubdate
- IdRef : 144880717
- 0000-0002-9706-5710
- Google Scholar : https://scholar.google.fr/citations?user=VduRIsgAAAAJ&hl=fr
Présentation
Publications
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Enhancing Electromagnetic Analysis Using Magnitude Squared IncoherenceIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012, 20 (3), pp.573-577. ⟨10.1109/TVLSI.2011.2104984⟩
Article dans une revue
lirmm-00761786v1
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Timing Slack Monitoring under Process and Environmental Variations: Application to a DSP Performance OptimizationMicroelectronics Journal, 2011, 42 (5), pp.718-732. ⟨10.1016/j.mejo.2011.02.005⟩
Article dans une revue
lirmm-00607877v1
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Secure Triple Track Logic Robustness Against Differential Power and Electromagnetic AnalysesJournal of Integrated Circuits and Systems, 2009, 4 (1), pp.20-28. ⟨10.29292/jics.v4i1.293⟩
Article dans une revue
lirmm-03613238v1
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Compact and Secured Primitives for the Design of Asynchronous CircuitsJournal of Low Power Electronics, 2005, 1 (1), pp.20-26. ⟨10.1166/jolpe.2005.009⟩
Article dans une revue
lirmm-00105365v1
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Differential Power Analysis Enhancement with Statistical PreprocessingDATE: Design, Automation and Test in Europe, 2010, Dresden, Germany. pp.1301-1304, ⟨10.1109/DATE.2010.5457007⟩
Communication dans un congrès
lirmm-00548738v1
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Spatial EM Jamming: a Countermeasure Against EM Analysis ?VLSI-SoC'10: 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, Madrid, Spain. pp.105-110
Communication dans un congrès
lirmm-00544358v1
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Incoherence Analysis and its Application to Time Domain EM Analysis of Secure CircuitsAPEMC 2010 - Asia-Pacific Symposium on Electromagnetic Compatibility, Apr 2010, Beijing, China. pp.1039-1042, ⟨10.1109/APEMC.2010.5475481⟩
Communication dans un congrès
lirmm-00607894v1
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Evaluation on FPGA of Triple Rail Logic Robustness Against DPA and DEMADATE: Design, Automation and Test in Europe, 2009, Nice, France. pp.634-639, ⟨10.1109/DATE.2009.5090744⟩
Communication dans un congrès
lirmm-00372847v1
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On-Chip Timing Slack MonitoringVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2009, Florianopolis, Brazil. pp.89-94, ⟨10.1109/VLSISOC.2009.6041336⟩
Communication dans un congrès
lirmm-00429350v1
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Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variationsFTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Suisse
Communication dans un congrès
lirmm-00404810v1
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Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of VariabilitiesPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.266-275, ⟨10.1007/978-3-642-11802-9_31⟩
Communication dans un congrès
lirmm-00433462v1
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Enhancing Electromagnetic Attacks using Spectral Coherence based CartographyVLSI-SoC 2009 - 17th IFIP International Conference on Very Large Scale Integration, Oct 2009, Florianopolis, Brazil. pp.11-16, ⟨10.1109/VLSISOC.2009.6041323⟩
Communication dans un congrès
lirmm-00429342v1
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An Innovative Timing Slack Monitor for Variation Tolerant CircuitsICICDT: International Conference on IC Design & Technology, May 2009, Austin, TX, United States. pp.215-218, ⟨10.1109/ICICDT.2009.5166299⟩
Communication dans un congrès
lirmm-00371174v1
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Evaluating the Robustness of Secure Triple Track Logic Through PrototypingSBCCI'08: Symposium on Integrated Circuits and Systems Design, Sep 2008, Gramado, Brazil, France. pp.193-198, ⟨10.1145/1404371.1404425⟩
Communication dans un congrès
lirmm-00373516v1
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Setup and Hold Timing Violations Induced by Process Variations, in a Digital MultiplierISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩
Communication dans un congrès
lirmm-00280809v1
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Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability AspectsISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, pp.310-315
Communication dans un congrès
lirmm-00280716v1
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Prototyping Secure Triple Track Logic (STTL) Robustness Against DPA & DEMA on FPGACryptArchi: Cryptographic Architectures, Jun 2008, Tregastel, France
Communication dans un congrès
lirmm-00373539v1
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A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAMDELTA 2008 - 4th IEEE International Symposium on Electronic Design, Test and Applications, Jan 2008, Hong Kong, China. pp.107-110, ⟨10.1109/DELTA.2008.72⟩
Communication dans un congrès
lirmm-00243966v1
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Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numériqueFTFC: Faible Tension - Faible Consommation, May 2008, Louvain-La-Neuve, Belgique
Communication dans un congrès
lirmm-00283731v1
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Triple Rail Logic Robustness against DPAReConFig 2008 - International Conference on Reconfigurable Computing and FPGAs, Dec 2008, Cancun, Mexico. pp.415-420, ⟨10.1109/ReConFig.2008.75⟩
Communication dans un congrès
lirmm-00350573v1
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Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétiqueJNRDM 2008 - 11e Journées Nationales du Réseau Doctoral de Microélectronique, May 2008, Bordeaux, France
Communication dans un congrès
lirmm-00281175v2
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Variabilité de Process et Performances des Mémoires SRAM EmbarquéesFTFC'07: 6èmes Journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France, pp.7-11
Communication dans un congrès
lirmm-00178319v1
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Process Variability Considerations in the Design of an eSRAMMTDT 2007 - IEEE International Workshop on Memory Technology, Design and Testing, Dec 2007, Taipei, Taiwan. pp.23-26, ⟨10.1109/MTDT.2007.4547609⟩
Communication dans un congrès
lirmm-00275258v1
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Méthodologie d'estimation de l'influence de la variabilité sur un opérateur numériqueFTFC 2007 - 6e journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France
Communication dans un congrès
lirmm-00204621v1
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Process Variabilities and Performances in a 90nm embedded SRAMIEEE International Integrated Reliability Workshop, Oct 2007, pp.050-055
Communication dans un congrès
lirmm-00198373v1
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Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPAPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.340-351, ⟨10.1007/978-3-540-74442-9_33⟩
Communication dans un congrès
lirmm-00175100v1
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Improvement of Dual Rail Logic as a Countermeasure Against DPAVLSI-SoC 2007 - IFIP International Conference on Very Large Scale Integration, Oct 2007, Atlanta, GA, United States. pp.270-275, ⟨10.1109/VLSISOC.2007.4402510⟩
Communication dans un congrès
lirmm-00186174v1
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Security Evaluation of Dual Rail Logic Against DPA AttacksVLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration, Oct 2006, Nice, France. pp.181-186, ⟨10.1109/VLSISOC.2006.313230⟩
Communication dans un congrès
lirmm-00109692v1
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Asynchronous Dual rail Cells to Secure Cryptosystem Against Side Channel AttacksSAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia-Antipolis
Communication dans un congrès
lirmm-00106539v1
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La Technologie Asynchrone QDI pour la Sécurité des CryptosystèmesJNRDM 2005 - 8e Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France. pp.461-463
Communication dans un congrès
lirmm-00106530v1
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Méthode de Conception de Primitives Asynchrones Double RailFTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.23-27
Communication dans un congrès
lirmm-00106003v1
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Design of Compact Dual Rail Asynchronous PrimitivesDCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, 2005, Lisbonne, Portugal
Communication dans un congrès
lirmm-00106434v1
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A Method to Design Compact Dual-rail Asynchronous PrimitivesPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.571-580, ⟨10.1007/11556930_58⟩
Communication dans un congrès
hal-00105846v1
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Conception et Modélisation de Briques Elémentaires CMOSCNFM'04 : 8ème Journées Pédagogiques du Comité National de Formation en Microélectronique, 2004, Saint-Malo, France. pp.35-37
Communication dans un congrès
lirmm-00108672v1
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Automatic Layout Synthesis Based Performance OptimizationIWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85
Communication dans un congrès
lirmm-00108654v1
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Design Optimization with Automated Cell GenerationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.722-731, ⟨10.1007/978-3-540-30205-6_74⟩
Communication dans un congrès
lirmm-00108894v1
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Secured Structures for Secured Asynchronous QDI CircuitsDCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France
Communication dans un congrès
hal-01393250v1
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Towards Autonomous Scalable Integrated SystemsDesign Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. ⟨10.1007/978-94-007-1125-9_4⟩
Chapitre d'ouvrage
lirmm-01399454v1
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Side Channel AttacksSecurity Trends for FPGAS
Chapitre d'ouvrage
lirmm-00809329v1
From Secured to Secure Reconfigurable Systems, Springer, pp.47-72, 2011, 978-94-007-1337-6. ⟨10.1007/978-94-007-1338-3_3⟩ |
Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA AttacksNadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.634-644, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. ⟨10.1007/11847083_44⟩
Chapitre d'ouvrage
lirmm-00109844v1
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