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154 résultats
Improving Storage of Patterns in Binary Cluster-Based Neural Networks: Clone-based Model and ArchitectureInternationnal workshop on Neural Coding, co-located with DATE Conference 2015, Mar 2015, Grenoble, France
Communication dans un congrès
hal-01101583v1
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Algorithm and Implementation of an Associative Memory for Oriented Edge Detection Using Improved Clustered Neural Networks2015 International Symposium on Circuits and Systems (ISCAS 2015), May 2015, Lisbonne, Portugal. pp.2501 - 2504, ⟨10.1109/ISCAS.2015.7169193⟩
Communication dans un congrès
hal-02116052v1
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Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAsDesign, Automation and Test in Europe Conference (DATE), Mar 2019, Florence, Italy
Communication dans un congrès
hal-02086145v1
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Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGAInternational Conference on Field Programmable Logic and Applications, Aug 2009, Italy. pp.464-468
Communication dans un congrès
hal-00663229v1
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Synthèse d'Interface de Communication pour les Composants VirtuelsMicro et nanotechnologies/Microélectronique. Université de Bretagne Sud, 2003. Français. ⟨NNT : ⟩
Thèse
tel-00077867v1
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Virtual Component IP Re-use in Telecommunication Systems Design: A Case Study of MPEG-2 / JPEG2000 Encoder2002, pp.733-736
Communication dans un congrès
hal-00077869v1
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Intégration Optimisée de Composants Virtuels orientés TDSI par la Synthèse d'Architecture2003, pp.353-358
Communication dans un congrès
hal-00077863v1
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Réseaux de clusters de neurones restreintsGRETSI 2015 : 25ème colloque du Groupement de Recherche en Traitement du Signal et des Images, Sep 2015, Lyon, France. pp.1 - 5
Poster de conférence
hal-01325893v1
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A Methodology based on Transportation Problem Modeling for Designing Parallel Interleaver Architectures36th IEEE International Conference on Acoustics, Speech and Signal Processing, May 2011, Prague, Czech Republic. pp.XX-YY
Communication dans un congrès
hal-00592669v1
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A memory Mapping Approach for Parallel Interleaver design with multiples read and write accessesIEEE International Symposium on Circuits and Systems (ISCAS), May 2010, Paris, France. page 3168-3171, ⟨10.1109/ISCAS.2010.5537955⟩
Communication dans un congrès
hal-00482682v1
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Energy Efficient Hardware Loop Based Optimization for CGRAsJournal of Signal Processing Systems, In press, ⟨10.1007/s11265-022-01760-9⟩
Article dans une revue
hal-03704229v1
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Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSIGRETSI'05 (Colloque sur le Traitement du Signal et de l'Image), 2005, LOUVAIN LA NEUVE, Belgique. pp.779-782
Communication dans un congrès
hal-00077384v1
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Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporelsColloque national du GRETSI, Groupe de Recherche et d'Etudes du Traitement du Signal, Sep 2007, Troyes, France
Communication dans un congrès
hal-00490210v1
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A Dynamically Reconfigurable ECC Decoder Architecture for the next generation communication standards (5G, SDR and behond)WInnComm Europe, Oct 2016, Paris, France
Communication dans un congrès
hal-01344550v1
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Clone-Based Encoded Neural Networks to Design Efficient Associative MemoriesIEEE Transactions on Neural Networks and Learning Systems, 2019, 30 (10), pp.1-14. ⟨10.1109/TNNLS.2018.2890658⟩
Article dans une revue
hal-02060021v1
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Algorithm and Implementation of an Associative Memory for Oriented Edge Detection Using Improved Clustered Neural NetworksColloque national du GdR BioCOmp, Oct 2015, Saint Paul de Vence, France
Poster de conférence
hal-02511244v1
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Algorithm and Implementation of an Associative Memory for Oriented Edge Detection Using Improved Clustered Neural NetworksInternational Workshop on Neuromorphic and Brain-Based Computing Systems (Neucomp), Mar 2015, Grenoble, France
Poster de conférence
hal-02511239v1
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Improving storage of patterns in recurrent neural networks: Clone-based model and architecture2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 2015, Lisbon, France. pp.577-580, ⟨10.1109/ISCAS.2015.7168699⟩
Communication dans un congrès
hal-02511108v1
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A Design Methodology for Integrating IP into SOC Systems2002, pp.307-310
Communication dans un congrès
hal-00077876v1
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VLSI Architectures and NoCs for Neural Coding1st International Symposium on Brainware LSI, Mar 2014, Japan
Communication dans un congrès
hal-01009489v1
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From Software Code to Hardware: Directions in High-Level SynthesisInternational Workshop on "Electronic System-Level Design towards Heterogeneous Computing", IEEE Design Automation and Test in Europe DATE, March 2014, Mar 2014, Germany
Communication dans un congrès
hal-01009493v1
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Constrained algorithmic IP design for system-on-chipIntegration, the VLSI Journal, 2007, 40 (2), pp.XX-XX
Article dans une revue
hal-00153087v1
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Designing Parallel Interleaver architecture through Tripartite Edge Coloring ApproachGDR SoC-SiP, Jun 2011, lyon, France
Communication dans un congrès
hal-00682201v1
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An Approach Based on Edge Coloring of Tripartite Graph for Designing Parallel LDPC Interleaver ArchitectureIEEE International Symposium on Circuits and Systems (ISCAS) 2011, May 2011, Rio de Janeiro, Brazil. pp.XX-YY
Communication dans un congrès
hal-00592617v1
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Communication and Timing Constraints Analysis for IP Design and Integration2003, pp.38-43
Communication dans un congrès
hal-00077861v1
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∂ GAUT: A High-Level Synthesis Tool for DSP applicationsPhilippe Coussy & Adam Morawiec. High-Level Synthesis: From Algorithm to Digital Circuits, Springer, pp.147-170, 2008
Chapitre d'ouvrage
hal-00369029v1
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Design Approach to Automatically Synthesize ANSI-C Assertions during High-Level Synthesis of Hardware AcceleratorsICSAS 2014 - International symposium on circuits and systems, Jun 2014, Melbourne, Australia
Communication dans un congrès
hal-01009572v1
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An Introduction to High-Level SynthesisIEEE Design & Test, 2009, 26 (4), pp.8-17
Article dans une revue
hal-00447325v1
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Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment2019 Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Mar 2019, Florence, Italy
Communication dans un congrès
hal-02052433v1
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Amélioration des performances des mémoires associatives par les réseaux à clonesColloque national du GdR SoC-SiP, Jun 2016, Nantes, France
Communication dans un congrès
hal-01318028v1
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