Nombre de documents

107

Pierre Boulet, professeur d'informatique à l'Université de Lille, directeur adjoint de CRIStAL


Article dans une revue20 documents

  • Mohammed Kamel Benhaoua, Amitkumar Singh, Abou El Hassan Benyamina, Pierre Boulet. DynMapNoCSIM : A Dynamic Mapping SIMULATOR for Network on Chip based MPSoC. Journal of Digital Information Management, 2015, 13 (1), pp.45--54. <hal-01198992>
  • Mahyar Shahsavari, M Faisal Nadeem, S Arash Ostadzadeh, Philippe Devienne, Pierre Boulet. Unconventional digital computing approach: memristive nanodevice platform. physica status solidi (c), Wiley, 2015, Issue physica status solidi (c) physica status solidi (c) Special Issue: E-MRS 2014 Spring Meeting – Symposium E • E-MRS 2014 Spring Meeting – Symposium F • E-MRS 2014 Spring Meeting – Symposium S, 12 (1-2), pp.222 - 228. <http://onlinelibrary.wiley.com/doi/10.1002/pssc.201400069/abstract>. <10.1002/pssc.201400069>. <hal-01116577>
  • Mohammed Kamel Benhaoua, Amit Kumar Singh, Abou El Hassan Benyamin, Akash Kumar, Pierre Boulet. Heuristic for Accelerating Run-Time Task Mapping in NoC-based Heterogeneous MPSoCs. Journal of Digital Information Management, 2014, 12 (5), pp.298--308. <hal-01198994>
  • Abbou El Hassen Benyamina, Mohammed Benhaoua, Pierre Boulet. Heuristics for Routing and Spiral Run-time Task Mapping in NoC-based Heterogeneous MPSOCs. International Journal of Computer Science Issues, IJCSI Press, 2013, 10 (4), pp.233--238. <hal-01198995>
  • Calin Glitia, Julien Deantoni, Frédéric Mallet, Jean-Vivien Millo, Pierre Boulet, et al.. Progressive and explicit refinement of scheduling for multidimensional data-flow applications using uml marte. Design Automation for Embedded Systems, Springer Verlag, 2012, 16 (2), pp.137-169. <http://www.springerlink.com/content/t03t7nl8463tjpr4/?MUD=MP>. <10.1007/s10617-012-9093-y>. <hal-00727239>
  • Majdi Elhaji, Pierre Boulet, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, et al.. System level modeling methodology of NoC design from UML-MARTE to VHDL. Design Automation for Embedded Systems, Springer Verlag, 2012, pp.1--27. <10.1007/s10617-012-9101-2>. <hal-00797601>
  • Imran Rafiq Quadri, Abdoulaye Gamatié, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser. Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: advantages, limitations and alternatives. Journal of Systems Architecture, Elsevier, 2012, <10.1016/j.sysarc.2012.01.001>. <hal-00666014>
  • Pierre Boulet. Modélisation et analyse de systèmes embarqués ou temps-réel avec le profil UML MARTE. Techniques de l'Ingenieur, Techniques de l'ingénieur, 2011, <http://www.techniques-ingenieur.fr/base-documentaire/electronique-photonique-th13/innovations-electronique-et-tic-ti358/modelisation-et-analyse-de-systemes-embarques-ou-temps-reel-avec-le-profil-uml-marte-in120/>. <inria-00587386>
  • Calin Glitia, Pierre Boulet, Eric Lenormand, Michel Barreteau. Repetitive model refactoring strategy for the design space exploration of intensive signal processing applications. Journal of Systems Architecture, Elsevier, 2011, 57 (9), pp.815-829. <10.1016/j.sysarc.2010.12.002>. <inria-00605069>
  • Calin Glitia, Philippe Dumont, Pierre Boulet. Array-OL with delays, a domain specific specification language for multidimensional intensive signal processing. Multidimensional Systems and Signal Processing, Springer Verlag, 2009, 21 (2), pp.105--131. <10.1007/s11045-009-0085-4>. <inria-00522751>
  • Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser. Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems. Scalable Computing : Practice and Experience, West University of Timisoara, 2009, 10 (2). <inria-00565260>
  • Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser. Synchronous Modeling and Analysis of Data Intensive Applications. EURASIP Journal on Embedded Systems, SpringerOpen, 2008, 2008 (1), pp.561863. <10.1155/2008/561863>. <hal-00784459>
  • Abou El Hassan Benyamina, Pierre Boulet. Multi-objective Mapping for NoC Architecture. Journal of Digital Information Management, Digital Information Research Foundation, 2007, 5 (6), pp.378--384. <inria-00565156>
  • Abdelkader Amar, Pierre Boulet, Jean-Luc Dekeyser. Towards Distributed Process Networks with CORBA. Parallel and Distributed Computing Practices, Nova Science, 2002, 5 (4). <inria-00565180>
  • Pierre Boulet, Xavier Redon. SPPoC: manipulation automatique de polyèdres pour la compilation. Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, Lavoisier, 2001, 20 (8), pp.1019-1048. <inria-00565187>
  • Pierre Boulet, Jack J. Dongarra, Yves Robert, Frédéric Vivien. Static Tiling for Heterogeneous Computing Platforms. Parallel Computing, Elsevier, 1999, 25 (5), pp.547-568. <inria-00565004>
  • Pierre Boulet, Jack J. Dongarra, Fabrice Rastello, Yves Robert, Frédéric Vivien. Algorithmic Issues on Heterogeneous Computing Platforms. Parallel Processing Letters, World Scientific Publishing, 1999, 9 (2), pp.197-213. <inria-00565003>
  • Pierre Boulet, Alain Darte, Georges-André Silber, Frédéric Vivien. Loop parallelization algorithms: From parallelism extraction to code generation. Parallel Computing, Elsevier, 1998, 24 (3-4), pp.421--444. <inria-00565000>
  • Vincent Bouchitté, Pierre Boulet, Alain Darte, Yves Robert. Evaluating array expressions on massively parallel machines with communication/computation overlap. International Journal of Supercomputer Applications and High Performance Computing, SAGE Publications, 1995, 9 (3), pp.205-219. <inria-00564991>
  • Pierre Boulet, Alain Darte, Tanguy Risset, Yves Robert. (Pen)-ultimate tiling?. Integration, the VLSI Journal, Elsevier, 1994, 17, pp.33-51. <inria-00564996>

Communication dans un congrès59 documents

  • Mahyar Shahsavari, Pierre Falez, Pierre Boulet. Combining a Volatile and Nonvolatile Memristor in Artificial Synapse to Improve Learning in Spiking Neural Networks. NANOARCH 2016 - 12th ACM/IEEE International Symposium on Nanoscale Architectures, Jul 2016, Beijing, China. 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2016, <http://www.nanoarch.org/16/>. <10.1145/2950067.2950090>. <hal-01368954>
  • Houssam Eddine Zahaf, Abou El Hassan Benyamina, Richard Olejnik, Giuseppe Lipari, Pierre Boulet. Modeling Parallel Real-time Tasks with Di-Graphs. ACM. RTNS '16 - Proceedings of the 24th International Conference on Real-Time Networks and Systems , Oct 2016, Brest, France. pp.349-358, RTNS '16. <http://rtns16.univ-brest.fr/#page=home>. <10.1145/2997465.2997475>. <hal-01393159>
  • Amine El Kouhen, Abdelouahed Gherbi, Cedric Dumoulin, Pierre Boulet, Sébastien Gerard. MID: A MetaCASE Tool For A Better Reuse Of Visual Notations. Daniel Amyot; Pau Fonseca i Casas; Gunter Mussbacher. 8th System Analysis and Modelling conference (SAM 2014), Sep 2014, Valencia, Spain. Springer, System Analysis and Modeling: Models and Reusability, 8769, pp.16-31, 2014, Lecture Notes in Computer Science (LNCS). <10.1007/978-3-319-11743-0_2>. <hal-01011899>
  • Amine El Kouhen, Cedric Dumoulin, Sébastien Gerard, Pierre Boulet. Specifez vos éditeurs de diagrammes à l'aide de composants réutilisables. 2ème Conférence en Ingénierie Logiciele (CIEL'13), Apr 2013, Nancy, France. 2013. <hal-00801235>
  • Amine El Kouhen, Sébastien Gerard, Cedric Dumoulin, Pierre Boulet. A Component-Based Approach for Specifying Reusable Visual Languages. 2013 IEEE Symposium on Visual Languages and Human-Centric Computing, Sep 2013, San José, CA, United States. IEEE, pp.135-138, 2013, <10.1109/VLHCC.2013.6645257>. <hal-00860909>
  • Amine El Kouhen, Cedric Dumoulin, Sébastien Gerard, Pierre Boulet. A Component-Based Approach for Specifying DSML's Concrete Syntax. Heiko Kern; Juha-Pekka Tolvanen; Paolo Bottoni. 2nd Workshop on Graphical Modeling Language Development (GMLD 2013), Jul 2013, Montpellier, France. ACM, pp.3-11, 2013, <10.1145/2489820.2489822>. <hal-00829173>
  • Asma Charfi Smaoui, Chokri Mraidha, Pierre Boulet. An Optimized Compilation of UML State Machines. ISORC - 15th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, Apr 2012, Shenzhen, China. 2012. <hal-00676943>
  • Jing Guo, Antonio Wendell De Oliveira Rodrigues, Jerarajan Thiyagalingam, Frédéric Guyomarch, Pierre Boulet, et al.. Harnessing the Power of GPUs without Losing Abstractions in SaC and ArrayOL: A Comparative Study. HIPS 2011, 16th International Workshop on High-Level Parallel Programming Models and Supportive Environments, May 2011, Anchorage (Alaska), United States. 2011. <inria-00569100>
  • Majdi Elhaji, Pierre Boulet, Rached Tourki, Abdelkrim Zitouni, Jean-Luc Dekeyser, et al.. Modeling Networks-on-Chip at System Level with the MARTE UML profile. M-BED'2011, Mar 2011, Grenoble, France. 2011. <inria-00569077>
  • Imran Rafiq Quadri, Abdoulaye Gamatié, Pierre Boulet, Jean-Luc Dekeyser. Modeling of Configurations for Embedded System Implementations in MARTE. 1st workshop on Model Based Engineering for Embedded Systems Design - Design, Automation and Test in Europe (DATE 2010), Mar 2010, Dresden, Germany. 2010. <inria-00486845>
  • M. Elhaji, Pierre Boulet, S. Meftali, A. Zitouni, J. Dekeyser, et al.. An MDE approach for modeling network on chip topologies. Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2010 5th International Conference on, Mar 2010, Hammamet, Tunisia. 2010, <10.1109/DTIS.2010.5487596>. <inria-00526629>
  • Abou El Hassan Benyamina, Pierre Boulet, A. Aroui, S. Eltar, Karima Dellal. Mapping Real Time Applications on NoC Architecture with Hybrid Multi-objective Algorithm. META'10 Intenational Conference on Metaheuristics and Nature Inspired Computing, Oct 2010, Djerba Island, Tunisia. 2010. <inria-00523969>
  • Rosilde Corvino, Abdoulaye Gamatié, Pierre Boulet. Architecture Exploration for Efficient Data Transfer and Storage in Data-Parallel Applications. Pasqua D'Ambra and Mario Guarracino and Domenico Talia. Euro-Par - 16th International Euro-Par Conference - 2010, Aug 2010, Ischia, Italy. Springer Berlin / Heidelberg, 6271, pp.101--116, 2010, LNCS. <10.1007/978-3-642-15277-1_11>. <inria-00522786>
  • A. Charfi, C. Mraidha, S. Gérard, F. Terrier, Pierre Boulet. Does Code Generation Promote or Prevent Optimizations?. IEEE Computer Society. Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), 2010 13th IEEE International Symposium on, May 2010, Parador of Carmona, Spain. pp.75--79, 2010, <10.1109/ISORC.2010.25>. <inria-00522661>
  • A. Charfi, C. Mraidha, S. Gerard, F. Terrier, Pierre Boulet. Toward optimized code generation through model-based optimization. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, Mar 2010, Dresden, Germany. pp.1313--1316, 2010, <http://www.date-conference.com/proceedings/PAPERS/2010/DATE10/PDFFILES/IP4_05.PDF>. <inria-00522657>
  • Calin Glitia, Pierre Boulet. Interaction between inter-repetition dependences and high-level transformations in Array-OL. Conference on Design and Architectures for Signal and Image Processing (DASIP 2009), 2009, Sophia Antipolis, France. 2009. <inria-00565261>
  • Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser. Using An MDE Approach for Modeling of Interconnection networks. The International Symposium on Parallel Architectures, Algorithms and Networks Conference (ISPAN 08), 2008, Sydney, Australia. 2008. <inria-00565155>
  • Calin Glitia, Pierre Boulet. High Level Loop Transformations for Multidimensional Signal Processing Embedded Applications. International Symposium on Systems, Architectures, MOdeling, and Simulation (SAMOS VIII), 2008, Samos, Greece. 2008. <inria-00565154>
  • Abou El Hassan Benyamina, Pierre Boulet. An Hybrid algorithm for Mapping on NoC Architectures. 2nd International Conference on Metaheuristics and Nature Inspired Computing, META'08, 2008, Hammamet, Tunisia. 2008. <inria-00565153>
  • Rabie Ben Atitallah, Philippe Marquet, Éric Piel, Samy Meftali, Smail Niar, et al.. Gaspard2: from MARTE to SystemC Simulation. Proceeedings of the DATE'08 workshop on Modeling and Analyzis of Real-Time and Embedded Systems with the MARTE UML profile, Mar 2008, Washington, United States. 2008. <inria-00524373>
  • Jean-Luc Dekeyser, Abdoulaye Gamatié, Anne Etien, Rabie Ben Atitallah, Pierre Boulet. Using the UML Profile for MARTE to MPSoC Co-Design. First International Conference on Embedded Systems & Critical Applications (ICESCA'08), May 2008, Tunis, Tunisia. 2008. <inria-00524363>
  • Pierre Boulet, Philippe Marquet, Éric Piel, Julien Taillard. Repetitive Allocation Modeling with MARTE. Forum on specification and design languages (FDL'07), 2007, Barcelona, Spain. 2007. <inria-00565160>
  • Souha Kamoun, Pierre Boulet. Model-Based Testing of the ERTMS System with SysML and MARTE. MoDeVVa'07, 2007, Nashville, United States. 2007. <inria-00565159>
  • Souha Kamoun, Pierre Boulet. Une approche modèle pour la génération de scénarios de tests : Application au système ERTMS/ETCS. Workshop International : Logistique and Transport 2007, 2007, Sousse, Tunisie. 2007. <inria-00565158>
  • Abou El Hassan Benyamina, Pierre Boulet. Multi-objective Mapping for NoC Architectures. 1st International Conference on Digital Communications and Computer Applications, 2007, Irbid, Jordan. pp.132-139, 2007. <inria-00565162>
  • Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Pierre Boulet, Jean-Luc Dekeyser. Vers des transformations d'applications à parallélisme de données en équations synchrones. 9ème édition de SYMPosium en Architectures nouvelles de machines, Oct 2006, Perpignan, France, 2006. <inria-00124125>
  • Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, Éric Rutten. UML2 Profile for Modeling Controlled Data Parallel Applications. Forum on specification and Design Languages (FDL'06), 2006, Darmstadt, Germany. 2006. <inria-00565164>
  • Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Pierre Boulet, Jean-Luc Dekeyser. Synchronous Modeling of Data-Intensive Applications. International Open Workshop on Synchronous Programming (Synchron 2006), 2006, Alpe d'Huez, France. 2006. <inria-00565163>
  • Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Ashish Meena. Model Driven Engineering for Regular MPSoC Co-design. ReCoSoC-05, 2005, Montpellier, France. 2005. <inria-00565173>
  • Jean-Luc Dekeyser, Pierre Boulet, Philippe Marquet, Samy Meftali. Model Driven Engineering for SoC Co-Design. NEWCAS'05, 2005, Québec, Canada. 2005. <inria-00565172>
  • Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet. Mode-Automata based Methodology for Scade. Hybrid Systems: Computation and Control (HSCC05), Mar 2005, Zurich, Switzerland, 2005. <inria-00000912>
  • Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, Éric Rutten. Introducing Control in the Gaspard2 Data-Parallel Metamodel: Synchronous Approach. International Workshop MARTES: Modeling and Analysis of Real-Time and Embedded Systems, Oct 2005, Montego Bay, Jamaica, 2005. <inria-00000911>
  • Pierre Boulet, Ashish Meena. The case for Globally Irregular Locally Regular Algorithm Architecture Adequation. Journées Francophones sur l'Adéquation Algorithme Architecture (JFAAA'05), 2005, Dijon, France. 2005. <inria-00565175>
  • Jean-Luc Dekeyser, Philippe Marquet, Samy Meftali, Cédric Dumoulin, Pierre Boulet, et al.. Why to do Without Model Driven Architecture in Embedded System Codesign?. The first annual IEEE BENELUX/DSP Valley Signal Processing Symposium, (SPS-DARTS 2005), 2005, Antwerp, Belgium. 2005. <inria-00565174>
  • Ashish Meena, Pierre Boulet. Model Driven Scheduling Framework for Multiprocessor SoC Design. Workshop on Scheduling for Parallel Computing (SPC 2005), 2005, Poznan, Poland. Springer-Verlag, 2005. <inria-00565169>
  • Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, Pierre Boulet. Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies - A partial answer to the MARTE RFP. MoDELS/UML 2005, ACM/IEEE 8th International Conference on Model Driven Engineering Languages and Systems, 2005, Montego Bay, Jamaica. Lecture Notes in Computer Science vol. 3713, pp.445-459, 2005. <inria-00565168>
  • Lossan Bondé, Pierre Boulet, Jean-Luc Dekeyser. Traceability and Interoperability at Different Levels of Abstraction in Model Transformations. Forum on Specification and Design Languages, FDL'05, 2005, Lausanne, Switzerland. 2005. <inria-00565170>
  • Abdelkader Amar, Pierre Boulet, Philippe Dumont. Projection of the Array-OL Specification Language onto the Kahn Process Network Computation Model. International Symposium on Parallel Architectures, Algorithms, and Networks, 2005, Las Vegas, Nevada, United States. 2005. <inria-00565167>
  • Arnaud Cuccuru, Pierre Boulet, Jean-Luc Dekeyser. Regular Hardware Architecture Modeling with UML2. FDL04, 2004, Lille, France. 2004. <inria-00565176>
  • Cédric Dumoulin, Pierre Boulet, Jean-Luc Dekeyser, Philippe Marquet. MDA for SoC Design, Intensive Signal Processing Experiment. FDL'03, 2003, Frankfurt, Germany. 2003. <inria-00565179>
  • Pierre Boulet, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Marquet. MDA for SoC Embedded Design, Intensive Signal Processing Experiment. SIVOES-MDA, 2003, San Francisco, United States. 2003. <inria-00565178>
  • Pierre Boulet, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Marquet, Philippe Kajfasz, et al.. Sophocles: Cyber-Enterprise for System-on-Chip Distributed Simulation -- Model Unification. IFIP International Workshop on IP Based System-on-Chip Design, 2003, Grenoble, France. 2003. <inria-00565177>
  • Pierre Boulet, Jean-Luc Dekeyser, Jean-Luc Levaire, Philippe Marquet, Julien Soula, et al.. Visual Data-parallel Programming for Signal Processing Applications. 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001, 2001, Mantova, Italy. pp.105--112, 2001. <inria-00565183>
  • Pierre Boulet, Jean-Luc Dekeyser, Florent Devin, Philippe Marquet. A Visual Development Environment for Meta-Computing Applications. HCI International 2001, 9th Int'l Conf. on Human-Computer Interaction, 2001, New Orleans, Lousiana, United States. Lawrence Erlbaum Associates, Publishers, 2001. <inria-00565182>
  • Abdelkader Amar, Pierre Boulet, Jean-Luc Dekeyser. Assembling Dynamic Components for Metacomputing using CORBA. Parallel Computing, 2001, Naples, Italy. Lecture Notes in Computer Science, 2001. <inria-00565181>
  • Emmanuel Cagniot, Jean-Luc Dekeyser, Pierre Boulet, Thomas Brandes, Francis Piriou, et al.. Parallélisation d'un code 3D Magnétostatique avec le Langage de Programmation High Performance Fortran. Conférence Européenne sur les Méthodes Numériques en Éléctomagnétisme, NUMELEC'2000 (poster session), 2000, Poitiers, France. pp.184-185, 2000. <inria-00565186>
  • Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, Francis Piriou, Pierre Boulet, et al.. Parallelization of 3D Magnetostatic Code Using High Performance Fortran. International Conference on Parallel Computing in Electrical Engineering, PARELEC'2000, 2000, Trois-Rivières, Quebec, Canada. pp.181--185, 2000. <inria-00565185>
  • Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, Francis Piriou, Pierre Boulet, et al.. High Level Parallelization of a 3D Electromagnetic Simulation Code With Irregular Communication Patterns. 4th International Meeting on Vector and Parallel Processing (VECPAR'2000), 2000, Porto, Portugal. Lecture Notes in Computer Science vol. 1470, pp.519--528, 2000. <inria-00565184>
  • Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, Francis Piriou, Pierre Boulet, et al.. Parallelization of a Fortran 90 Program for Electromagnetic Problems. 3rd Annual HPF User Group Meeting, HUG'99, 1999, Redondo Beach, CA, United States. 1999. <inria-00565189>
  • Pierre Boulet, Jean-Luc Dekeyser, Alain Demeure, Florent Devin, Philippe Marquet. Une approche à la SQL du traitement de données intensif dans Gaspard. RenPar'11, Rencontres Francophones du Parallélisme des Architectures et des Systèmes, 1999, Rennes, France. 1999. <inria-00565188>
  • Pierre Boulet, Paul Feautrier. Scanning polyhedra without DO-loops. PACT'98, 1998, Paris, France. IEEE Computer Society, pp.4-11, 1998. <inria-00564990>
  • Pierre Boulet, Xavier Redon. Communication Pre-evaluation in HPF. Euro-Par'98, 1998, Southampton, United Kingdom. Lecture Notes in Computer Science, 1470, pp.263-272, 1998. <inria-00565190>
  • Pierre Boulet, Michèle Dion. Code generation in Bouclettes. Proceedings of the Fifth Euromicro Workshop on Parallel and Distributed Processing, 1997, London, United Kingdom. IEEE Computer Society Press, pp.273--280, 1997. <inria-00565001>
  • Pierre Boulet, Thomas Brandes. Evaluation of Automatic Parallelization Strategies for HPF Compilers. HPCN 96, 1996, Bruxelles, Belgium. Springer Verlag Lecture Notes in Computer Science, pp.778-783, 1996. <inria-00564994>
  • Pierre Boulet. Bouclettes: A Fortran Loop Parallelizer. HPCN 96, 1996, Bruxelles, Belgium. Springer Verlag Lecture Notes in Computer Science, pp.784-791, 1996. <inria-00564993>
  • Vincent Bouchitte, Pierre Boulet, Alain Darte, Yves Robert. Heuristics for the evaluation of array expressions on state-of-the-art massively parallel machines. M. Moonen and F. Catthoor. Algorithms and Parallel VLSI Architectures III, 1995, Unknown, North Holland, pp.319-330, 1995. <hal-00857100>
  • Pierre Boulet, José A.B. Fortes. Experimental Evaluation of Affine Schedules for Matrix Multiplication on the MasPar Architecture. Proceedings MPCS'94, 1994, Ischia, Italy. pp.452--459, 1994. <inria-00565005>
  • Pierre Boulet, Alain Darte, Tanguy Risset, Yves Robert. (Pen)-ultimate tiling?. IEEE Computer Society Press. Proceedings of the IEEE Scalable High Performance Computing Conference, 1994, Knoxville, TN, United States. pp.568-576, 1994. <inria-00564995>
  • Vincent Bouchitte, Pierre Boulet, Alain Darte, Yves Robert. Evaluating array expressions on massively parallel machines with communication/computation overlap. B. Buchberger and J. Volkert. Parallel Processing: CONPAR94 - VAPP VI, 1994, Unknown, Springer Verlag, pp.713-724, 1994, LNCS 854. <hal-00857085>

Poster1 document

  • Mahyar Shahsavari, Philippe Devienne, Pierre Boulet. N2S3, a Simulator for the Architecture Exploration of Neuromorphic Accelerators. NeuComp 2015, Mar 2015, Grenoble, France. 2015. <hal-01240444>

Chapitre d'ouvrage7 documents

  • A. H. Benyamina, Pierre Boulet, K. Benhaoua. Static and Dynamic Mapping Heuristics for Multiprocessor Systems-on-Chip. Gamatié, Abdoulaye. Computing in Research and Development in Africa, Springer International Publishing, pp.229--247, 2014, 978-3-319-08238-7 978-3-319-08239-4. <hal-01198993>
  • Rosilde Corvino, Abdoulaye Gamatié, Pierre Boulet. Design Space Exploration for Efficient Data Intensive Computing on SoCs. Borko Furht and Armando Escalante. Handbook of Data Intensive Computing, Springer, 2011. <inria-00637012>
  • Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, Éric Rutten. UML2 Profile for Modeling Controlled Data Parallel Applications. Huss, Sorin Alexander. Advances in Design and Specification Languages for SoCs, Selected contributions from FDL'06, Springer, 2007, ChDL. <inria-00565161>
  • Abdelkader Amar, Pierre Boulet, Jean-Luc Dekeyser. Towards Distributed Process Networks with CORBA. Frédéric Desprez. Algorithms and Tools for Parallel Computing On Heterogeneous Clusters, Nova Science Publishers, Inc, 2006. <inria-00565166>
  • Pierre Boulet, Cédric Dumoulin, Antoine Honoré. Model Driven Engineering for System-on-Chip Design. Jean-Philippe Babau and Joël Champeau and Sébastien Gérard. From MDD concepts to experiments and illustrations, ISTE, Hermes science and Lavoisier, 2006, 1-905209-59-0. <inria-00565165>
  • Lossan Bondé, Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Cédric Dumoulin, et al.. Model Driven Architecture for Intensive Embedded Systems. Sébastien Gérard and Jean-Philippe Babeau and Joël Champeau. Model Driven Engineering for Distributed Embedded Real-Time Systems, ISTE, Hermes science and Lavoisier, 2005, 1-905209-32-0. <inria-00565171>
  • Vincent Bouchitté, Pierre Boulet, Alain Darte, Yves Robert. Evaluating Array Expressions on Massively Parallel Machines with Communication/Computation Overlap. B. Buchberger and J. Volkert. Parallel Processing: CONPAR 94-VAPP VI, 854, Springer Verlag, pp.713-724, 1994, LNCS. <inria-00564992>

Direction d'ouvrage, Proceedings1 document

  • Pierre Boulet. Advances in Design and Specification Languages for SoCs Selected Contributions from FDL'04. Pierre Boulet. Kluwer Academic Publishers, pp.303, 2005, 0-387-26149-4. <10.1007/b136935>. <inria-00585558>

Rapport17 documents

  • Amen Souissi, Cedric Dumoulin, Pierre Boulet. PMS+: Un outil pour les processus de production de logiciels. [Rapport de recherche] 2013, pp.9. <hal-00802213>
  • Amine El Kouhen, Cedric Dumoulin, Sébastien Gerard, Pierre Boulet. Evaluation of Modeling Tools Adaptation. 2012. <hal-00706701v2>
  • Amen Souissi, Pierre Boulet, Cedric Dumoulin, Michael Launay. Modélisation centrée sur les processus métier pour la génération complète de portails collaboratifs. [Rapport de recherche] 2011. <inria-00638298>
  • Calin Glitia, Pierre Boulet, Eric Lenormand, Michel Barreteau. Repetitive Model Refactoring for Design Space Exploration of Intensive Signal Processing Applications. [Research Report] 2009, pp.21. <inria-00465456>
  • Calin Glitia, Pierre Boulet. High Level Loop Transformations for Systematic Signal Processing Embedded Applications. [Research Report] RR-6469, INRIA. 2008, pp.27. <inria-00262023v2>
  • Pierre Boulet. Formal Semantics of Array-OL, a Domain Specific Language for Intensive Multidimensional Signal Processing. [Research Report] RR-6467, INRIA. 2008, pp.33. <inria-00261178v2>
  • Imran Rafiq Quadri, Pierre Boulet, Jean-Luc Dekeyser. Modeling of Topologies of Interconnection Networks based on Multidimensional Multiplicity. [Research Report] RR-6201, INRIA. 2007. <inria-00149527v4>
  • Rabie Ben Atitallah, Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Antoine Honoré, et al.. Gaspard2 UML profile documentation. [Technical Report] RT-0342, INRIA. 2007, pp.45. <inria-00171137v2>
  • Pierre Boulet. Array-OL Revisited, Multidimensional Intensive Signal Processing Specification. [Research Report] RR-6113, INRIA. 2007, pp.24. <inria-00128840v3>
  • Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, Éric Rutten. Introducing Control in the Gaspard2 Data-Parallel Metamodel: Synchronous Approach. [Research Report] RR-5794, INRIA. 2006, pp.49. <inria-00070228>
  • Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser. Synchronous Modeling of Data Intensive Applications. [Research Report] RR-5876, INRIA. 2006, pp.21. <inria-00001216>
  • Abdelkader Amar, Pierre Boulet, Pierre Dumont. Projection of the Array-OL Specification Language onto the Kahn Process Network Computation Model. [Research Report] RR-5515, INRIA. 2005, pp.18. <inria-00070491>
  • Philippe Dumont, Pierre Boulet. Another Multidimensional Synchronous Dataflow: Simulating Array-OL in Ptolemy II. [Research Report] RR-5516, INRIA. 2005, pp.19. <inria-00070490>
  • Abdelkader Amar, Pierre Boulet, Jean-Luc Dekeyser, Frans Theeuwen. Distributed Process Networks Using Half FIFO Queues in CORBA. [Research Report] RR-4765, INRIA. 2003. <inria-00071821>
  • Cedric Dumoulin, Pierre Boulet, Jean-Luc Dekeyser, Philippe Marquet. UML 2.0 Structure Diagram for Intensive Signal Processing Application Specification. [Research Report] RR-4766, INRIA. 2003. <inria-00071820>
  • Pierre Boulet, Alain Darte, Georges-André Silber, Frédéric Vivien. Loop parallelization algorithms: from parallelism extraction to code generation. [Research Report] 97--17, 1997. <hal-00856896>
  • Pierre Boulet, Michèle Dion, Eric Lequiniou, Tanguy Risset. Reference Manual of the Bouclettes Parallelizer. [Technical Report] 1994. <inria-00565002>

Thèse1 document

  • Pierre Boulet. Outils pour la parallélisation automatique. Génie logiciel [cs.SE]. Ecole normale supérieure de lyon - ENS LYON, 1996. Français. <tel-00564899>

HDR1 document

  • Pierre Boulet. Contributions aux environnements de programmation pour le calcul intensif. Génie logiciel [cs.SE]. Université des Sciences et Technologie de Lille - Lille I, 2002. <tel-00564904>