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Patrick Girard
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Documents
Identifiants chercheurs
patrick-girard-lirmm-
0000-0003-0722-8772
Présentation
Publications
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On the Test and Mitigation of Malfunctions in Low-Power SRAMsJournal of Electronic Testing: : Theory and Applications, 2014, 30 (5), pp.611-627. ⟨10.1007/s10836-014-5479-z⟩
Article dans une revue
lirmm-01238443v1
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Impact of Resistive-Bridging Defects in SRAM at Different Technology NodesJournal of Electronic Testing: : Theory and Applications, 2012, 28 (3), pp.317-329. ⟨10.1007/s10836-012-5291-6⟩
Article dans une revue
lirmm-00805017v1
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A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power ReductionJournal of Electronic Testing: : Theory and Applications, 2008, 24 (4), pp.353-364. ⟨10.1007/s10836-007-5053-z⟩
Article dans une revue
lirmm-00331296v1
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Test Solution for Data Retention Faults in Low-Power SRAMsDATE 2013 - 16th Design, Automation and Test in Europe Conference, Mar 2013, Grenoble, France. pp.442-447, ⟨10.7873/DATE.2013.099⟩
Communication dans un congrès
lirmm-00805140v1
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A Built-in Scheme for Testing and Repairing Voltage Regulators of Low-Power SRAMsVTS: VLSI Test Symposium, Apr 2013, Berkeley, CA, United States. pp.1-6, ⟨10.1109/VTS.2013.6548894⟩
Communication dans un congrès
lirmm-00805366v1
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Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failuresDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Mar 2013, Abu Dhabi, United Arab Emirates. pp.39-44, ⟨10.1109/DTIS.2013.6527775⟩
Communication dans un congrès
lirmm-01248603v1
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On the Reuse of Read and Write Assist Circuits to Improve Test Efficiency in Low-Power SRAMsITC: International Test conference, Sep 2013, Anaheim, CA, United States. pp.1-10, ⟨10.1109/TEST.2013.6651927⟩
Communication dans un congrès
lirmm-00818977v1
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Analyzing resistive-open defects in SRAM core-cell under the effect of process variabilityETS: European Test Symposium, May 2013, Avignon, France. ⟨10.1109/ETS.2013.6569373⟩
Communication dans un congrès
lirmm-01921630v1
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Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM TestingATS: Asian Test Symposium, Nov 2013, Jiaosi Township, Taiwan. pp.109-114, ⟨10.1109/ATS.2013.30⟩
Communication dans un congrès
lirmm-01248609v1
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Low-power SRAMs Power Mode Control Logic: Failure Analysis and Test SolutionsITC'2012: International Test Conference, Nov 2012, Anaheim, CA, United States. pp.1-10, ⟨10.1109/TEST.2012.6401578⟩
Communication dans un congrès
lirmm-00805143v1
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Defect Analysis in Power Mode Control Logic of Low-Power SRAMsETS: European Test Symposium, May 2012, Annecy, France. ⟨10.1109/ETS.2012.6233033⟩
Communication dans un congrès
lirmm-00805374v1
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Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line CouplingGDR SOC-SIP'11 : Colloque GDR SoC-SiP, Lyon, France
Communication dans un congrès
lirmm-00679522v1
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Variability Analysis of an SRAM Test ChipETS: European Test Symposium, May 2011, Trondheim, Norway
Communication dans un congrès
lirmm-00651791v1
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Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line CouplingDDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Netherlands. pp.353-358
Communication dans un congrès
lirmm-00592182v1
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On Using Address Scrambling to Implement Defect Tolerance in SRAMsITC'2011: International Test Conference, Sep 2011, Anaheim, CA, United States. pp.N/A
Communication dans un congrès
lirmm-00647773v1
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Detecting NBTI Induced Failures in SRAM Core-CellsVTS'10: VLSI Test Symposium, Santa Cruz, CA, United States. pp.75-80
Communication dans un congrès
lirmm-00553612v1
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Failure Analysis and Test Solutions for Low-Power SRAMsATS: Asian Test Symposium, Nov 2011, New Delhi, India. pp.459-460, ⟨10.1109/ATS.2011.97⟩
Communication dans un congrès
lirmm-00805123v1
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On Using Address Scrambling for Defect Tolerance in SRAMsInternational test Conference, Sep 2011, Anaheim, CA, United States. pp.1-8, ⟨10.1109/TEST.2011.6139149⟩
Communication dans un congrès
lirmm-00805334v1
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Impact of Resistive-Bridging Defects in SRAM Core-CellDELTA'10: International Symposium on Electronic Design, Test & Applications, Ho Chi Minh, Vietnam. pp.265-270
Communication dans un congrès
lirmm-00553592v1
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A Statistical Simulation Method for Reliability Analysis of SRAM Core-CellsDAC: Design Automation Conference, Jun 2010, Anaheim, United States. pp.853-856
Communication dans un congrès
lirmm-00553619v1
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Setting Test Conditions for Detecting Faults Induced by Random Dopant Fluctuation in SRAM Core-CellsVARI: Workshop on CMOS Variability, 2010, Montpellier, France
Communication dans un congrès
lirmm-00553626v1
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Setting Test Conditions for Improving SRAM ReliabilityETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.257-262
Communication dans un congrès
lirmm-00492741v1
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Analysis of Resistive-Bridging Defects in SRAM Core-Cells: a Comparative Study from 90nm down to 40nm Technology NodesETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.132-137
Communication dans un congrès
lirmm-00493236v1
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Minimizing Peak Power Consumption during Scan Testing: Structural Technique for Don't Care Bits AssignmentPRIME'06: Conference on Ph.D. Research in Microelectronics and Electronics, Jun 2006, Otranto, Italy, pp.65-68
Communication dans un congrès
lirmm-00137614v1
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Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling HeuristicsDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Sep 2006, Tunis, Tunisia. pp.359-364
Communication dans un congrès
lirmm-00093690v1
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Power-Aware Test Data Compression for Embedded IP CoreATS 2006 - 15th IEEE Asian Test Symposium, Nov 2006, Fukuoka, Japan. pp.5-10, ⟨10.1109/ATS.2006.66⟩
Communication dans un congrès
lirmm-00116832v1
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Technique Structurelle d'Affectation des Bits Non Spécifiés en Vue d'une Réduction de la Puissance de Pic Pendant le Test SérieJNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France
Communication dans un congrès
lirmm-00136838v1
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Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan TestingVLSI-SOC'06: 14th IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip, Oct 2006, Nice (France), pp.403-408
Communication dans un congrès
lirmm-00108141v1
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Power-Aware Scan Testing for Peak Power ReductionVLSI-SOC'05: IFIP International Conference on Very Large Scale Integration, Oct 2005, Perth, Australia. pp.441-446
Communication dans un congrès
lirmm-00106112v1
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Analyse et Réduction de la Puissance de Pic durant le Test SérieJNRDM 2005 - 8e Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France
Communication dans un congrès
lirmm-00106528v1
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Peak Power Consumption During Scan Testing: Issue, Analysis and Heuristic SolutionDDECS'05: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2005, Sopron, Hungary. pp.151-159
Communication dans un congrès
lirmm-00105990v1
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Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set PerspectivesPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.540-549, ⟨10.1007/11556930_55⟩
Communication dans un congrès
lirmm-00106111v1
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SRAM Core-cell Quality MetricsGDR SOC SIP, France. 2009
Poster de conférence
lirmm-00434962v1
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Analysis of Resistive-Bridging Defects in SRAM Core-Cell: Impact within the Core-Cell and in the Memory ArrayETS: European Test Symposium, May 2009, Sevilla, Spain. 14th IEEE European Test Symposium, 2009
Poster de conférence
lirmm-00433796v1
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Structural Power-Aware Assignment of Xs for Peak Power Reduction during Scan TestingETS: European Test Symposium, May 2006, Southampton, United Kingdom. 11th IEEE European Test Symposium, 2006
Poster de conférence
lirmm-00134781v1
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Scan Cell Reordering for Peak Power Reduction during Scan Test CyclesVLSI-Soc: From Systems to Silicon, pp.267-281, 2007, 978-0-387-73661-7
Chapitre d'ouvrage
lirmm-00194261v1
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Assist Circuits for SRAM TestingFrance, Patent n° : US9418759. 2014
Brevet
lirmm-02089903v1
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Circuit arrangement, a method for testing a supply voltage provided to a test circuit, and a method for repairing a voltage sourceFrance, Patent n° : US20140307515. 2013
Brevet
lirmm-02089895v1
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