Filtrer vos résultats
- 27
- 17
- 29
- 11
- 2
- 1
- 1
- 29
- 17
- 2
- 4
- 2
- 3
- 3
- 2
- 8
- 3
- 2
- 2
- 1
- 1
- 2
- 1
- 3
- 5
- 36
- 8
- 32
- 5
- 2
- 1
- 1
- 44
- 25
- 12
- 11
- 11
- 9
- 8
- 7
- 5
- 3
- 2
- 2
- 2
- 2
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
44 résultats
|
|
|
triés par
|
Flexible Multi-ASIP SoC for High-Throughput Turbo DecodersPremier Colloque National du GDR SOC-SIP, Jun 2007, Paris, France
Communication dans un congrès
hal-02280092v1
|
|||
|
|
(System)Verilog to Chisel Translation for Faster Hardware Design2020 31th International Symposium on Rapid System Prototyping (RSP), Sep 2020, VIrtual Conference, France
Communication dans un congrès
hal-02949112v1
|
||
|
|
HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic2016 Euromicro Conference on Digital System Design (DSD), 2016, Limassol, Cyprus. pp.511-518, ⟨10.1109/DSD.2016.51⟩
Communication dans un congrès
hal-01389247v1
|
||
Validation automatique d’une méthode de migration des tâches sur la plateforme ZynqJournées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRD'16), May 2016, Toulouse, France
Communication dans un congrès
hal-01445859v1
|
|||
|
|
ASIP-based multiprocessor SoC design for simple and double binary turbo decodingDATE 06 : Design, Automation and Test in Europe, Mar 2006, Munich, Germany. pp.1 - 6, ⟨10.1109/DATE.2006.244126⟩
Communication dans un congrès
hal-02194947v1
|
||
Fast and Autonomous HLS Methodology for Hardware Accelerator Generation Under Resource ConstraintsEuromicro Conference on Digital System Design (DSD'13), Sep 2013, Santander, Spain. pp.201 - 208, ⟨10.1109/DSD.2013.30⟩
Communication dans un congrès
hal-00919969v1
|
|||
On the parallelism of convolutional turbo decoding and interleaving interferenceGLOBECOM 2006 : 49th annual Global telecommunications conference, Nov 2006, San Francisco, United States. pp.1 - 5, ⟨10.1109/GLOCOM.2006.558⟩
Communication dans un congrès
hal-02194954v1
|
|||
Teaching basic computer architecture, assembly language programming, and operating system design using RISC-VRISC V week 2019, Oct 2019, Paris, France
Communication dans un congrès
hal-02614532v1
|
|||
|
|
Parallelism Efficiency in Convolutional Turbo DecodingEURASIP Journal on Advances in Signal Processing, 2010, vol. 2010, Article ID 927920, 11 p. ⟨10.1155/2010/927920⟩
Article dans une revue
hal-00569878v1
|
||
Message-Oriented Devices on FPGAsInternational Symposium on Rapid System Prototyping (RSP 2018), Oct 2018, Torino, Italy. pp.8-14
Communication dans un congrès
hal-02114435v1
|
|||
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decodingDATEC 2007 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2007, Nice, France. pp.654 - 659
Communication dans un congrès
hal-02194929v1
|
|||
A Chisel Framework for Flexible Design Space Exploration through a Functional ApproachACM Transactions on Design Automation of Electronic Systems, 2023, 28 (4), pp.1-31. ⟨10.1145/3590769⟩
Article dans une revue
hal-04298227v1
|
|||
|
|
Chisel Usecase: Designing General Matrix Multiply for FPGAFernando Rincón, Jesús Barba, Hayden K. H. So, Pedro Diniz, Julián Caba. Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC 2020), Apr 2020, Toledo, Spain. Springer, Applied Reconfigurable Computing. Architectures, Tools, and Applications 16th International Symposium, ARC 2020, Toledo, Spain, April 1–3, 2020, Proceedings, pp.61-72, Lecture Notes in Computer Science. ⟨10.1007/978-3-030-44534-8_5⟩
Poster de conférence
hal-03082750v1
|
||
Fast and Standalone Design Space Exploration for High-Level Synthesis under Resource ConstraintsJournal of Systems Architecture, 2014, 60 (1), pp.79-93. ⟨10.1016/j.sysarc.2013.10.002⟩
Article dans une revue
hal-00914536v1
|
|||
Maintaining Communication Consistency during Task Migrations in Heterogeneous Reconfigurable DevicesMulti-Processor System-on-Chip 1: Architectures, wiley, chichester, uk, pp.255-285, 2021, 978-1-789-45021-7
Chapitre d'ouvrage
hal-03194391v1
|
|||
Prototyping dynamic task migration on heterogeneous reconfigurable systemsInternational Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, Oct 2017, Seoul, South Korea
Communication dans un congrès
hal-01971312v1
|
|||
|
|
Generating Efficient Context-Switch Capable Circuits Through Autonomous Design FlowACM Transactions on Reconfigurable Technology and Systems (TRETS), 2016, 10 (1), pp.9. ⟨10.1145/2996199⟩
Article dans une revue
hal-01367798v2
|
||
|
|
Towards Agile Hardware Designs with Chisel: a Network Use-caseIEEE Design & Test, 2021, ⟨10.1109/MDAT.2021.3063339⟩
Article dans une revue
hal-03157426v1
|
||
FPGA prototypes for turbo communication applicationsUniversity Booth of DATE 09 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2009, Nice, France
Communication dans un congrès
hal-01841144v1
|
|||
|
|
From application to ASIP-based FPGA prototype : a case study on turbo decodingRSP'2008 : the 19th IEEE/IFIP international symposium on rapid system prototyping, Jun 2008, Monterey, United States. pp.128 - 134, ⟨10.1109/RSP.2008.16⟩
Communication dans un congrès
hal-02194910v1
|
||
Méthodologie de génération rapide et automatique d’accélérateurs matériels sous contraintes de ressources : progression itérative et gloutonneConférence en Parallélisme, Architecture et Système (ComPAS'13), Jan 2013, Grenoble, France
Communication dans un congrès
hal-01408850v1
|
|||
Automated Non-Regression Testing for Accelerator Prototyping on FPGAInternational symposium on Rapid System Prototyping (RSP'16), Oct 2016, Pittsbrugh, United States. pp.45-51
Communication dans un congrès
hal-01523887v1
|
|||
|
|
Parallélisme et turbocodes convolutifsMajecSTIC 2006 : MAnifestation des JEunes Cherchercheurs STIC, Nov 2006, Lorient, France
Communication dans un congrès
hal-02280103v1
|
||
From parallelism levels to a multi-ASIP architecture for turbo decodingIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17 (1), pp.92 - 102. ⟨10.1109/TVLSI.2008.2003164⟩
Article dans une revue
hal-01853650v1
|
|||
Bandwidth reduction of extrinsic information exchange in turbo decodingElectronics Letters, 2006, 42 (19), pp.1104 - 1106. ⟨10.1049/el:20062209⟩
Article dans une revue
hal-01853652v1
|
|||
Cohérence des communications lors de la migration de tâches matériellesISTE. Systèmes multiprocesseurs sur puce 1 - Architectures, ISTE - International Scientific and Technical Encyclopedia, pp.309-343, 2023, ⟨10.51926/ISTE.9021.ch11⟩
Chapitre d'ouvrage
hal-04131346v1
|
|||
A Novel Method for Enabling FPGA Context-Switch (Abstract Only)Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015, Monterey, CA, USA, United States. pp.261--261, ⟨10.1145/2684746.2689096⟩
Communication dans un congrès
hal-01353496v1
|
|||
|
|
Efficient Decompression of Binary Encoded Balanced Ternary SequencesIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019
Article dans une revue
hal-02103214v1
|
||
HCM: An Abstraction Layer for Seamless Programming of DPR FPGA2nd Internation Conference on Field Programmable Logic and Applications (FPL'12), Aug 2012, Oslo, Norway. pp.583 - 586, ⟨10.1109/FPL.2012.6339212⟩
Communication dans un congrès
hal-00745837v1
|
|||
La synthèse de haut niveau au service du changement de contexte matériel.Colloque National GDR SoC-SiP, 2016, Nantes, France
Communication dans un congrès
hal-01353497v1
|
- 1
- 2