Skip to Main content

Keywords

Researcher identifiers

  • IdHAL : nadine-azemard

Social networks

    Export Publications

    Export the displayed publications:

    External widget

    Number of documents

    92

    liste-publi-NAC


    Philippe Maurine   

    Journal articles10 documents

    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gilles R. Ducharme. Delay-correlation-aware SSTA based on conditional moments. Microelectronics Journal, Elsevier, 2012, 43 (4), pp.263-273. ⟨10.1016/j.mejo.2012.01.003⟩. ⟨lirmm-00761821⟩
    • Philippe Maurine, Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, et al.. Timing Slack Monitoring under Process and Environmental Variations: Application to a DSP Performance Optimization. Microelectronics Journal, Elsevier, 2011, 42 (5), pp.718-732. ⟨lirmm-00607877⟩
    • Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Sylvain Engels, et al.. On-Chip Process Variability Monitoring Flow. Journal of Low Power Electronics, American Scientific Publishers, 2010, 6 (4), pp.601-606. ⟨10.1166/jolpe.2010.1109⟩. ⟨lirmm-00546368⟩
    • Sylvain Engels, Robin Wilson, Nadine Azemard, Philippe Maurine, Vincent Migairou. Timing Margin Evaluation with a Simple Statistical Timing Analysis Flow. Journal of Embedded Computing, IOS Press, 2009, 3 (3), pp.221-229. ⟨lirmm-00371162⟩
    • Benoit Lasbouygues, Robin Wilson, Nadine Azemard, Philippe Maurine. Temperature and Voltage Aware Timing Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2007, 26 (4), pp.801-815. ⟨10.1109/TCAD.2006.884860⟩. ⟨lirmm-00178921⟩
    • Benoit Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azemard, et al.. Logical Effort Model Extension to Propagation Delay Representation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2006, 25 (9), pp.1677-1684. ⟨10.1109/TCAD.2005.857400⟩. ⟨lirmm-00104315⟩
    • Sylvain Engels, Robin Wilson, Nadine Azemard, Philippe Maurine. A Comprehensive Performance Macro-Modeling of on-Chip RC Interconnects Considering Line Shielding Effects. Integration, the VLSI Journal, Elsevier, 2006, 39 (4), pp.433-456. ⟨10.1016/j.vlsi.2005.08.007⟩. ⟨lirmm-00106854⟩
    • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Delay Bounds Based Constraint Distribution Method. IEE Proceedings - Computers and Digital Techniques (1994-2006), Institution of Engineering and Technology, 2005, 152 (6), pp.765-770. ⟨10.1049/ip-cdt:20050026⟩. ⟨lirmm-00105370⟩
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. General Representation of CMOS Structure Transition time for Timing Library Representation. Electronics Letters, IET, 2002, 38 (4), pp.175-177. ⟨lirmm-00239318⟩
    • Philippe Maurine, Mustapha Rezzoug, Nadine Azemard, Daniel Auvergne. Transition Time Modeling in Deep Submicron CMOS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2002, 21 (11), pp.1352-1363. ⟨lirmm-00239324⟩

    Conference papers75 documents

    • Nadine Azemard, Zeqin Wu, Philippe Maurine, Gilles R. Ducharme. Statistical Cells Timing Metrics Characterization. FTFC: Faible Tension - Faible Consommation, Jun 2012, Paris, France. ⟨lirmm-00762131⟩
    • Nadine Azemard, Zeqin Wu, Philippe Maurine, Gilles R. Ducharme. Characterizing Statistical Cells Timing Metrics with Semi-Monte-Carlo Method. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2011, Hong-Kong, China. ⟨lirmm-00617606⟩
    • Nadine Azemard, Zeqin Wu, Philippe Maurine, Gilles R. Ducharme. Statistical Timing Characterization of Standard Cells with Semi-Monte-Carlo Method. VARI: Workshop on CMOS Variaility, May 2011, Grenoble, France. ⟨lirmm-00617593⟩
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gilles R. Ducharme. SSTA with Delay Correlations. NEWCAS: New Circuits and Systems, Jun 2010, Montreal, QC, Canada. pp.261-266, ⟨10.1109/NEWCAS.2010.5603930⟩. ⟨lirmm-00504882⟩
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gilles R. Ducharme. Computing Delay Correlations in SSTA. ICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.130-133, ⟨10.1109/ICICDT.2010.5510277⟩. ⟨lirmm-00546301⟩
    • Nabila Moubdi, Philippe Maurine, Nadine Azemard, Robin Wilson, Sylvain Engels. Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPC. ICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.82-85, ⟨10.1109/ICICDT.2010.5510289⟩. ⟨lirmm-00546316⟩
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gilles R. Ducharme. SSTA with Cell-to-Cell Delay Correlations. VARI: Workshop on CMOS Variability, May 2010, Montpellier, France. ⟨lirmm-00546322⟩
    • Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Vincent Dumettier, et al.. On-Chip Process Variability Monitoring. VARI: Workshop on CMOS Variability, May 2010, Montpellier, France. ⟨lirmm-00546337⟩
    • Zeqin Wu, Nadine Azemard, Philippe Maurine, Gilles R. Ducharme. Interpretation of SSTA Results. FTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Switzerland. ⟨lirmm-00374060⟩
    • Nabila Moubdi, Robin Wilson, Sylvain Engels, Nadine Azemard, Philippe Maurine. On-Chip Process Variability Monitoring. DATE: Design, Automation and Test in Europe, Apr 2009, Nice, France. ⟨lirmm-00374368⟩
    • Bettina Rebaud, Marc Belleville, Edith Beigné, Michel Robert, Philippe Maurine, et al.. Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variations. FTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Suisse. ⟨lirmm-00404810⟩
    • Bettina Rebaud, Marc Belleville, Edith Beigné, Michel Robert, Philippe Maurine, et al.. An Innovative Timing Slack Monitor for Variation Tolerant Circuits. ICICDT: International Conference on IC Design & Technology, May 2009, Austin, TX, United States. pp.215-218, ⟨10.1109/ICICDT.2009.5166299⟩. ⟨lirmm-00371174⟩
    • Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, et al.. Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.266-275, ⟨10.1007/978-3-642-11802-9_31⟩. ⟨lirmm-00433462⟩
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gilles R. Ducharme. Interpreting SSTA Results with Correlation. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.16-25, ⟨10.1007/978-3-642-11802-9_6⟩. ⟨lirmm-00433505⟩
    • Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Vincent Dumettier, et al.. Product On-Chip Process Compensation for Low Power and Yield Enhancement. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.247-255, ⟨10.1007/978-3-642-11802-9_29⟩. ⟨lirmm-00433504⟩
    • Bettina Rebaud, Marc Belleville, Edith Beigné, Michel Robert, Philippe Maurine, et al.. On-Chip Timing Slack Monitoring. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2009, Florianopolis, Brazil. pp.89-94, ⟨10.1109/VLSISOC.2009.6041336⟩. ⟨lirmm-00429350⟩
    • Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, et al.. Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩. ⟨lirmm-00280809⟩
    • Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, et al.. Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numérique. FTFC: Faible Tension - Faible Consommation, May 2008, Louvain-La-Neuve, Belgique. ⟨lirmm-00283731⟩
    • Zeqin Wu, Philippe Maurine, Gilles R. Ducharme, Nadine Azemard. SSTA Considering Effects of Structure Correlations, Input Slope and Output Load Variations. FTFC: Faible Tension - Faible Consommation, May 2008, Louvain-la-Neuve, Belgium. pp.39-43. ⟨lirmm-00288537⟩
    • Bettina Rebaud, Zeqin Wu, Marc Belleville, Christian Bernard, Michel Robert, et al.. Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétique. JNRDM: Journées Nationales du Réseau Doctoral en Microélectronique, May 2008, Bordeaux, France. ⟨lirmm-00281175v2⟩
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gilles R. Ducharme. SSTA Considering Switching Process Induced Correlations. APCCAS: Asia Pacific Conference on Circuits and System, Nov 2008, Macao, China. pp.562-565, ⟨10.1109/APCCAS.2008.4746085⟩. ⟨lirmm-00340564⟩
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gilles R. Ducharme. SSTA with Correlations Considering input Slope and Output Load Variations. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2008, Rhodes Island, Greece. pp.164-167. ⟨lirmm-00332757⟩
    • Zeqin Wu, Philippe Maurine, Gilles R. Ducharme, Nadine Azemard. Conditional Moments based SSTA Considering Switching Process Induced Correlations. DCIS: Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. pp.70-77. ⟨lirmm-00340221⟩
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gilles R. Ducharme. SSTA with Structure Correlations Considering input Slope and Output Load Variations. GDR SOC-SIP, Jun 2008, Paris, France. pp.3. ⟨lirmm-00340231⟩
    • Vincent Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azemard, et al.. A Simple Statistical Timing Analysis Flow and its Application to Timing Margin Evaluation. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.138-147, ⟨10.1007/978-3-540-74442-9_14⟩. ⟨lirmm-00175076⟩
    • Vincent Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azemard, et al.. A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. FTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.19-25. ⟨lirmm-00178454⟩
    • Robin Perrot, Nadine Azemard, Philippe Maurine. Une Famille d'Additionneurs Asynchrones CMOS Bundled Data à Temps de Calcul Dépendant aux Données. FTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.75-80. ⟨lirmm-00178466⟩
    • Benoit Lasbouygues, Robin Wilson, Nadine Azemard, Philippe Maurine. Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops. DATE: Design, Automation and Test in Europe, Mar 2007, Nice, France. ⟨10.1109/DATE.2007.364426⟩. ⟨lirmm-00178525⟩
    • Robin Perrot, Nadine Azemard, Philippe Maurine. Request-Skip Adders: CMOS Standard Cell Data Dependent Adders. ICECS: International Conference on Electronics, Circuits and Systems, Dec 2006, Nice, France. pp.510-513, ⟨10.1109/ICECS.2006.379837⟩. ⟨lirmm-00130195⟩
    • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Circuit Sizing Method under Delay Constraint. ISCAS: International Symposium on Circuits and Systems, May 2006, Island of Kos, Greece. pp.5123-5126, ⟨10.1109/ISCAS.2006.1693785⟩. ⟨lirmm-00106911⟩
    • Benoit Lasbouygues, Robin Wilson, Nadine Azemard, Philippe Maurine. Timing Analysis in Presence of Supply Voltage and Temperature Variations. ISPD: International Symposium on Physical Design, Apr 2006, San Jose, CA, United States. pp.10-16, ⟨10.1145/1123008.1123012⟩. ⟨lirmm-00102760⟩
    • Vincent Migairou, Robin Wilson, Sylvain Engels, Nadine Azemard, Philippe Maurine. Statistical Characterization of Library Timing Performance. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2006, Montpellier, France. pp.468-476, ⟨10.1007/11847083_45⟩. ⟨lirmm-00093233⟩
    • Robin Perrot, Philippe Maurine, Nadine Azemard. Exploration of the Area-Latency Tradeoff of Asynchronous CMOS data Dependent Adders. DCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain. ⟨lirmm-00117102⟩
    • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Circuit Performance Optimization under Delay Constraints. DCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain. ⟨lirmm-00117119⟩
    • Robin Perrot, Nadine Azemard, Philippe Maurine. Une Famille d'Additionneur Asynchrones CMOS à Temps de Calcul Dépendant de Données. JNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. pp.469-472. ⟨lirmm-00102842⟩
    • Benoit Lasbouygues, Robin Wilson, Nadine Azemard, Philippe Maurine. Timing Analysis in Presence of Voltage Drops and Temperature Gradients. TAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. pp.28-34. ⟨lirmm-00106705⟩
    • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard. Protocole d'Optimisation de Circuit CMOS Orienté Basse Puissance. FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.17-22. ⟨lirmm-00106002⟩
    • Robin Perrot, Nadine Azemard, Philippe Maurine. Additionneurs RCA Data Dependent Micropipelines. FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.183-188. ⟨lirmm-00106005⟩
    • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Optimization Protocol Based on Low Power Metrics. IWLS: International Workshop on Logic Synthesis, Jun 2005, Lake Arrowhead Resort, CA, United States. pp.288-293. ⟨lirmm-00106018⟩
    • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Path Optimization Protocol Based on Speed Low Power Metrics. EUROCON: International Conference on "Computer as a Tool", Nov 2005, Belgrade, Serbia. pp.523-526, ⟨10.1109/EURCON.2005.1629980⟩. ⟨lirmm-00106428⟩
    • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Circuit Optimization Based on Speed Indicators. ICECS: International Conference on Electronics, Circuits and Systems, Dec 2005, Gammarth, Tunisia. pp.167-170, ⟨10.1109/icecs.2005.4633585⟩. ⟨lirmm-00106439⟩
    • Alexandre Verle, Xavier Michel, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Low Power Oriented CMOS Circuit Optimization Protocol. DATE: Design, Automation and Test in Europe, Mar 2005, Munich, Germany. pp.640-645. ⟨lirmm-00106452⟩
    • Robin Perrot, Nadine Azemard, Philippe Maurine. Ripple Carry Adder for Micropipeline Circuits. DCIS: Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal. pp.4d.3.1-4d.3.6. ⟨lirmm-00106075⟩
    • Alexis Landrault, Alexandre Verle, Philippe Maurine, Nadine Azemard. Synthèse Physique et Optimisation des Performances au Niveau Transistor. FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.91-95. ⟨lirmm-00106004⟩
    • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Speed Indicators for Circuit Optimization. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.618-628, ⟨10.1007/11556930_63⟩. ⟨lirmm-00106076⟩
    • Benoit Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Temperature Dependency in UDSM Process. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.693-703, ⟨10.1007/11556930_71⟩. ⟨lirmm-00106077⟩
    • Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Optimization Protocol Based on Performance Metric. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.964-968. ⟨lirmm-00108935⟩
    • Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Definition of P/N Width Ratio for CMOS Standard Cell Library. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.769-773. ⟨lirmm-00108933⟩
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. RC on-chip interconnect Performance revisited. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.809-814. ⟨lirmm-00108934⟩
    • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Delay Bound Based CMOS Gate Sizing Technique. ISCAS: International Symposium on Circuits and Systems, May 2004, Vancouver, BC, Canada. pp.189-192, ⟨10.1109/ISCAS.2004.1329494⟩. ⟨lirmm-00108856⟩
    • Alexis Landrault, Nadine Azemard, Philippe Maurine, Michel Robert, Daniel Auvergne. Design Optimization with Automated Cell Generation. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.722-731, ⟨10.1007/978-3-540-30205-6_74⟩. ⟨lirmm-00108894⟩
    • Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Performance Metric Based Optimization Protocol. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.100-109, ⟨10.1007/978-3-540-30205-6_12⟩. ⟨lirmm-00108892⟩
    • Benoit Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Physical Extension of the Logical Effort Model. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.838-848, ⟨10.1007/978-3-540-30205-6_86⟩. ⟨lirmm-00108895⟩
    • Benoit Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Temperature Dependence in Low Power CMOS UDSM Process. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.111-118, ⟨10.1007/978-3-540-30205-6_13⟩. ⟨lirmm-00108893⟩
    • Alexis Landrault, Nadine Azemard, Philippe Maurine, Michel Robert, Daniel Auvergne. Automatic Layout Synthesis Based Performance Optimization. IWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85. ⟨lirmm-00108654⟩
    • Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Metric Definition for Circuit Speed Optimization. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. pp.451-460. ⟨lirmm-00269568⟩
    • Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Metric Definition for Circuit Speed Optimization. IWLS: International Workshop on Logic Synthesis, May 2003, Laguna Beach, CA, United States. ⟨lirmm-00269689⟩
    • Benoit Lasbouygues, J. Schindler, Sylvain Engels, Philippe Maurine, Xavier Michel, et al.. Timing Performance Representation of a CMOS Standard Cell Library. DCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. pp.83-88. ⟨lirmm-00239460⟩
    • Benoit Lasbouygues, J. Schindler, Sylvain Engels, Philippe Maurine, Xavier Michel, et al.. Continuous Representation of the Performance of a CMOS Library. ESSCIRC: European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal. pp.595-598, ⟨10.1109/ESSCIRC.2003.1257205⟩. ⟨lirmm-00239459⟩
    • Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Définition d'une Métrique d'Insertion de Buffers. FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.131-136. ⟨lirmm-00269520⟩
    • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Dimensionnement de Portes CMOS Sous Contrainte de Délai. FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.111-117. ⟨lirmm-00269522⟩
    • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. CMOS Gate Sizing under Delay Constraint. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Torino, Italy. pp.60-69, ⟨10.1007/978-3-540-39762-5_8⟩. ⟨lirmm-00244021⟩
    • Benoit Lasbouygues, J. Schindler, Sylvain Engels, Philippe Maurine, Nadine Azemard, et al.. Représentation Unifiée des Performances Temporelles d'une Bibliothèque de Cellules Standards. FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.119-124. ⟨lirmm-00269519⟩
    • Philippe Maurine, Xavier Michel, Nadine Azemard, Daniel Auvergne. Gate Speed Improvement at Minimal Power Dissipation. APPCAS: Asia-Pacific Conference on Circuits and Systems, Oct 2002, Denpasar, Bali, pp.278-282. ⟨lirmm-00239453⟩
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Defining the Maximum Speed of CMOS Gate Library. DCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.81-86. ⟨lirmm-00239455⟩
    • Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Metric Definition for Buffer Insertion. DCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.307-312. ⟨lirmm-00239458⟩
    • Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Evaluation et Optimisation de Chemins Combinatoires. Colloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.173-176. ⟨lirmm-00269329⟩
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2002, Seville, Spain. pp.247-257, ⟨10.1007/3-540-45716-X_25⟩. ⟨lirmm-00244012⟩
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Full Analyttical Model for delay Performance Estimation in Submicron CMOS. MIXDES: Mixed Design of Integrated Circuits and Systems, Jun 2001, Zakopane, Poland. pp.355-359. ⟨lirmm-00239444⟩
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Performance Indicators for Designing CMOS Logic. ICM: International Conference on Microelectronics, Oct 2001, Rabat, Morocco. pp.99-102, ⟨10.1109/ICM.2001.997497⟩. ⟨lirmm-00239446⟩
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Technological Assignment for a Minimal Power Consumption. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.236-241. ⟨lirmm-00239450⟩
    • Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Timing Closure Management based on Delay Bound Determination. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.430-434. ⟨lirmm-00239452⟩
    • Philippe Maurine, Régis Poirier, Nadine Azemard, Daniel Auvergne. Switching Current Modeling in CMOS Inverter for Speed and Power Estimation. DCIS: Design of Circuits and Integrated Systems, Nov 2001, Porto, Portugal. pp.618-622. ⟨lirmm-00239448⟩
    • Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Delay Bound Determination for Timing Closure on CMOS Circuits. IWLS: International Workshop on Logic and Synthesis, Jun 2001, Granlibakken Conference Center, United States. pp.96-100. ⟨lirmm-00244007⟩
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2001, Yverdon-Les-Bains, Switzerland. pp.5.3.1-5.3.10. ⟨lirmm-00244010⟩

    Poster communications1 document

    Book sections4 documents

    • Pascal Benoit, Gilles Sassatelli, Philippe Maurine, Lionel Torres, Nadine Azemard, et al.. Towards Autonomous Scalable Integrated Systems. Design Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. ⟨10.1007/978-94-007-1125-9_4⟩. ⟨lirmm-01399454⟩
    • Daniel Auvergne, Philippe Maurine, Nadine Azemard. Modeling for Designing in Deep Sub-Micron Technologies. PIGUET C. Low-Power Electronics Design, CPR Press, 2004, 0-8493-1941-2. ⟨lirmm-00109162⟩
    • Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Feasible delay Bound Definition. SOC Design Methodologies, Kluwer Academic Publishers, pp.325-335, 2002, IFIP TC10 / WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC’01) December 3–5, 2001, Montpellier, France, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_40⟩. ⟨lirmm-00239363⟩
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Gate Sizing for Low Power Design. SOC Design Methodologies, Kluwer Academic Publishers, pp.301-312, 2002, IFIP TC10 / WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC’01) December 3–5, 2001, Montpellier, France, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_26⟩. ⟨lirmm-00239359⟩

    Directions of work or proceedings2 documents

    • Nadine Azemard, Philippe Maurine, Johan Vounckx. Integration, the VLSI Journal. 41 (1), Elsevier, 160 p., 2008, Power and Timing Modeling, Optimization and Simulation (Special Issue), ⟨10.1016/j.vlsi.2007.06.004⟩. ⟨lirmm-00189961⟩
    • Johan Vounckx, Nadine Azemard, Philippe Maurine. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings. LNCS (4148), Springer, 677 p., 2006, 978-3-540-39097-8. ⟨10.1007/11847083⟩. ⟨lirmm-00135046⟩