Nadine Azemard

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nadine-azemard
IdRef : 068448813

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philippe-maurine

	Delay-correlation-aware SSTA based on conditional moments Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme Microelectronics Journal, 2012, 43 (4), pp.263-273. ⟨10.1016/j.mejo.2012.01.003⟩ Article dans une revue lirmm-00761821v1
	Timing Slack Monitoring under Process and Environmental Variations: Application to a DSP Performance Optimization Philippe Maurine , Bettina Rebaud , Marc Belleville , Edith Beigné , Christian Bernard Microelectronics Journal, 2011, 42 (5), pp.718-732. ⟨10.1016/j.mejo.2011.02.005⟩ Article dans une revue lirmm-00607877v1
	On-Chip Process Variability Monitoring Flow Nabila Moubdi , Philippe Maurine , Robin M. Wilson , Nadine Azemard , Sylvain Engels Journal of Low Power Electronics, 2010, 6 (4), pp.601-606. ⟨10.1166/jolpe.2010.1109⟩ Article dans une revue lirmm-00546368v1
	Timing Margin Evaluation with a Simple Statistical Timing Analysis Flow Sylvain Engels , Robin M. Wilson , Nadine Azemard , Philippe Maurine , Vincent Migairou Journal of Embedded Computing, 2009, 3 (3), pp.221-229. ⟨10.3233/JEC-2009-0094⟩ Article dans une revue lirmm-00371162v1
	Temperature and Voltage Aware Timing Analysis Benoit Lasbouygues , Robin P. Wilson , Nadine Azemard , Philippe Maurine IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26 (4), pp.801-815. ⟨10.1109/TCAD.2006.884860⟩ Article dans une revue lirmm-00178921v1
	A Comprehensive Performance Macro-Modeling of on-Chip RC Interconnects Considering Line Shielding Effects Sylvain Engels , Robin Wilson , Nadine Azemard , Philippe Maurine Integration, the VLSI Journal, 2006, 39 (4), pp.433-456. ⟨10.1016/j.vlsi.2005.08.007⟩ Article dans une revue lirmm-00106854v1
	Logical Effort Model Extension to Propagation Delay Representation Benoit Lasbouygues , Sylvain Engels , Robin P. Wilson , Philippe Maurine , Nadine Azemard IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25 (9), pp.1677-1684. ⟨10.1109/TCAD.2005.857400⟩ Article dans une revue lirmm-00104315v1
	Delay Bounds Based Constraint Distribution Method Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne IEE Proceedings - Computers and Digital Techniques (1994-2006), 2005, 152 (6), pp.765-770. ⟨10.1049/ip-cdt:20050026⟩ Article dans une revue lirmm-00105370v1
	General Representation of CMOS Structure Transition time for Timing Library Representation Philippe Maurine , Nadine Azemard , Daniel Auvergne Electronics Letters, 2002, 38 (4), pp.175-177. ⟨10.1049/el:20020103⟩ Article dans une revue lirmm-00239318v1
	Transition Time Modeling in Deep Submicron CMOS Philippe Maurine , Mustapha Rezzoug , Nadine Azemard , Daniel Auvergne IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, 21 (11), pp.1352-1363. ⟨10.1109/TCAD.2002.804088⟩ Article dans une revue lirmm-00239324v1

	Iterative Method for Performance Prediction Improvement of Integrated Circuits Gwenael Chaillou , Philippe Maurine , Jean-Marc J.-M. Galliere , Nadine Azemard DCIS 2021 - 36th Conference on Design of Circuits and Integrated Systems, Nov 2021, Vila do Conde, Portugal. pp.1-5, ⟨10.1109/DCIS53048.2021.9666182⟩ Communication dans un congrès lirmm-03710383v1
	Statistical Cells Timing Metrics Characterization Nadine Azemard , Zeqin Wu , Philippe Maurine , Gilles R. Ducharme FTFC: Faible Tension - Faible Consommation, Jun 2012, Paris, France Communication dans un congrès lirmm-00762131v1
	Characterizing Statistical Cells Timing Metrics with Semi-Monte-Carlo Method Nadine Azemard , Zeqin Wu , Philippe Maurine , Gilles R. Ducharme VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2011, Hong-Kong, China Communication dans un congrès lirmm-00617606v1
	Statistical Timing Characterization of Standard Cells with Semi-Monte-Carlo Method Nadine Azemard , Zeqin Wu , Philippe Maurine , Gilles R. Ducharme VARI: Workshop on CMOS Variaility, May 2011, Grenoble, France Communication dans un congrès lirmm-00617593v1
	Computing Delay Correlations in SSTA Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme ICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.130-133, ⟨10.1109/ICICDT.2010.5510277⟩ Communication dans un congrès lirmm-00546301v1
	SSTA with Cell-to-Cell Delay Correlations Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme VARI: Workshop on CMOS Variability, May 2010, Montpellier, France Communication dans un congrès lirmm-00546322v1
	SSTA with Delay Correlations Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme NEWCAS: New Circuits and Systems, Jun 2010, Montreal, QC, Canada. pp.261-266, ⟨10.1109/NEWCAS.2010.5603930⟩ Communication dans un congrès lirmm-00504882v1
	Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPC Nabila Moubdi , Philippe Maurine , Nadine Azemard , Robin M. Wilson , Sylvain Engels ICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.82-85, ⟨10.1109/ICICDT.2010.5510289⟩ Communication dans un congrès lirmm-00546316v1
	On-Chip Process Variability Monitoring Nabila Moubdi , Philippe Maurine , Robin M. Wilson , Nadine Azemard , Vincent Dumettier VARI: Workshop on CMOS Variability, May 2010, Montpellier, France Communication dans un congrès lirmm-00546337v1
	On-Chip Process Variability Monitoring Nabila Moubdi , Robin M. Wilson , Sylvain Engels , Nadine Azemard , Philippe Maurine DATE: Design, Automation and Test in Europe, Apr 2009, Nice, France Communication dans un congrès lirmm-00374368v1
	An Innovative Timing Slack Monitor for Variation Tolerant Circuits Bettina Rebaud , Marc Belleville , Edith Beigné , Michel Robert , Philippe Maurine ICICDT: International Conference on IC Design & Technology, May 2009, Austin, TX, United States. pp.215-218, ⟨10.1109/ICICDT.2009.5166299⟩ Communication dans un congrès lirmm-00371174v1
	On-Chip Timing Slack Monitoring Bettina Rebaud , Marc Belleville , Edith Beigné , Michel Robert , Philippe Maurine VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2009, Florianopolis, Brazil. pp.89-94, ⟨10.1109/VLSISOC.2009.6041336⟩ Communication dans un congrès lirmm-00429350v1
	Product On-Chip Process Compensation for Low Power and Yield Enhancement Nabila Moubdi , Philippe Maurine , Robin M. Wilson , Nadine Azemard , Vincent Dumettier PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.247-255, ⟨10.1007/978-3-642-11802-9_29⟩ Communication dans un congrès lirmm-00433504v1
	Interpretation of SSTA Results Zeqin Wu , Nadine Azemard , Philippe Maurine , Gilles R. Ducharme FTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Switzerland Communication dans un congrès lirmm-00374060v1
	Interpreting SSTA Results with Correlation Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.16-25, ⟨10.1007/978-3-642-11802-9_6⟩ Communication dans un congrès lirmm-00433505v1
	Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of Variabilities Bettina Rebaud , Marc Belleville , Edith Beigné , Christian Bernard , Michel Robert PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.266-275, ⟨10.1007/978-3-642-11802-9_31⟩ Communication dans un congrès lirmm-00433462v1
	Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variations Bettina Rebaud , Marc Belleville , Edith Beigné , Michel Robert , Philippe Maurine FTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Suisse Communication dans un congrès lirmm-00404810v1
	SSTA with Structure Correlations Considering input Slope and Output Load Variations Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme GDR SOC-SIP, Jun 2008, Paris, France. pp.3 Communication dans un congrès lirmm-00340231v1
	SSTA Considering Switching Process Induced Correlations Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme APCCAS: Asia Pacific Conference on Circuits and System, Nov 2008, Macao, China. pp.562-565, ⟨10.1109/APCCAS.2008.4746085⟩ Communication dans un congrès lirmm-00340564v1
	Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier Bettina Rebaud , Marc Belleville , Christian Bernard , Zeqin Wu , Michel Robert ISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩ Communication dans un congrès lirmm-00280809v1
	Conditional Moments based SSTA Considering Switching Process Induced Correlations Zeqin Wu , Philippe Maurine , Gilles R. Ducharme , Nadine Azemard DCIS: Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. pp.70-77 Communication dans un congrès lirmm-00340221v1
	SSTA Considering Effects of Structure Correlations, Input Slope and Output Load Variations Zeqin Wu , Philippe Maurine , Gilles R. Ducharme , Nadine Azemard FTFC: Faible Tension - Faible Consommation, May 2008, Louvain-la-Neuve, Belgium. pp.39-43 Communication dans un congrès lirmm-00288537v1
	Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numérique Bettina Rebaud , Marc Belleville , Christian Bernard , Zeqin Wu , Michel Robert FTFC: Faible Tension - Faible Consommation, May 2008, Louvain-La-Neuve, Belgique Communication dans un congrès lirmm-00283731v1
	Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétique Bettina Rebaud , Zeqin Wu , Marc Belleville , Christian Bernard , Michel Robert JNRDM 2008 - 11e Journées Nationales du Réseau Doctoral de Microélectronique, May 2008, Bordeaux, France Communication dans un congrès lirmm-00281175v2
	SSTA with Correlations Considering input Slope and Output Load Variations Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2008, Rhodes Island, Greece. pp.164-167 Communication dans un congrès lirmm-00332757v1
	Une Famille d'Additionneurs Asynchrones CMOS Bundled Data à Temps de Calcul Dépendant aux Données Robin Perrot , Nadine Azemard , Philippe Maurine FTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.75-80 Communication dans un congrès lirmm-00178466v1
	A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation Vincent Migairou , Robin Wilson , Sylvain Engels , Zeqin Wu , Nadine Azemard FTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.19-25 Communication dans un congrès lirmm-00178454v1
	A Simple Statistical Timing Analysis Flow and its Application to Timing Margin Evaluation Vincent Migairou , Robin Wilson , Sylvain Engels , Zeqin Wu , Nadine Azemard PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.138-147, ⟨10.1007/978-3-540-74442-9_14⟩ Communication dans un congrès lirmm-00175076v1
	Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops Benoit Lasbouygues , Robin M. Wilson , Nadine Azemard , Philippe Maurine DATE: Design, Automation and Test in Europe, Mar 2007, Nice, France. ⟨10.1109/DATE.2007.364426⟩ Communication dans un congrès lirmm-00178525v1
	Une Famille d'Additionneur Asynchrones CMOS à Temps de Calcul Dépendant de Données Robin Perrot , Nadine Azemard , Philippe Maurine JNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. pp.469-472 Communication dans un congrès lirmm-00102842v1
	Exploration of the Area-Latency Tradeoff of Asynchronous CMOS data Dependent Adders Robin Perrot , Philippe Maurine , Nadine Azemard DCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain Communication dans un congrès lirmm-00117102v1
	Timing Analysis in Presence of Voltage Drops and Temperature Gradients Benoit Lasbouygues , Robin M. Wilson , Nadine Azemard , Philippe Maurine TAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. pp.28-34 Communication dans un congrès lirmm-00106705v1
	Timing Analysis in Presence of Supply Voltage and Temperature Variations Benoit Lasbouygues , Robin M. Wilson , Nadine Azemard , Philippe Maurine ISPD: International Symposium on Physical Design, Apr 2006, San Jose, CA, United States. pp.10-16, ⟨10.1145/1123008.1123012⟩ Communication dans un congrès lirmm-00102760v1
	Request-Skip Adders: CMOS Standard Cell Data Dependent Adders Robin Perrot , Nadine Azemard , Philippe Maurine ICECS: International Conference on Electronics, Circuits and Systems, Dec 2006, Nice, France. pp.510-513, ⟨10.1109/ICECS.2006.379837⟩ Communication dans un congrès lirmm-00130195v1
	Statistical Characterization of Library Timing Performance Vincent Migairou , Robin P. Wilson , Sylvain Engels , Nadine Azemard , Philippe Maurine PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2006, Montpellier, France. pp.468-476, ⟨10.1007/11847083_45⟩ Communication dans un congrès lirmm-00093233v1
	Circuit Sizing Method under Delay Constraint Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard ISCAS: International Symposium on Circuits and Systems, May 2006, Island of Kos, Greece. pp.5123-5126, ⟨10.1109/ISCAS.2006.1693785⟩ Communication dans un congrès lirmm-00106911v1
	Circuit Performance Optimization under Delay Constraints Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard DCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain Communication dans un congrès lirmm-00117119v1
	Optimization Protocol Based on Low Power Metrics Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard IWLS: International Workshop on Logic Synthesis, Jun 2005, Lake Arrowhead Resort, CA, United States. pp.288-293 Communication dans un congrès lirmm-00106018v1
	Speed Indicators for Circuit Optimization Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.618-628, ⟨10.1007/11556930_63⟩ Communication dans un congrès lirmm-00106076v1
	Protocole d'Optimisation de Circuit CMOS Orienté Basse Puissance Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.17-22 Communication dans un congrès lirmm-00106002v1
	Synthèse Physique et Optimisation des Performances au Niveau Transistor Alexis Landrault , Alexandre Verle , Philippe Maurine , Nadine Azemard FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.91-95 Communication dans un congrès lirmm-00106004v1
	Ripple Carry Adder for Micropipeline Circuits Robin Perrot , Nadine Azemard , Philippe Maurine DCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal Communication dans un congrès lirmm-00106075v1
	Circuit Optimization Based on Speed Indicators Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard ICECS: International Conference on Electronics, Circuits and Systems, Dec 2005, Gammarth, Tunisia. pp.167-170, ⟨10.1109/icecs.2005.4633585⟩ Communication dans un congrès lirmm-00106439v1
	Path Optimization Protocol Based on Speed Low Power Metrics Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard EUROCON: International Conference on "Computer as a Tool", Nov 2005, Belgrade, Serbia. pp.523-526, ⟨10.1109/EURCON.2005.1629980⟩ Communication dans un congrès lirmm-00106428v1
	Temperature Dependency in UDSM Process Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.693-703, ⟨10.1007/11556930_71⟩ Communication dans un congrès lirmm-00106077v1
	Additionneurs RCA Data Dependent Micropipelines Robin Perrot , Nadine Azemard , Philippe Maurine FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.183-188 Communication dans un congrès lirmm-00106005v1
	Low Power Oriented CMOS Circuit Optimization Protocol Alexandre Verle , Xavier Michel , Nadine Azemard , Philippe Maurine , Daniel Auvergne DATE 2005 - 8th Design, Automation and Test in Europe Conference and Exhibition, Mar 2005, Munich, Germany. pp.640-645, ⟨10.1109/DATE.2005.202⟩ Communication dans un congrès lirmm-00106452v1
	Design Optimization with Automated Cell Generation Alexis Landrault , Nadine Azemard , Philippe Maurine , Michel Robert , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.722-731, ⟨10.1007/978-3-540-30205-6_74⟩ Communication dans un congrès lirmm-00108894v1
	Temperature Dependence in Low Power CMOS UDSM Process Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.111-118, ⟨10.1007/978-3-540-30205-6_13⟩ Communication dans un congrès lirmm-00108893v1
	Automatic Layout Synthesis Based Performance Optimization Alexis Landrault , Nadine Azemard , Philippe Maurine , Michel Robert , Daniel Auvergne IWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85 Communication dans un congrès lirmm-00108654v1
	Optimization Protocol Based on Performance Metric Xavier Michel , Alexandre Verle , Nadine Azemard , Philippe Maurine , Daniel Auvergne DCIS 2004 - 19th International Conference on Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.964-968 Communication dans un congrès lirmm-00108935v1
	Delay Bound Based CMOS Gate Sizing Technique Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne ISCAS: International Symposium on Circuits and Systems, May 2004, Vancouver, BC, Canada. pp.189-192, ⟨10.1109/ISCAS.2004.1329494⟩ Communication dans un congrès lirmm-00108856v1
	Performance Metric Based Optimization Protocol Xavier Michel , Alexandre Verle , Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.100-109, ⟨10.1007/978-3-540-30205-6_12⟩ Communication dans un congrès lirmm-00108892v1
	Definition of P/N Width Ratio for CMOS Standard Cell Library Alexandre Verle , Philippe Maurine , Nadine Azemard , Daniel Auvergne DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.769-773 Communication dans un congrès lirmm-00108933v1
	RC on-chip interconnect Performance revisited Philippe Maurine , Nadine Azemard , Daniel Auvergne DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.809-814 Communication dans un congrès lirmm-00108934v1
	Physical Extension of the Logical Effort Model Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.838-848, ⟨10.1007/978-3-540-30205-6_86⟩ Communication dans un congrès lirmm-00108895v1
	CMOS Gate Sizing under Delay Constraint Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Torino, Italy. pp.60-69, ⟨10.1007/978-3-540-39762-5_8⟩ Communication dans un congrès lirmm-00244021v1
	Dimensionnement de Portes CMOS Sous Contrainte de Délai Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.111-117 Communication dans un congrès lirmm-00269522v1
	Définition d'une Métrique d'Insertion de Buffers Xavier Michel , Alexandre Verle , Nadine Azemard , Philippe Maurine , Daniel Auvergne FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.131-136 Communication dans un congrès lirmm-00269520v1
	Timing Performance Representation of a CMOS Standard Cell Library Benoit Lasbouygues , J. Schindler , Sylvain Engels , Philippe Maurine , Xavier Michel DCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. pp.83-88 Communication dans un congrès lirmm-00239460v1
	Metric Definition for Circuit Speed Optimization Xavier Michel , Alexandre Verle , Nadine Azemard , Philippe Maurine , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. pp.451-460 Communication dans un congrès lirmm-00269568v1
	Metric Definition for Circuit Speed Optimization Xavier Michel , Alexandre Verle , Philippe Maurine , Nadine Azemard , Daniel Auvergne IWLS: International Workshop on Logic Synthesis, May 2003, Laguna Beach, CA, United States Communication dans un congrès lirmm-00269689v1
	Représentation Unifiée des Performances Temporelles d'une Bibliothèque de Cellules Standards Benoit Lasbouygues , J. Schindler , Sylvain Engels , Philippe Maurine , Nadine Azemard FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.119-124 Communication dans un congrès lirmm-00269519v1
	Continuous Representation of the Performance of a CMOS Library Benoit Lasbouygues , J. Schindler , Sylvain Engels , Philippe Maurine , Xavier Michel ESSCIRC: European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal. pp.595-598, ⟨10.1109/ESSCIRC.2003.1257205⟩ Communication dans un congrès lirmm-00239459v1
	Gate Speed Improvement at Minimal Power Dissipation Philippe Maurine , Xavier Michel , Nadine Azemard , Daniel Auvergne APPCAS: Asia-Pacific Conference on Circuits and Systems, Oct 2002, Denpasar, Bali, pp.278-282 Communication dans un congrès lirmm-00239453v1
	Defining the Maximum Speed of CMOS Gate Library Philippe Maurine , Nadine Azemard , Daniel Auvergne DCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.81-86 Communication dans un congrès lirmm-00239455v1
	Structure Independent Representation of Output Transition Time for CMOS Library Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2002, Seville, Spain. pp.247-257, ⟨10.1007/3-540-45716-X_25⟩ Communication dans un congrès lirmm-00244012v1
	Metric Definition for Buffer Insertion Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne DCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.307-312 Communication dans un congrès lirmm-00239458v1
	Evaluation et Optimisation de Chemins Combinatoires Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne Colloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.173-176 Communication dans un congrès lirmm-00269329v1
	Technological Assignment for a Minimal Power Consumption Philippe Maurine , Nadine Azemard , Daniel Auvergne VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.236-241 Communication dans un congrès lirmm-00239450v1
	Timing Closure Management based on Delay Bound Determination Nadine Azemard , Michel Aline , Philippe Maurine , Daniel Auvergne VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.430-434 Communication dans un congrès lirmm-00239452v1
	Full Analyttical Model for delay Performance Estimation in Submicron CMOS Philippe Maurine , Nadine Azemard , Daniel Auvergne MIXDES: Mixed Design of Integrated Circuits and Systems, Jun 2001, Zakopane, Poland. pp.355-359 Communication dans un congrès lirmm-00239444v1
	Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination Philippe Maurine , Nadine Azemard , Daniel Auvergne PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2001, Yverdon-Les-Bains, Switzerland. pp.5.3.1-5.3.10 Communication dans un congrès lirmm-00244010v1
	Delay Bound Determination for Timing Closure on CMOS Circuits Nadine Azemard , Michel Aline , Philippe Maurine , Daniel Auvergne IWLS: International Workshop on Logic and Synthesis, Jun 2001, Granlibakken Conference Center, United States. pp.96-100 Communication dans un congrès lirmm-00244007v1
	Switching Current Modeling in CMOS Inverter for Speed and Power Estimation Philippe Maurine , Régis Poirier , Nadine Azemard , Daniel Auvergne DCIS: Design of Circuits and Integrated Systems, Nov 2001, Porto, Portugal. pp.618-622 Communication dans un congrès lirmm-00239448v1
	Performance Indicators for Designing CMOS Logic Philippe Maurine , Nadine Azemard , Daniel Auvergne ICM: International Conference on Microelectronics, Oct 2001, Rabat, Morocco. pp.99-102, ⟨10.1109/ICM.2001.997497⟩ Communication dans un congrès lirmm-00239446v1

	Méthode Itérative pour l’Amélioration de la Prédiction des Performances des Circuits Intégrés Gwenael Chaillou , Philippe Maurine , Jean-Marc J.-M. Galliere , Nadine Azemard 15e Colloque National du GDR SoC², Jun 2021, Rennes, France Poster de conférence lirmm-03358670v1
	Statistical Timing Characterization Nadine Azemard , Zeqin Wu , Philippe Maurine , Gilles R. Ducharme SoC: System on Chip, Oct 2012, Tampere, Finland. International Symposium on System on Chip, 2012, ⟨10.1109/ISSoC.2012.6376360⟩ Poster de conférence lirmm-00762107v1

	Integration, the VLSI Journal Nadine Azemard , Philippe Maurine , Johan Vounckx Elsevier, 41 (1), 160 p., 2008, Power and Timing Modeling, Optimization and Simulation (Special Issue), ⟨10.1016/j.vlsi.2007.06.004⟩ Ouvrages lirmm-00189961v1
	Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Johan Vounckx , Nadine Azemard , Philippe Maurine Springer, LNCS (4148), 677 p., 2006, 978-3-540-39097-8. ⟨10.1007/11847083⟩ Ouvrages lirmm-00135046v1

	Towards Autonomous Scalable Integrated Systems Pascal Benoit , Gilles Sassatelli , Philippe Maurine , Lionel Torres , Nadine Azemard Design Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. ⟨10.1007/978-94-007-1125-9_4⟩ Chapitre d'ouvrage lirmm-01399454v1
	Modeling for Designing in Deep Sub-Micron Technologies Daniel Auvergne , Philippe Maurine , Nadine Azemard PIGUET C. Low-Power Electronics Design, CPR Press, 2004, 0-8493-1941-2 Chapitre d'ouvrage lirmm-00109162v1
	Feasible delay Bound Definition Nadine Azemard , Michel Aline , Philippe Maurine , Daniel Auvergne SOC Design Methodologies, 90, Kluwer Academic Publishers, pp.325-335, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_40⟩ Chapitre d'ouvrage lirmm-00239363v1
	Gate Sizing for Low Power Design Philippe Maurine , Nadine Azemard , Daniel Auvergne SOC Design Methodologies, 90, Kluwer Academic Publishers, pp.301-312, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_26⟩ Chapitre d'ouvrage lirmm-00239359v1

Nadine Azemard

Présentation

Publications

Delay-correlation-aware SSTA based on conditional moments

Timing Slack Monitoring under Process and Environmental Variations: Application to a DSP Performance Optimization

On-Chip Process Variability Monitoring Flow

Timing Margin Evaluation with a Simple Statistical Timing Analysis Flow

Temperature and Voltage Aware Timing Analysis

A Comprehensive Performance Macro-Modeling of on-Chip RC Interconnects Considering Line Shielding Effects

Logical Effort Model Extension to Propagation Delay Representation

Delay Bounds Based Constraint Distribution Method

General Representation of CMOS Structure Transition time for Timing Library Representation

Transition Time Modeling in Deep Submicron CMOS

Iterative Method for Performance Prediction Improvement of Integrated Circuits

Statistical Cells Timing Metrics Characterization

Characterizing Statistical Cells Timing Metrics with Semi-Monte-Carlo Method

Statistical Timing Characterization of Standard Cells with Semi-Monte-Carlo Method

Computing Delay Correlations in SSTA

SSTA with Cell-to-Cell Delay Correlations

SSTA with Delay Correlations

Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPC

On-Chip Process Variability Monitoring

On-Chip Process Variability Monitoring

An Innovative Timing Slack Monitor for Variation Tolerant Circuits

On-Chip Timing Slack Monitoring

Product On-Chip Process Compensation for Low Power and Yield Enhancement

Interpretation of SSTA Results

Interpreting SSTA Results with Correlation

Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of Variabilities

Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variations

SSTA with Structure Correlations Considering input Slope and Output Load Variations

SSTA Considering Switching Process Induced Correlations

Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier

Conditional Moments based SSTA Considering Switching Process Induced Correlations

SSTA Considering Effects of Structure Correlations, Input Slope and Output Load Variations

Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numérique

Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétique

SSTA with Correlations Considering input Slope and Output Load Variations

Une Famille d'Additionneurs Asynchrones CMOS Bundled Data à Temps de Calcul Dépendant aux Données

A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation

A Simple Statistical Timing Analysis Flow and its Application to Timing Margin Evaluation

Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops

Une Famille d'Additionneur Asynchrones CMOS à Temps de Calcul Dépendant de Données

Exploration of the Area-Latency Tradeoff of Asynchronous CMOS data Dependent Adders

Timing Analysis in Presence of Voltage Drops and Temperature Gradients

Timing Analysis in Presence of Supply Voltage and Temperature Variations

Request-Skip Adders: CMOS Standard Cell Data Dependent Adders

Statistical Characterization of Library Timing Performance

Circuit Sizing Method under Delay Constraint

Circuit Performance Optimization under Delay Constraints

Optimization Protocol Based on Low Power Metrics

Speed Indicators for Circuit Optimization

Protocole d'Optimisation de Circuit CMOS Orienté Basse Puissance

Synthèse Physique et Optimisation des Performances au Niveau Transistor

Ripple Carry Adder for Micropipeline Circuits

Circuit Optimization Based on Speed Indicators

Path Optimization Protocol Based on Speed Low Power Metrics

Temperature Dependency in UDSM Process

Additionneurs RCA Data Dependent Micropipelines

Low Power Oriented CMOS Circuit Optimization Protocol

Design Optimization with Automated Cell Generation

Temperature Dependence in Low Power CMOS UDSM Process

Automatic Layout Synthesis Based Performance Optimization

Optimization Protocol Based on Performance Metric

Delay Bound Based CMOS Gate Sizing Technique

Performance Metric Based Optimization Protocol

Definition of P/N Width Ratio for CMOS Standard Cell Library

RC on-chip interconnect Performance revisited

Physical Extension of the Logical Effort Model

CMOS Gate Sizing under Delay Constraint

Dimensionnement de Portes CMOS Sous Contrainte de Délai

Définition d'une Métrique d'Insertion de Buffers

Timing Performance Representation of a CMOS Standard Cell Library

Metric Definition for Circuit Speed Optimization

Metric Definition for Circuit Speed Optimization

Représentation Unifiée des Performances Temporelles d'une Bibliothèque de Cellules Standards

Continuous Representation of the Performance of a CMOS Library

Gate Speed Improvement at Minimal Power Dissipation

Defining the Maximum Speed of CMOS Gate Library

Structure Independent Representation of Output Transition Time for CMOS Library