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    Article dans une revue19 documents

    • Kheirallah Rida, Gilles Ducharme, Nadine Azemard. Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices. Journal of Low Power Electronics, American Scientific Publishers, 2016, 12 (1), pp.58-63. 〈lirmm-01295833〉
    • Rida Kheirallah, Gilles Ducharme, Nadine Azemard. Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices. Journal of Low Power Electronics, American Scientific Publishers, 2016, 12 (1), pp.58-63. 〈10.1166/jolpe.2016.1420〉. 〈hal-01825073〉
    • Zeqin Wu, Nadine Azemard, Gilles R. Ducharme, Philippe Maurine. Delay-correlation-aware SSTA based on conditional moments. Microelectronics Journal, Elsevier, 2012, 43 (4), pp.263-273. 〈10.1016/j.mejo.2012.01.003〉. 〈lirmm-00761821〉
    • Philippe Maurine, Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, et al.. Timing Slack Monitoring under Process and Environmental Variations: Application to a DSP Performance Optimization. Microelectronics Journal, Elsevier, 2011, 42 (5), pp.718-732. 〈lirmm-00607877〉
    • Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Sylvain Engels, et al.. On-Chip Process Variability Monitoring Flow. Journal of Low Power Electronics, American Scientific Publishers, 2010, 6 (4), pp.601-606. 〈10.1166/jolpe.2010.1109〉. 〈lirmm-00546368〉
    • Sylvain Engels, Robin Wilson, Nadine Azemard, Philippe Maurine, Vincent Migairou. Timing Margin Evaluation with a Simple Statistical Timing Analysis Flow. Journal of Embedded Computing, IOS Press, 2009, 3 (3), pp.221-229. 〈lirmm-00371162〉
    • Benoit Lasbouygues, R. Wilson, Nadine Azemard, Philippe Maurine. Temperature and Voltage Aware Timing Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2007, 26 (4), pp.801-815. 〈lirmm-00178921〉
    • S. Engels, R. Wilson, Nadine Azemard, Philippe Maurine. A Comprehensive Performance Macro-Modeling of on-Chip RC Interconnects Considering Line Shielding Effects. Integration, the VLSI Journal, Elsevier, 2006, 39, pp.433-456. 〈lirmm-00106854〉
    • Benoit Lasbouygues, S. Engels, R. Wilson, Philippe Maurine, Nadine Azemard, et al.. Logical Effort Model Extension to Propagation Delay Representation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2006, 25 (9), pp.1677-1684. 〈lirmm-00104315〉
    • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Delay Bounds Based Constraint Distribution Method. IEE Proceedings - Computers and Digital Techniques (1994-2006), Institution of Engineering and Technology, 2005, 152 (6), pp.765-770. 〈10.1049/ip-cdt:20050026〉. 〈lirmm-00105370〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. General Representation of CMOS Structure Transition Time for Timing Library Representation. Electronics Letters, IET, 2002, 38 (4), pp.175-177. 〈lirmm-00268588〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. General Representation of CMOS Structure Transition time for Timing Library Representation. Electronics Letters, IET, 2002, 38 (4), pp.175-177. 〈lirmm-00239318〉
    • Philippe Maurine, Mustapha Rezzoug, Nadine Azemard, Daniel Auvergne. Transition Time Modeling in Deep Submicron CMOS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2002, 21 (11), pp.1352- 1363. 〈lirmm-00239324〉
    • Philippe Maurine, Mustapha Rezzoug, Nadine Azemard, Daniel Auvergne. Transition Time Modeling in Deep Submicron CMOS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2002, 21 (11), pp.1352-1363. 〈lirmm-00268437〉
    • Nadine Azemard, Daniel Auvergne. POPS: A tool for delay/power performance optimization. Journal of Systems Architecture, Elsevier, 2001, 47 (3), pp.375-382. 〈10.1016/S1383-7621(00)00055-2〉. 〈lirmm-00239314〉
    • Michel Robert, Guy Cathébras, Nadine Azemard, Denis Deschacht, Daniel Auvergne. A Performance Driven Layout Synthesis Approach for Digital CMOS Cell Implementation. Integration, the VLSI Journal, Elsevier, 1993, N/A, pp.N/A. 〈lirmm-00239254〉
    • Denis Deschacht, Michel Robert, Nadine Azemard, Daniel Auvergne. Post-Layout Timing Simulation of CMOS Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 1993, 12 (8), pp.1170-1177. 〈lirmm-00239206〉
    • Daniel Auvergne, Nadine Azemard, Denis Deschacht, Michel Robert. Input Waveform Slope Effects in CMOS Delays. IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 1990, 25 (6), pp.1588-1590. 〈lirmm-00239201〉
    • Daniel Auvergne, Nadine Azemard, Guy Cathébras, Denis Deschacht, Michel Robert. Evaluation Dynamique et Optimisation des Structures CMOS et VLSI. Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, Lavoisier, 1989, 8 (6), pp.593-607. 〈lirmm-00239199〉

    Communication dans un congrès132 documents

    • Rida Kheirallah, Jean-Marc Galliere, Gilles Ducharme, Nadine Azemard. Combined analysis of supply voltage and body-bias voltage for energy management. PATMOS: Power and Timing Modeling, Optimization and Simulation, Jul 2018, Platja d’Aro, Spain. 28th IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation, 2018, 〈http://patmos2018.die.upm.es〉. 〈lirmm-01867809〉
    • Nicolas Jeanniot, Gael Pillonnet, Pascal Nouet, Nadine Azemard, Aida Todri-Sanial. Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic. ICRC: International Conference on Rebooting Computing, Nov 2017, Washington, DC, United States. IEEE, IEEE International Conference on Rebooting Computing, 2017, 〈10.1109/ICRC.2017.8123661〉. 〈lirmm-01768831〉
    • Jie Liang, Lee Jaehyun, Salim Berrada, Vihar P. Georgiev, Asenov Asen, et al.. Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application. NMDC: Nanotechnology Materials and Devices Conference, Oct 2017, Singapore, Singapore. IEEE 12th Nanotechnology Materials and Devices Conference, 2017, 〈https://ieeexplore.ieee.org/document/8350506/〉. 〈10.1109/NMDC.2017.8350506〉. 〈lirmm-01880220〉
    • Jie Liang, Liuyang Zhang, Nadine Azemard, Pascal Nouet, Aida Todri-Sanial. Physical description and analysis of doped carbon nanotube interconnects. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2016, Brême, Germany. IEEE, 26th IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.250-255, 2016, 〈10.1109/PATMOS.2016.7833695〉. 〈lirmm-01457338〉
    • Kheirallah Rida, Jean-Marc Galliere, Aida Todri-Sanial, Gilles Ducharme, Nadine Azemard. Statistical Energy Study for 28nm FDSOI Devices. EuroSimE: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Apr 2015, Budapest, Hungary. Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2015 16th International Conference on, 2015, 〈10.1109/EuroSimE.2015.7103149〉. 〈lirmm-01168602〉
    • Kheirallah Rida, Gilles Ducharme, Nadine Azemard. Statistical Energy Study for 28nm FDSOI Technology. VARI: Workshop on CMOS Variability, Sep 2015, Salvador, Bahia, Brazil. 2015, 6th International Workshop on CMOS Variability. 〈http://www.inf.ufrgs.br/vari/〉. 〈lirmm-01256280〉
    • Nadine Azemard, Zeqin Wu, Philippe Maurine, Gille Ducharme. Statistical Cells Timing Metrics Characterization. FTFC'12: IEEE Faible Tension Faible Consommation, Jun 2012, Paris, France. session4-paper3, 2012. 〈lirmm-00762131〉
    • Nadine Azemard. VARI Worshop Overview. DCIS'12: XXVII Design of Circuits and Integrated Systems Conference, Nov 2012, Avignon, France. pp.159-161, 2012. 〈lirmm-00762113〉
    • Nadine Azemard, Zeqin Wu, Philippe Maurine, Gille Ducharme. Statistical Timing Characterization of Standard Cells with Semi-Monte-Carlo Method. VARI: Workshop on CMOS Variaility, May 2011, Grenoble, France. 2011, 2nd European Workshop on CMOS Variaility. 〈lirmm-00617593〉
    • Nadine Azemard, Zeqin Wu, Philippe Maurine, Gille Ducharme. Characterizing Statistical Cells Timing Metrics with Semi-Monte-Carlo Method. VLSI-Soc'11 : IFIP/IEEE International Conference on Very Large Scale Integration, Oct 2011, Hong-Kong, China. pp.6, 2011. 〈lirmm-00617606〉
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. SSTA with Cell-to-Cell Delay Correlations. VARI: Workshop on CMOS Variability, May 2010, Montpellier, France. 2010, 1st European Workshop on CMOS Variability. 〈lirmm-00546322〉
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. Computing Delay Correlations in SSTA. ICICDT'10: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.N/A, 2010. 〈lirmm-00546301〉
    • Nabila Moubdi, Philippe Maurine, Nadine Azemard, Robin Wilson, Sylvain Engels. Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPC. ICICDT'10: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.N/A, 2010. 〈lirmm-00546316〉
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. SSTA with Delay Correlations. NEWCAS: International New Circuits and Systems Conference, Jun 2010, Montreal, Canada. 8th IEEE International NEWCAS Conference, pp.261-266, 2010, 〈http://newcas.grm.polymtl.ca/keynotes.html〉. 〈lirmm-00504882〉
    • Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Vincent Dumettier, et al.. On-Chip Process Variability Monitoring. VARI: Workshop on CMOS Variability, May 2010, Montpellier, France. 2010, 1st European Workshop on CMOS Variability. 〈lirmm-00546337〉
    • Bettina Rebaud, Marc Belleville, Edith Beigne, Michel Robert, Philippe Maurine, et al.. An Innovative Timing Slack Monitor for Variation Tolerant Circuits. ICICDT'09: International Conference on IC Design & Technology, May 2009, Austin, Texas, USA, pp.215-218, 2009. 〈lirmm-00371174〉
    • Zeqin Wu, Nadine Azemard, Philippe Maurine, Gille Ducharme. Interpretation of SSTA Results. FTFC'09 : 8èmes Journées Faible Tension Faible Consommation, Jun 2009, Neuchâtel, Switzerland. pp.N/A, 2009. 〈lirmm-00374060〉
    • Nabila Moubdi, Robin Wilson, Sylvain Engels, Nadine Azemard, Philippe Maurine. On-Chip Process Variability Monitoring. DATE: Design, Automation and Test in Europe, Apr 2009, Nice, France. 2009, W2. 〈lirmm-00374368〉
    • Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Vincent Dumettier, et al.. Product On-Chip Process Compensation for Low Power and Yield Enhancement. Patmos'09: 19th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2009, Delft, Netherlands. Springer, pp.247-255, 2009. 〈lirmm-00433504〉
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. Interpreting SSTA Results with Correlation. Springer. PATMOS'09: 19th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.16-25, 2009. 〈lirmm-00433505〉
    • Bettina Rebaud, Marc Belleville, Edith Beigne, Michel Robert, Philippe Maurine, et al.. Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variations. FTFC'09 : 8èmes Journées d'Etudes Faible Tension Faible Consommation, Jun 2009, Neuchâtel, Suisse, pp.N/A, 2009, 〈http://www.isep.fr/ftfc/public/index.php〉. 〈lirmm-00404810〉
    • Bettina Rebaud, Marc Belleville, Edith Beigne, Michel Robert, Philippe Maurine, et al.. On-Chip Timing Slack Monitoring. VLSI-SOC 2009: IFIP/IEEE International Conference on Very Large Scale Integration, Oct 2009, Florianopolis, Brazil. pp.89-94, 2009, Session: Physical Design, Low Power Design. 〈10.1109/VLSISOC.2009.6041336〉. 〈lirmm-00429350〉
    • Bettina Rebaud, Marc Belleville, Edith Beigne, Christian Bernard, Michel Robert, et al.. Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of Variabilities. Patmos'09: 19th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2009, Delft, Netherlands. Springer, pp.266-275, 2009. 〈lirmm-00433462〉
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. SSTA with Structure Correlations Considering input Slope and Output Load Variations. GDR SOC-SIP, Jun 2008, Paris, France. pp.3, 2008. 〈lirmm-00340231〉
    • Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Définition d'une Métrique d'Insertion de Buffers. FTFC'03 : 4èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, Paris (France), pp. 131-136, 2003. 〈lirmm-00269520〉
    • Bettina Rebaud, Marc Belleville, Christian Bernard, Michel Robert, Patrick Maurine, et al.. A Comparative Study of Variability Impact on Static Flip-Flop Timing Characteristics. ICICDT: International Conference on IC Design and Technology, Jun 2008, Grenoble, France. IEEE, International Conference on IC Design and Technology, pp.167-170, 2008, 〈http://www.ICICDT.org〉. 〈lirmm-00305246〉
    • Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Evaluation et Optimisation de Chemins Combinatoires. Colloque du GDR CAO de Circuits et Systèmes Intégrés, Paris (France), France. pp. 173-176, 2002. 〈lirmm-00269329〉
    • Benoit Lasbouygues, J. Schindler, S. Engels, Philippe Maurine, Nadine Azemard, et al.. Représentation Unifiée des Performances Temporelles d'une Bibliothèque de Cellules Standards. FTFC'03 : 4èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, Paris (France), pp. 119-124, 2003. 〈lirmm-00269519〉
    • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Dimensionnement de Portes CMOS Sous Contrainte de Délai. FTFC'03 : 4èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, Paris (France), pp. 111-117, 2003. 〈lirmm-00269522〉
    • Benoit Lasbouygues, J. Schindler, S. Engels, Philippe Maurine, Xavier Michel, et al.. Continuous Representation of the Performance of a CMOS Library. ESSCIRC'03: 29th European Solid-State Circuits Conference, Estoril (Portugal), pp. 595-598, 2003. 〈lirmm-00269690〉
    • Xavier Michel, Nadine Azemard, Daniel Auvergne. Metric Definition for Buffer Insertion. DCIS'02: 17th International Conference on Design of Circuits and Integrated Systems, Santander (Spain), pp.307-312, 2002. 〈lirmm-00268433〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Structure Independant Representation of Output Transition Time for CMOS Library. PATMOS'02: 12th International Workshop on Power and Timing ModelingOptimization and Simulation, Seville, Espagne, Springer, pp.247-257, 2002, Lecture Notes in Computer Science. 〈lirmm-00268618〉
    • Philippe Maurine, Xavier Michel, Nadine Azemard, Daniel Auvergne. Gate Speed Improvement at Minimal Power Dissipation. APPCAS'02, Denpasar, Bali, pp.278-282, 2002. 〈lirmm-00268628〉
    • Nadine Azemard, Philippe Maurine, Daniel Auvergne. Feasible Delay Bound Definition. SoC Design Methodologies - 11th International Conference on Very Large Scale Integration of Systems-on-Chips, Montpellier, France, Kluwer Academic Publishers, pp.325-335, 2002. 〈lirmm-00268478〉
    • Séverine Cremoux, Nadine Azemard, Daniel Auvergne. Path Selection for Delay and Power Performance Optimization. SAME'98 : Sophia Antipolis Forum on Microelectronics, Sophia Antipolis, Nice, France, pp.48-53, 1998. 〈lirmm-00239415〉
    • Zeqin Wu, Philippe Maurine, Gille Ducharme, Nadine Azemard. SSTA Considering Effects of Structure Correlations, Input Slope and Output Load Variations. FTFC'08 : 7èmes Journées d'Etudes Faible Tension Faible Consommation, May 2008, Louvain-la-Neuve, Belgique, pp.39-43, 2008, 〈www.isep.fr/ftfc〉. 〈lirmm-00288537〉
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. SSTA with Correlations Considering input Slope and Output Load Variations. IFIP VLSI-SOC 2008 - IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, Rhodes, Greece, pp.164-167, 2008. 〈lirmm-00332757〉
    • Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, et al.. Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numérique. FTFC'08 : 7èmes Journées d'Etudes Faible Tension Faible Consommation, May 2008, Louvain-La-Neuve, Belgique. pp.N/A, 2008, 〈http://www.isep.fr/ftfc/〉. 〈lirmm-00283731〉
    • Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, et al.. Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, IEEE, pp.316-321, 2008. 〈lirmm-00280809〉
    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. SSTA Considering Switching Process Induced Correlations. APCCAS'08: IEEE Asia Pacific Conference on Circuits and System, Nov 2008, pp.562-565, 2008. 〈lirmm-00340564〉
    • Zeqin Wu, Philippe Maurine, Gille Ducharme, Nadine Azemard. Conditional Moments based SSTA Considering Switching Process Induced Correlations. DCIS'08: Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. pp.70-77, 2008, 〈http://obaldia.imag.fr/〉. 〈lirmm-00340221〉
    • Bettina Rebaud, Zeqin Wu, Marc Belleville, Christian Bernard, Michel Robert, et al.. Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétique. JNRDM'08 : Journées Nationales du Réseau Doctoral en Microélectronique, May 2008, pp.N/A, 2008, 〈http://www.u-bordeaux1.fr/jnrdm/〉. 〈lirmm-00281175v2〉
    • V. Migairou, R. Wilson, S. Engels, Zeqin Wu, Nadine Azemard, et al.. A Simple Statistical Timing Analysis Flow and its Application to Timing Margin Evaluation. PATMOS'07: Power and Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden, Springer, pp.138-147, 2007, LNCS. 〈lirmm-00175076〉
    • V. Migairou, R. Wilson, S. Engels, Zeqin Wu, Nadine Azemard, et al.. A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. FTFC 2007 : 6èmes Journées d'Etudes Faible - Tension Faible Consommation, May 2007, Paris, France, pp.19-25, 2007, 〈http://www.isep.fr/ftfc〉. 〈lirmm-00178454〉
    • Robin Perrot, Nadine Azemard, Philippe Maurine. Une Famille d'Additionneurs Asynchrones CMOS Bundled Data à Temps de Calcul Dépendant aux Données. FTFC 2007: 6èmes Journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France, pp.75-80, 2007, 〈www.isep.fr/ftfc〉. 〈lirmm-00178466〉
    • Benoit Lasbouygues, Robin Wilson, Nadine Azemard, Philippe Maurine. Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops. DATE: Design, Automation and Test in Europe, Mar 2007, Nice, France. 2007, 〈10.1109/DATE.2007.364426〉. 〈lirmm-00178525〉
    • Robin Perrot, Nadine Azemard, Philippe Maurine. Une Famille d'Additionneur Asynchrones CMOS à Temps de Calcul Dépendant de Données. JNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. 9ièmes Journées Nationales du Réseau Doctoral de Microélectronique, pp.469-472, 2006. 〈lirmm-00102842〉
    • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Circuit Sizing Method under Delay Constraint. ISCAS'06: IEEE International Symposium on Circuits and Systems, May 2006, Kos (Greece), pp.5123-5126, 2006. 〈lirmm-00106911〉
    • Benoit Lasbouygues, Robin Wilson, Nadine Azemard, Philippe Maurine. Timing Analysis in Presence of Voltage Drops and Temperature Gradients. TAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.28-34, 2006. 〈lirmm-00106705〉
    • Robin Perrot, Nadine Azemard, Philippe Maurine. Request-Skip Adders: CMOS Standard Cell Data Dependent Adders. ICECS'06: 13th IEEE International Conference on Electronics, Circuits and Systems, Dec 2006, Nice (France), pp.510-513, 2006. 〈lirmm-00130195〉
    • B. Lasbouygues, Robin Wilson, Nadine Azemard, Philippe Maurine. Timing Analysis in Presence of Supply Voltage and Temperature Variations. ISPD: International Symposium on Physical Design, Apr 2006, San Jose, CA, United States. pp.10-16, 2006. 〈lirmm-00102760〉
    • Robin Perrot, Philippe Maurine, Nadine Azemard. Exploration of the Area-Latency Tradeoff of Asynchronous CMOS data Dependent Adders. DCIS'06: 21th Conference on Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain, pp.CDROM, 2006. 〈lirmm-00117102〉
    • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Circuit Performance Optimization under Delay Constraints. DCIS'06: 21th Conference on Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain, pp.CDROM, 2006. 〈lirmm-00117119〉
    • V. Migairou, R. Wilson, S. Engels, Nadine Azemard, Philippe Maurine. Statistical Characterization of Library Timing Performance. PATMOS'06: Power and Timing Modeling, Optimization and Simulation - Integrated Circuit and System Design, Sep 2006, Montpellier (France), Springer, pp.468-476, 2006, LNCS. 〈lirmm-00093233〉
    • Alexis Landrault, Alexandre Verle, Philippe Maurine, Nadine Azemard. Synthèse Physique et Optimisation des Performances au Niveau Transistor. FTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.91-95, 2005. 〈lirmm-00106004〉
    • Robin Perrot, Nadine Azemard, Philippe Maurine. Additionneurs RCA Data Dependent Micropipelines. FTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.183-188, 2005. 〈lirmm-00106005〉
    • Robin Perrot, Nadine Azemard, Philippe Maurine. Ripple Carry Adder for Micropipeline Circuits. DCIS: Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal. 20th International Conference on Design of Circuits and Integrated Systems, pp.4d.3.1-4d.3.6, 2005. 〈lirmm-00106075〉
    • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Speed Indicators for Circuit Optimization. PATMOS'05: 15th International Workshop on Power and Timing ModelingOptimization and Simulation, Sep 2005, Leuven, Belgium, pp.618-628, 2005. 〈lirmm-00106076〉
    • Benoit Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Temperature Dependency in UDSM Process. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. 15th International Workshop on Power and Timing Modeling, Optimization and Simulation, LNCS (3728), pp.693-703, 2005, 〈10.1007/11556930_71〉. 〈lirmm-00106077〉
    • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard. Protocole d'Optimisation de Circuit CMOS Orienté Basse Puissance. FTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.17-22, 2005. 〈lirmm-00106002〉
    • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Optimization Protocol Based on Low Power Metrics. IWLS'05: 14th IEEE International Workshop on Logic Synthesis, Jun 2005, Lake Arrowhead Resort, CA (USA), pp.288-293, 2005. 〈lirmm-00106018〉
    • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Path Optimization Protocol Based on Speed Low Power Metrics. EUROCON'05: International Conference on "Computer as a Tool", Nov 2005, Montenegro, Belgrade (Serbie), pp.523-526, 2005. 〈lirmm-00106428〉
    • Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Circuit Optimization Based on Speed Indicators. ICECS'05: 12th IEEE International Conference on ElectronicsCircuits and Systems, Dec 2005, Gammarth, Tunisie, pp.167-170, 2005. 〈lirmm-00106439〉
    • Alexandre Verle, Xavier Michel, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Low Power Oriented CMOS Circuit Optimization Protocol. DATE'05: Design, Automation and Test in Europe, Mar 2005, Munich, Germany. pp.640-645, 2005. 〈lirmm-00106452〉
    • Alexandre Verle, Xavier Michel, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Low Power Oriented CMOS Circuit Optimization Protocol. DATE: Design, Automation and Test in Europe, Mar 2005, Munich, Germany. Design, Automation and Test in Europe, pp.640-645, 2005. 〈lirmm-01507287〉
    • Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Definition of P/N Width Ratio for CMOS Standard Cell Library. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. 19th International Conference on Design of Circuits and Integrated Systems, pp.769-773, 2004. 〈lirmm-00108933〉
    • Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Optimization Protocol Based on Performance Metric. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. 19th International Conference on Design of Circuits and Integrated Systems, pp.964-968, 2004. 〈lirmm-00108935〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. RC on-chip interconnect Performance revisited. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. 19th International Conference on Design of Circuits and Integrated Systems, pp.809-814, 2004. 〈lirmm-00108934〉
    • Alexis Landrault, Nadine Azemard, Philippe Maurine, Michel Robert, Daniel Auvergne. Automatic Layout Synthesis Based Performance Optimization. IWLS'04: 13th IEEE International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, pp.80-85, 2004. 〈lirmm-00108654〉
    • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Delay Bound Based CMOS Gate Sizing Technique. ISCAS'04: International Symposium on Circuits and Systems, May 2004, Vancouver (Canada), pp.189-192, 2004. 〈lirmm-00108856〉
    • Benoit Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Temperature Dependence in Low Power CMOS UDSM Process. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. Springer, 14th International Workshop on Power and Timing Modeling Optimization and Simulation, LNCS (3254), pp.111-118, 2004, 〈10.1007/978-3-540-30205-6_13〉. 〈lirmm-00108893〉
    • Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Performance Metric Based Optimization Protocol. PATMOS'04: 14th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2004, Santorini (Greece), Springer, pp.100-109, 2004, Lecture Notes in Computer Science. 〈lirmm-00108892〉
    • Alexis Landrault, Nadine Azemard, Philippe Maurine, Michel Robert, Daniel Auvergne. Design Optimization with Automated Cell Generation. PATMOS'04: 14th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2004, Santorini (Greece), Springer, pp.722-731, 2004, Lecture Notes in Computer Science. 〈lirmm-00108894〉
    • Benoit Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Physical Extension of the Logical Effort Model. PATMOS'04: 14th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2004, Santorini (Greece), Springer, pp.838-848, 2004, Lecture Notes in Computer Science. 〈lirmm-00108895〉
    • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. CMOS Gate Sizing under Delay Constraint. Springer. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. 12th International Workshop on Power And Timing Modeling, Optimization and Simulation, LNCS (2799), pp.60-69, 2003. 〈lirmm-00269566〉
    • Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Metric Definition for Circuit Speed Optimization. Springer. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, LNCS (2799), pp.451-460, 2003. 〈lirmm-00269568〉
    • Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Metric Definition for Circuit Speed Optimization. IWLS: International Workshop on Logic Synthesis, May 2003, Laguna Beach, CA, United States. 12th IEEE International Workshop on Logic Synthesis, 2003, 〈http://www.iwls.org/iwls2003/〉. 〈lirmm-00269689〉
    • Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Metric Definition for Circuit Speed Optimization. IWLS'03: IEEE 12th International Workshop on Logic & Synthesis, May 2003, pp.CD, 2003. 〈lirmm-00244020〉
    • Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Metric Definition for Circuit Speed Optimization. PAMOS'03: 13th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2003, Torino, Italy, pp.451-460, 2003. 〈lirmm-00244025〉
    • Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. CMOS Gate Sizing under Delay Constraint. PAMOS'03: 13th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2003, Torino, Italy, pp.60-69, 2003. 〈lirmm-00244021〉
    • Benoit Lasbouygues, J. Schindler, S. Engels, Philippe Maurine, Xavier Michel, et al.. Continuous Representation of the Performance of a CMOS Library. ESSCIRC'03: 29th European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal, pp.595-598, 2003. 〈lirmm-00239459〉
    • Benoit Lasbouygues, J. Schindler, Sylvain Engels, Philippe Maurine, Xavier Michel, et al.. Timing Performance Representation of a CMOS Standard Cell Library. DCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. 18th International Conference on Design of Circuits and Integrated Systems, pp.83-88, 2003. 〈lirmm-00239460〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Defining the Maximum Speed of CMOS Gate Library. DCIS: Design of Circuits and Integrated Systems, 2002, Santander, Spain. 17th International Conference on Design of Circuits and Integrated Systems, pp.81-86, 2002. 〈lirmm-00268431〉
    • Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Gate Sizing for Low Power Design. SoC Design Methodologies, 2002, Montpellier, France. Kluwer Academic Publishers, pp.301-312, 2002. 〈lirmm-00268519〉
    • Philippe Maurine, Xavier Michel, Nadine Azemard, Daniel Auvergne. Gate Speed Improvement at Minimal Power Dissipation. APPCAS'02: IEEE Asia-Pacific Conference on Circuits and Systems, Oct 2002, Denpasar, Bali, pp.278-282, 2002. 〈lirmm-00239453〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS'02: 12th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2002, Seville, Espagne, pp.247-257, 2002. 〈lirmm-00244012〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Defining the Maximum Speed of CMOS Gate Library. DCIS'02: XVII Design of Circuits and Integrated Systems Conference, Nov 2002, Santander, Espagne, pp.81-86, 2002. 〈lirmm-00239455〉
    • Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Metric Definition for Buffer Insertion. DCIS'02: XVII Design of Circuits and Integrated Systems Conference, Nov 2002, Santander, Espagne, pp.307-312, 2002. 〈lirmm-00239458〉
    • Nadine Azemard, Michel Aline, Daniel Auvergne. Delay Bound Determination for Timing Closure Satisfaction. ISCAS'01: IEEE International Symposium on Circuits and Systems, May 2001, Sydney, Australie, 5, pp.375- 378, 2001. 〈lirmm-00241322〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Perfornance Evaluation for Submicron CMOS Design. PhD Forum at DAC 2001 : Design Automation Conference, Jun 2001, Las Vegas, Nevada, USA, pp.N/A, 2001. 〈lirmm-00239441〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Technological Assignment for a Minimal Power Consumption. VLSI-SoC'01: 11th IFIP International Conference on Very Large Scale Integration - The Global System On Chip Design & CAD Conference, Dec 2001, Montpellier, France, pp.236-241, 2001. 〈lirmm-00239450〉
    • Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Timing Closure Management based on Delay Bound Determination. VLSI-SoC'01: 11th IFIP International Conference on Very Large Scale Integration - The Global System On Chip Design & CAD Conference, Dec 2001, Montpellier, France, pp.430-434, 2001. 〈lirmm-00239452〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Performance Indicators for Designing CMOS Logic. ICM'01: 13th International Conference on Microelectronic, Oct 2001, Rabat, Maroc, pp.125-129, 2001. 〈lirmm-00239446〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination. PATMOS'01: 11th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2001, Yverdon-Les-Bains, Switzerland, pp.5.3.1-5.3.10, 2001. 〈lirmm-00244010〉
    • Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Delay Bound Determination for Timing Closure on CMOS Circuits. IWLS'01: IEEE 10th International Workshop on Logic & Synthesis, Jun 2001, Granlibakken Conference Center, USA, pp.96-100, 2001. 〈lirmm-00244007〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Full Analyttical Model for delay Performance Estimation in Submicron CMOS. MIXDES'01: 8th Mixed Design of Integrated Circuits and Systems, Jun 2001, Zakopane, Pologne, pp.355-359, 2001. 〈lirmm-00239444〉
    • Philippe Maurine, Régis Poirier, Nadine Azemard, Daniel Auvergne. Switching Current Modeling in CMOS Inverter for Speed and Power Estimation. DCIS'01: XVI Design of Circuits and Integrated Systems Conference, Nov 2001, Porto, Portugal, pp.618-622, 2001. 〈lirmm-00239448〉
    • Nadine Azemard, Michel Aline, Daniel Auvergne. POPS: A tool for Delay/Power Performance/Optimization. ASIC-SoC'00: 13th IEEE International ASIC/SOC Conference, Sep 2000, Arlington, USA, pp.276-280, 2000. 〈lirmm-00239434〉
    • Michel Aline, Nadine Azemard, Daniel Auvergne. Upper and Lower bound Determination of delay on Critical Path. DCIS'00: XV Design of Circuits and Integrated Systems Conference,, Nov 2000, Montpellier, France, pp.543-547, 2000. 〈lirmm-00239437〉
    • Nadine Azemard, Michel Aline, Daniel Auvergne. Delay Bound Determination for Path Constraint Satisfaction. ISMA'00: International Symposium on Microelectronics and Assembly, MSO4 : Design, Modeling and Simulation, Nov 2000, Singapour, pp.122 - 129, 2000. 〈lirmm-00241266〉
    • Fernando Moraes, Michel Robert, Daniel Auvergne, Nadine Azemard. A Physical Synthesis Design Flow based on Virtual Components. DCIS'00: XV Design of Circuits and Integrated Systems Conference, Nov 2000, Montpellier, France, pp.740-745, 2000. 〈lirmm-00239439〉
    • Nadine Azemard, Michel Aline, Daniel Auvergne. Local Gate Resizing for Critical Path Optimization. DCIS'99: IX Design of Circuits and Integrated Systems Conference, Nov 1999, Palma de Majorque, Espagne, pp.195-200, 1999. 〈lirmm-00239429〉
    • Nadine Azemard, Michel Aline, Daniel Auvergne. Post Layout Management of Delay Power Constraints in Submicronic CMOS Implementation. IWLS'99 : IEEE International Workshop on Logic Synthesis, Jun 1999, Granlibakken Resort, Lake Tahoe, CA, USA, pp.198-201, 1999. 〈lirmm-00244002〉
    • Nadine Azemard, Michel Aline, Daniel Auvergne. Satisfaction of Delay/Power Constraints by Iterative Gate Sizing. PATMOS'99: 9th International Workshop on Power and Timing Modeling Optimization and Simulation, Oct 1999, Kos, Greece, pp.325-334, 1999. 〈lirmm-00244003〉
    • Séverine Cremoux, Michel Aline, Nadine Azemard, Daniel Auvergne. Delay-Power Performance Analysis. ICECS'99: 6th IEEE International Conference on Electronics, Circuits and Systems, Sep 1999, Pafos, Chypre, pp.1543-1546, 1999. 〈lirmm-00239424〉
    • Séverine Cremoux, Nadine Azemard, Daniel Auvergne. Path Resizing Based on Incremental Technique. ISCAS'98: IEEE International Symposium on Circuits and Systems, May 1998, Monterey, CA, USA, pp.71, 1998. 〈lirmm-00241190〉
    • Séverine Cremoux, Nadine Azemard, Daniel Auvergne. POPS: A New Tool for Path Evaluation. PATMOS'98: 8th International Workshop on Power and Timing Modeling Optimization and Simulation, Oct 1998, Lyngby, Denmark, pp.235-244, 1998. 〈lirmm-00241378〉
    • Séverine Cremoux, Nadine Azemard, Daniel Auvergne. Long and Short Path Sizing for Delay-Power Performance Management. IWLS'98: International Workshop on Logic Synthesis, Jun 1998, Lake Tahoe, CA, USA, pp.N/A, 1998. 〈lirmm-00241376〉
    • Séverine Cremoux, Nadine Azemard, Michel Aline, Daniel Auvergne. POPS: Performance Optimization by Path Selection. DCIS'98 : XIII Design of Circuits and Integrated Systems Conference, Nov 1998, Madrid, Spain, pp.10-15, 1998. 〈lirmm-00239421〉
    • Séverine Cremoux, Nadine Azemard, Michel Aline, Daniel Auvergne. A New Tool for Path Performance Optimization. International Workshop on IP Based Synthesis and System Design, Dec 1998, Grenoble, France, pp.175-179, 1998. 〈lirmm-00241408〉
    • Thierry Monnier, Séverine Cremoux, Nadine Azemard, Daniel Auvergne. A Path Sensitization Approach for Performance Optimization. ISIC'97: 7th International Symposium on IC Technology, Systems and Applications, Sep 1997, pp.94-97, 1997. 〈lirmm-00241160〉
    • Séverine Cremoux, Thierry Monnier, Nadine Azemard, Daniel Auvergne. Performance Otimization by Path Selection. IWLS 97: IEEE International Workshop on Logic Synthesis, May 1997, Tahoe City, CA, USA, pp.152-155, 1997. 〈lirmm-00241372〉
    • Séverine Cremoux, Nadine Azemard, Daniel Auvergne. Selective Gate Sizing for Delay/Power Performance Management. IWLAS'97: International Workshop on Logic and Architecture Synthesis, Dec 1997, Grenoble, France, pp.1-9, 1997. 〈lirmm-00241374〉
    • Séverine Cremoux, Jose Luis Guntzel, Nadine Azemard, Daniel Auvergne. Path Sensitization for Performance Optimization. MIXDES 97: 4 th Mixed Design of Integrated Circuits and Systems, Jun 1997, Poznan, Pologne, pp.195-200, 1997. 〈lirmm-00239409〉
    • Séverine Cremoux, Thierry Monnier, Jose Luis Guntzel, Nadine Azemard, Daniel Auvergne. A Path Selection Algorithm for Performance Optimization. IWLAS'96-IFIP: International Workshop on Logic and Architecture Synthesis, Dec 1996, Grenoble, France, pp.277-284, 1996. 〈lirmm-00241369〉
    • Sandra Turgis, Nadine Azemard, Daniel Auvergne. Design and Selection of Buffers for Minimum Power-Delay Product. ED&TC'96: European Design and Test Conference, Mar 1996, Paris, France, pp.224-228, 1996. 〈lirmm-00239400〉
    • Sandra Turgis, Nadine Azemard, Daniel Auvergne. Design and Sizing of Tapered Buffers for Minimum Power-Delay Product. PATMOS'95: Fifth International Workshop on Power and Timing Modelling, Optimization and Simulation, Oct 1995, Oldenburg, Allemagne, pp.79-90, 1995. 〈lirmm-00241366〉
    • Sandra Turgis, Nadine Azemard, Daniel Auvergne. Short-Circuit Power Dissipation calculation on CMOS Inverters using the Equivalent Short-Circuit Capacitance Concept. PATMOS'95: Fifth International Workshop on Power and Timing Modelling, Optimization and Simulation, Oct 1995, Oldenburg, Allemagne, pp.213-224, 1995. 〈lirmm-00241367〉
    • Sandra Turgis, Nadine Azemard, Daniel Auvergne. Explicit Evaluation of Short Circuit Power Dissipation for CMOS Logic Structures. ISLPD'95: International Symposium on Low Power Design, Apr 1995, Dana Point Resort, CA, USA, pp.129-134, 1995. 〈lirmm-00241153〉
    • Myrian Mellah, Nadine Azemard, Daniel Auvergne. General Determination of Buffer Insertion Limits. Fourth International Workshop on Design Automation: 4th Russian Workshop, Jun 1994, Moscou, Russie, pp.21-23, 1994. 〈lirmm-00241361〉
    • Myrian Mellah, Nadine Azemard, Daniel Auvergne. Standard Cell Performance Modelling. PATMOS'94: Fourth International Workshop on Power and Timing Modelling, Optimization and Simulation, Oct 1994, Barcelone, Espagne, pp.158-167, 1994. 〈lirmm-00241364〉
    • Fernando Moraes, Nadine Azemard, Michel Robert, Daniel Auvergne. Flexible Macrocell layout Generator. 4th ACM/SIGDA Physical Design Workshop, Layout Synthesis for the New Generation of VLSI ASIC Technologies, Apr 1993, UCLA Conference Center, CA, USA, pp.105-116, 1993. 〈lirmm-00241344〉
    • Fernando Moraes, Nadine Azemard, Michel Robert, Daniel Auvergne. Tool Box for Performance Driven Macrocell layout Synthesis. 4th EUROCHIP Workshop on VLSI Design Training, Sep 1993, Toledo, Spain, pp.56-61, 1993. 〈lirmm-00241348〉
    • Nadine Azemard, Sylvie Amat, Myrian Mellah, Daniel Auvergne. A Real Characterization based Buffer Selection Algorithm. PATMOS'93: Third International Workshop on Power and Timing Modelling and Optimization, Oct 1993, La Grande Motte, France, pp.1-9, 1993. 〈lirmm-00241350〉
    • Daniel Auvergne, Sylvie Amat, Myrian Mellah, Nadine Azemard, Michel Robert. Evaluation of Speed up Strategy from Gate Performance Modelling. IFIP Workshop on Logic and Architecture Synthesis, Dec 1993, Grenoble, France, pp.193-208, 1993. 〈lirmm-00241358〉
    • Nadine Azemard, Denis Deschacht, Michel Robert, Daniel Auvergne. Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor Sising. PATMOS'92: Second International Workshop on Power and Timing Modelling and Optimization, Sep 1992, Paris, France. pp.102-108, 1992. 〈lirmm-00241327〉
    • Nadine Azemard, Vincent Bonzom, Sylvie Amat, Daniel Auvergne. Optimization Technique for Performance driven Cell Generator. EUROASIC'92, Jun 1992, CNIT La Défense, Paris, France, pp.152-155, 1992. 〈lirmm-00239390〉
    • Nadine Azemard, Vincent Bonzom, Daniel Auvergne. P.SIZE : A Sizing aid for Optimized Designs. EURODAC'92: European Design Automation Conference, Sep 1992, Hamburg, Germany, pp.160-166, 1992. 〈lirmm-00239396〉
    • Michel Robert, Joel Trauchessec, Guy Cathébras, Vincent Bonzom, Nadine Azemard, et al.. Evaluation of VLSI Layout Implementation for Efficiency. EURO-ASIC'91: The European Conference on Design Automation with The European Event in ASIC Design, May 1991, Paris, France. pp.362-365, 1991. 〈lirmm-00239384〉
    • Daniel Auvergne, Nadine Azemard, Denis Deschacht, Michel Robert. An Accurate and Efficient Delay Time Modelling and its Application to CMOS Data Path Evaluation and Transistor Sizing. 13th IMACS: World Congress on Computation and Applied Mathematics, Jul 1991, Dublin, Ireland. pp.1661-1663, 1991. 〈lirmm-00239387〉
    • Daniel Auvergne, Nadine Azemard, Vincent Bonzom, Denis Deschacht, Michel Robert. Formal Sizing Rules of CMOS Circuits. EDAC'91: European Conference on Design Automation, Feb 1991, Amsterdam, Netherlands. pp.96-100, 1991. 〈lirmm-00239374〉
    • Nadine Azemard, Vincent Bonzom. CMOS Circuit Speed Optimization based on Closed form Equation. International Students Microelectronic Conference, May 1990, Zagreb, Yugoslavia, pp.29-32, 1990. 〈lirmm-00239369〉

    Poster1 document

    • Nadine Azemard, Zeqin Wu, Philippe Maurine, Gille Ducharme. Statistical Timing Characterization. S0C'12: International Symposium on System-on-Chip, Oct 2012, Tmapere, Finland. pp.N/A, 2012. 〈lirmm-00762107〉

    Ouvrage (y compris édition critique et traduction)6 documents

    • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme. Delay-Correlation-Aware SSTA Based on Conditional Moments. Z. Wu and P. Maurine and N. Azemard and G. Ducharme. Microelectronic Journal, pp.263-276, 2012. 〈lirmm-00762085〉
    • Nadine Azemard. Spécial Issue in Journal of Low Power Electronics. 4(3), pp.696-724, 2012. 〈lirmm-00546355〉
    • Nadine Azemard, Lars Svensson. Special Issue: Power and Timing Modeling, Optimization and Simulation. N. Azémard and L. Svensson. IOS Press, Journal of Embedded Computing (JEC), 3(3), pp.155-254, 2009. 〈lirmm-00371166〉
    • Nadine Azemard, Philippe Maurine, Johan Vounckx. Power and Timing Modeling, Optimization and Simulation - Integration the VLSI Journal (Special Issue). Elsevier, 41 (2), pp.160, 2008. 〈lirmm-00189961〉
    • Nadine Azemard, Lars Svensson. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007. Springer, pp.583, 2007, LNCS, 978-3-540-74441-2. 〈lirmm-00175210〉
    • Nadine Azemard, Philippe Maurine, Johan Vounckx. PATMOS'06: Power and Timing Modeling, Optimization and Simulation - Integrated Circuit and System Design. J. Vounckx, N. Azémard, P. Maurine. Springer, pp.677, 2006, LNCS, 3-540-39094-4. 〈lirmm-00135046〉

    Chapitre d'ouvrage5 documents

    • Pascal Benoit, Gilles Sassatelli, Philippe Maurine, Lionel Torres, Nadine Azemard, et al.. Towards Autonomous Scalable Integrated Systems. Design Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. 〈10.1007/978-94-007-1125-9_4〉. 〈lirmm-01399454〉
    • Daniel Auvergne, Philippe Maurine, Nadine Azemard. Modeling for Designing in Deep Sub-Micron Technologies. PIGUET C. Low-Power Electronics Design, CPR Press, 2004, 0-8493-1941-2. 〈lirmm-00109162〉
    • Michel Aline, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Feasible delay Bound Definition. SOC Design Methodologies, Kluwer Academic Publishers, pp.325-335, 2002. 〈lirmm-00239363〉
    • Philippe Maurine, Nadine Azemard, Daniel Auvergne. Gate Sizing for Low Power Design. SOC Design Methodologies, Kluwer Academic Publishers, pp.301-312, 2002. 〈lirmm-00239359〉
    • Séverine Cremoux, Nadine Azemard, Daniel Auvergne. Path Selection Based on Incremental Technique. Mixed Design of Integrated Circuits and Systems, Kluwer Academic Publishers, pp.137-142, 1998. 〈lirmm-00239354〉

    Direction d'ouvrage, Proceedings, Dossier5 documents

    • Ricardo Da Luz Reis, Nadine Azemard. Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1–4, 2015. Nadine Azemard; Ricardo Reis. 2015, Salvador, Bahia, Brazil. 12 (1), pp.56-57, 2016, Special Issue dans Journal of Low Power Electronics, 〈10.1166/jolpe.2016.1425〉. 〈lirmm-01398788〉
    • Nadine Azemard, Eugeni Garcia-Moreno. Selected Articles from the 5th European Workshop on CMOS Variability, Palma (Mallorca), Spain, September 29–October 1, 2014. Nadine Azemard; Garcia-Moreno Eugeni. 2014, Mallorca, Spain. 11 (2), pp.249-249, 2015, Special Issue dans Journal of Low Power Electronics, 〈10.1166/jolpe.2015.1368〉. 〈lirmm-01168609〉
    • Nadine Azemard, Jörg Henkel. Selected Peer-Reviewed Articles from the 4th European Workshop on CMOS Variability, Karlsruhe, Germany, September 9–11, 2013: Selected Peer-Reviewed Articles from the 4th European Workshop on CMOS Variability, Karlsruhe, Germany, September 9–11, 2013. Nadine Azemard; Jörg Henkel. Sep 2013, Karlsruhe, Germany. 10 (1), pp.116-117, 2014, Journal of Low Power Electronics - JOLPE, 〈10.1166/jolpe.2014.1310〉. 〈lirmm-01168100〉
    • Nadine Azemard, Gilles Jacquemod. Selected Articles from the VARI 2012 Workshop. Nadine Azemard; Gilles Jacquemod. VARI, 2012, France. 8 (5), American Scientific Publishers, pp.696-696, 2012, Special Issue in Journal of Low Power Electronics, 〈10.1166/jolpe.2012.1227〉. 〈lirmm-01398764〉
    • Nadine Azemard, Marc Belleville. Selected Articles from the VARI 2011 Workshop. Nadine Azemard; Marc Belleville. VARI, 2011, France. 8 (1), American Scientific Publishers, pp.82-82, 2012, Special Issue in Journal of Low Power Electronics, 〈10.1166/jolpe.2012.1178〉. 〈lirmm-00762096〉

    Autre publication11 documents

    • Patrick Girard, Nadine Azemard. A Central Market Place for Dissemination of Low-Power Microelectronics Design Knowledge. 12701. 2005. 〈lirmm-00106615〉
    • Nadine Azemard, Patrick Girard. A central Market place for Dissemination of low Power Microelectronics design knowledge. 2005. 〈lirmm-00259919〉
    • Patrick Girard, Nadine Azemard, Daniel Auvergne. A Central Market Place for Dissemination of Low Power Microelectronics Design Knowledge. 11484. 2004. 〈lirmm-00109185〉
    • Nadine Azemard, Patrick Girard. A Central Market Place for Dissemination of Low Power Microelectronics Design Knowledge. 11783. 2004. 〈lirmm-00109188〉
    • Nadine Azemard, Patrick Girard, Daniel Auvergne. Contrat CEE MARLOW : Premier Rapport d'Avancement du Projet (PPR1). 9912. 2003, pp.P nd. 〈lirmm-00269637〉
    • Patrick Girard, Nadine Azemard, Daniel Auvergne. Contrat CEE MARLOW : Premier Rapport de Management du Projet (PMR1). 9913. 2003, pp.P nd. 〈lirmm-00269638〉
    • Nadine Azemard, Patrick Girard, Daniel Auvergne. A Central Market Place for Dissemination of Low Power Microelectronics Design Knowledge. 2003. 〈lirmm-00259922〉
    • Patrick Girard, Nadine Azemard, Daniel Auvergne. A Central Market Place for Dissemination of Low Power Microelectronics Design Knowledge. 2003. 〈lirmm-00259925〉
    • Daniel Auvergne, Nadine Azemard, J. Carrabina, Philippe Coll, A. Guyot, et al.. Library Free Integrated Circuits for Submicron Technologies. 8145. 2002. 〈lirmm-00268592〉
    • Daniel Auvergne, Nadine Azemard, Jordi Carrabina, Philippe Coll, Alain Guyot, et al.. Library free integrated circuit design for submicron technologies. 2002. 〈lirmm-00259937〉
    • Daniel Auvergne, Nadine Azemard, Jordi Carrabina, Philippe Coll, Alain Guyot, et al.. Library Free Integrated Circuit Design for Submicron Technologies. 2000. 〈lirmm-00259939〉