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142 résultats
Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach for LTE eNodeBSpringer-Verlag London, pp.224, 2012, Lecture Notes in Electrical Engineering, 978-1-4471-4209-6. ⟨10.1007/978-1-4471-4210-2⟩
Ouvrages
hal-00739957v1
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Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing TechnologiesJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2016
Article dans une revue
hal-01415970v1
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Automatic CNN Model Partitioning for GPU/FPGA-based Embedded Heterogeneous Accelerators using Geometric ProgrammingJournal of Signal Processing Systems, 2023, 95, pp.1203-1218. ⟨10.1007/s11265-023-01898-0⟩
Article dans une revue
hal-04289176v1
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Algorithmic-level Approximate Computing Applied to Energy Efficient HEVC DecodingIEEE Transactions on Emerging Topics in Computing, 2019, 7 (1), pp.5-17. ⟨10.1109/TETC.2016.2593644⟩
Article dans une revue
hal-01354638v1
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Optimization of automatically generated multi-core code for the LTE RACH-PD algorithmDASIP 2008, Nov 2008, Bruxelles, Belgium
Communication dans un congrès
hal-00336477v1
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A model of architecture for estimating GPU processing performance and powerDesign Automation for Embedded Systems, 2021, 25 (1), pp.43-63. ⟨10.1007/s10617-020-09244-4⟩
Article dans une revue
hal-03156001v1
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Scalable HEVC Decoder for Mobile Devices: Trade-offs between Energy Consumption and QualityConference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2016, Rennes, France
Communication dans un congrès
hal-01415938v1
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On predicting the HEVC intra quad-tree partitioning with tunable energy and rate-distortionJournal of Real-Time Image Processing, 2019, 16 (1), pp.161-174. ⟨10.1007/s11554-018-0809-5⟩
Article dans une revue
hal-01929171v1
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Models of Architecture[Research Report] PREESM/2015-12TR01, 2015, IETR/INSA Rennes; Scuola Superiore Sant’Anna, Pisa; Institut Pascal, Clermont Ferrand; University of Maryland, College Park; Tampere University of Technology, Tampere. 2015
Rapport
hal-01244470v1
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Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow GraphsEmbedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2019, Pythagorion, Samos Island, Greece. pp.269-280, ⟨10.1007/978-3-030-27562-4_19⟩
Communication dans un congrès
hal-02267487v2
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Accelerating CNN inference on FPGAs: A Survey2018
Pré-publication, Document de travail
hal-01695375v2
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Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC14 th IFAC INTERNATIONAL CONFERENCE on PROGRAMMABLE DEVICES and EMBEDDED SYSTEMS (PDeS), Oct 2016, Brno, Czech Republic
Communication dans un congrès
hal-01415965v1
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M14965: Implementing SVC from RVC AVC: description of the specific SVC FUs2007
Autre publication scientifique
hal-00696462v1
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M14457: A scheme for implementing MPEG-4 SP codec in the RVC framework2007
Autre publication scientifique
hal-00696464v1
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Scratchy : A Class of Adaptable Architectures with Software-Managed Communication for Edge Streaming ApplicationsDASIP 2024: Workshop on Design and Architectures for Signal and Image Processing, Jan 2024, Munich (Allemagne), Germany
Communication dans un congrès
hal-04509310v1
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Models, Methods and Tools for Bridging the Design Productivity Gap of Embedded Signal Processing SystemsSignal and Image processing. Université Clermont Auvergne, 2017
HDR
tel-01610096v1
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Models of Architecture for DSP SystemsSpringer. Handbook of Signal Processing Systems, Third Edition, In press
Chapitre d'ouvrage
hal-01660620v1
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IA évolutionniste pour la détection de comportements déviants dans les SI[Rapport de recherche] SILICOM; INSA RENNES; IETR/INSA Rennes. 2021
Rapport
hal-03374007v1
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Preserving data integrity of encoded medical images: the LAR compression frameworkAdvances in Reasoning-Based Image Processing Intelligent Systems, Springer, pp.1-35, 2012
Chapitre d'ouvrage
hal-00658130v1
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Why is FPGA-GPU Heterogeneity the Best Option for Embedded Deep Neural Networks?2021
Pré-publication, Document de travail
hal-03135114v1
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Convex Energy Optimization of Streaming Applications for MPSoCs44th IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), May 2019, Brighton, United Kingdom
Communication dans un congrès
hal-02302603v1
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Embedded Computer Systems: Architectures, Modeling, and Simulation: 19th International Conference, SAMOS 20192019
Ouvrages
hal-02491737v1
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ELECTRO-MAGNETIC SIDE-CHANNEL ATTACK THROUGH LEARNED DENOISING AND CLASSIFICATIONICASSP 2020-IEEE International Conference on Acoustics, Speech, and Signal Processing, May 2020, Barcelona, Spain. ⟨10.1109/ICASSP40776.2020.9053913⟩
Communication dans un congrès
hal-02477654v1
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Attacking at non-harmonic frequencies in screaming-channel attacks22nd Smart Card Research and Advanced Application Conference (CARDIS 2023), Nov 2023, Amsterdam, Netherlands. pp.1--20
Communication dans un congrès
hal-04309083v2
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Software HEVC video decoder: towards an energy saving for mobile applicationsMultimedia Tools and Applications, 2020, 79 (37-38), pp.26861-26884. ⟨10.1007/s11042-020-09025-y⟩
Article dans une revue
hal-02851418v1
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Models of Architecture: Application to ESL Model-Based Energy Consumption Estimation[Research Report] IETR/INSA Rennes; Scuola Superiore Sant’Anna, Pisa; Institut Pascal; University of Maryland, College Park; Tampere University of Technology, Tampere. 2017
Rapport
hal-01464856v1
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DAMHSE Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototypingMicroprocessors and Microsystems: Embedded Hardware Design , 2019, 71, pp.102882. ⟨10.1016/j.micpro.2019.102882⟩
Article dans une revue
hal-02309549v1
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Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph12th International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS XII), Jul 2012, Agios Konstantinos, Greece. pp.160
Communication dans un congrès
hal-00721335v1
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Ultra-Fast Machine Learning Inference through C Code Generation for Tangled Program Graphs2022 IEEE Workshop on Signal Processing Systems (SiPS), Nov 2022, Rennes, France. pp.1-6, ⟨10.1109/SiPS55645.2022.9919237⟩
Communication dans un congrès
hal-03845227v1
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Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable AcceleratorsIEEE Embedded Systems Letters, 2019, 11 (3), pp.69-72. ⟨10.1109/LES.2018.2882989⟩
Article dans une revue
hal-02062002v1
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