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Michel Robert
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Documents
Identifiants chercheurs
michel-robert-
0000-0002-5075-2898
Présentation
Michel ROBERT (PhD:1987) is Professor at the University of Montpellier (France), where he’s teaching microelectronics in the engineering program. His present research interests at the Montpellier Laboratory of Informatics, Robotics, and Micro-electronics ([LIRMM](https://www.lirmm.fr/)) are design and modelisation of system on chip architectures. He is author or co-author of more than 300 publications in the field of CMOS integrated circuits design. He has supervised around forty doctoral thesis. He chaired the IFIP WG 10.5 (International Federation for Information Processing) from 2007 to 2011.
He served as director of the doctoral school, of the LIRMM research laboratory, then of the laboratory of excellence for digital solutions and modeling for the environment and the living, before becoming president of the University of Montpellier (2012-2015). He has held various national responsibilities in monitoring and evaluation in higher education and research. He was Director of the Institutional Evaluation Department of the High Council for the Evaluation of Research and Higher Education (Hcéres) from 2016 to 2021.
Publications
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Post-Layout Timing Simulation of CMOS CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993, 12 (8), pp.1170-1177. ⟨10.1109/43.238609⟩
Article dans une revue
lirmm-00239206v1
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A Performance Driven Layout Synthesis Approach for Digital CMOS Cell ImplementationIntegration, the VLSI Journal, 1993
Article dans une revue
lirmm-00239254v1
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Input Waveform Slope Effects in CMOS DelaysIEEE Journal of Solid-State Circuits, 1990, 25 (6), pp.1588-1590. ⟨10.1109/4.62196⟩
Article dans une revue
lirmm-00239201v1
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Evaluation Dynamique et Optimisation des Structures CMOS et VLSIRevue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, 1989, 8 (6), pp.593-607
Article dans une revue
lirmm-00239199v1
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Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor SisingPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 1992, Paris, France. pp.102-108
Communication dans un congrès
lirmm-00241327v1
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An Accurate and Efficient Delay Time Modelling and its Application to CMOS Data Path Evaluation and Transistor SizingWorld Congress on Computation and Applied Mathematics, IMACS: International Association for Mathematics and Computers in Simulation, Jul 1991, Dublin, Ireland. pp.1661-1663
Communication dans un congrès
lirmm-00239387v1
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Formal Sizing Rules of CMOS CircuitsEDAC 1991 - European Conference on Design Automation, Feb 1991, Amsterdam, Netherlands. pp.96-100, ⟨10.1109/EDAC.1991.206368⟩
Communication dans un congrès
lirmm-00239374v1
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Evaluation of VLSI Layout Implementation for EfficiencyEURO-ASIC 1991 - European Conference on Design Automation with European Event in ASIC Design, May 1991, Paris, France. pp.362-365, ⟨10.1109/EUASIC.1991.212836⟩
Communication dans un congrès
lirmm-00239384v1
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