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Michel Robert

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Identifiants chercheurs

Présentation

Michel ROBERT (PhD:1987) is Professor at the University of Montpellier (France), where he’s teaching microelectronics in the engineering program. His present research interests at the Montpellier Laboratory of Informatics, Robotics, and Micro-electronics ([LIRMM](https://www.lirmm.fr/)) are design and modelisation of system on chip architectures. He is author or co-author of more than 300 publications in the field of CMOS integrated circuits design. He has supervised around forty doctoral thesis. He chaired the IFIP WG 10.5 (International Federation for Information Processing) from 2007 to 2011. He served as director of the doctoral school, of the LIRMM research laboratory, then of the laboratory of excellence for digital solutions and modeling for the environment and the living, before becoming president of the University of Montpellier (2012-2015). He has held various national responsibilities in monitoring and evaluation in higher education and research. He was Director of the Institutional Evaluation Department of the High Council for the Evaluation of Research and Higher Education (Hcéres) from 2016 to 2021.

Publications

philippe-maurine
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Differential Power Analysis Enhancement with Statistical Preprocessing

Victor Lomné , Amine Dehbaoui , Philippe Maurine , Lionel Torres , Michel Robert
DATE: Design, Automation and Test in Europe, 2010, Dresden, Germany. pp.1301-1304, ⟨10.1109/DATE.2010.5457007⟩
Communication dans un congrès lirmm-00548738v1
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Spatial EM Jamming: a Countermeasure Against EM Analysis ?

François Poucheret , Lyonel Barthe , Pascal Benoit , Lionel Torres , Philippe Maurine
VLSI-SoC'10: 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, Madrid, Spain. pp.105-110
Communication dans un congrès lirmm-00544358v1
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Incoherence Analysis and its Application to Time Domain EM Analysis of Secure Circuits

Philippe Maurine , Amine Dehbaoui , Thomas Ordas , Victor Lomné , Lionel Torres
APEMC 2010 - Asia-Pacific Symposium on Electromagnetic Compatibility, Apr 2010, Beijing, China. pp.1039-1042, ⟨10.1109/APEMC.2010.5475481⟩
Communication dans un congrès lirmm-00607894v1

On-Chip Timing Slack Monitoring

Bettina Rebaud , Marc Belleville , Edith Beigné , Michel Robert , Philippe Maurine
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2009, Florianopolis, Brazil. pp.89-94, ⟨10.1109/VLSISOC.2009.6041336⟩
Communication dans un congrès lirmm-00429350v1

Evaluation on FPGA of Triple Rail Logic Robustness Against DPA and DEMA

Victor Lomné , Philippe Maurine , Lionel Torres , Michel Robert , Rafael Soares
DATE: Design, Automation and Test in Europe, 2009, Nice, France. pp.634-639, ⟨10.1109/DATE.2009.5090744⟩
Communication dans un congrès lirmm-00372847v1
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Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variations

Bettina Rebaud , Marc Belleville , Edith Beigné , Michel Robert , Philippe Maurine
FTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Suisse
Communication dans un congrès lirmm-00404810v1
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Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of Variabilities

Bettina Rebaud , Marc Belleville , Edith Beigné , Christian Bernard , Michel Robert
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.266-275, ⟨10.1007/978-3-642-11802-9_31⟩
Communication dans un congrès lirmm-00433462v1
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Enhancing Electromagnetic Attacks using Spectral Coherence based Cartography

Amine Dehbaoui , Victor Lomné , Philippe Maurine , Lionel Torres , Michel Robert
VLSI-SoC 2009 - 17th IFIP International Conference on Very Large Scale Integration, Oct 2009, Florianopolis, Brazil. pp.11-16, ⟨10.1109/VLSISOC.2009.6041323⟩
Communication dans un congrès lirmm-00429342v1

An Innovative Timing Slack Monitor for Variation Tolerant Circuits

Bettina Rebaud , Marc Belleville , Edith Beigné , Michel Robert , Philippe Maurine
ICICDT: International Conference on IC Design & Technology, May 2009, Austin, TX, United States. pp.215-218, ⟨10.1109/ICICDT.2009.5166299⟩
Communication dans un congrès lirmm-00371174v1

Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier

Bettina Rebaud , Marc Belleville , Christian Bernard , Zeqin Wu , Michel Robert
ISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩
Communication dans un congrès lirmm-00280809v1

Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects

Michael Yap San Min , Philippe Maurine , Magali Bastian Hage-Hassan , Michel Robert
ISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, pp.310-315
Communication dans un congrès lirmm-00280716v1
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Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétique

Bettina Rebaud , Zeqin Wu , Marc Belleville , Christian Bernard , Michel Robert
JNRDM 2008 - 11e Journées Nationales du Réseau Doctoral de Microélectronique, May 2008, Bordeaux, France
Communication dans un congrès lirmm-00281175v2

Prototyping Secure Triple Track Logic (STTL) Robustness Against DPA & DEMA on FPGA

Victor Lomné , Rafael A. Soares , Thomas Ordas , Philippe Maurine , Lionel Torres
CryptArchi: Cryptographic Architectures, Jun 2008, Tregastel, France
Communication dans un congrès lirmm-00373539v1
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Evaluating the Robustness of Secure Triple Track Logic Through Prototyping

Rafael A. Soares , Ney Calazans , Victor Lomné , Philippe Maurine , Lionel Torres
SBCCI'08: Symposium on Integrated Circuits and Systems Design, Sep 2008, Gramado, Brazil, France. pp.193-198, ⟨10.1145/1404371.1404425⟩
Communication dans un congrès lirmm-00373516v1
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A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM

Michael Yap San Min , Philippe Maurine , Magali Bastian Hage-Hassan , Michel Robert
DELTA 2008 - 4th IEEE International Symposium on Electronic Design, Test and Applications, Jan 2008, Hong Kong, China. pp.107-110, ⟨10.1109/DELTA.2008.72⟩
Communication dans un congrès lirmm-00243966v1
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Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numérique

Bettina Rebaud , Marc Belleville , Christian Bernard , Zeqin Wu , Michel Robert
FTFC: Faible Tension - Faible Consommation, May 2008, Louvain-La-Neuve, Belgique
Communication dans un congrès lirmm-00283731v1
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Triple Rail Logic Robustness against DPA

Victor Lomné , Thomas Ordas , Philippe Maurine , Lionel Torres , Michel Robert
ReConFig 2008 - International Conference on Reconfigurable Computing and FPGAs, Dec 2008, Cancun, Mexico. pp.415-420, ⟨10.1109/ReConFig.2008.75⟩
Communication dans un congrès lirmm-00350573v1

Variabilité de Process et Performances des Mémoires SRAM Embarquées

Michael Yap San Min , Philippe Maurine , Magali Bastian Hage-Hassan , Michel Robert
FTFC'07: 6èmes Journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France, pp.7-11
Communication dans un congrès lirmm-00178319v1

Improvement of Dual Rail Logic as a Countermeasure Against DPA

Hanitriniaina Razafindraibe , Michel Robert , Philippe Maurine
VLSI-SoC 2007 - IFIP International Conference on Very Large Scale Integration, Oct 2007, Atlanta, GA, United States. pp.270-275, ⟨10.1109/VLSISOC.2007.4402510⟩
Communication dans un congrès lirmm-00186174v1
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Méthodologie d'estimation de l'influence de la variabilité sur un opérateur numérique

Bettina Rebaud , Marc Belleville , Christian Bernard , Michel Robert , Philippe Maurine
FTFC 2007 - 6e journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France
Communication dans un congrès lirmm-00204621v1

Process Variabilities and Performances in a 90nm embedded SRAM

Michael Yap San Min , Philippe Maurine , Magali Bastian Hage-Hassan , Michel Robert
IEEE International Integrated Reliability Workshop, Oct 2007, pp.050-055
Communication dans un congrès lirmm-00198373v1
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Process Variability Considerations in the Design of an eSRAM

Michael Yap San Min , Philippe Maurine , Michel Robert , Magali Bastian Hage-Hassan
MTDT 2007 - IEEE International Workshop on Memory Technology, Design and Testing, Dec 2007, Taipei, Taiwan. pp.23-26, ⟨10.1109/MTDT.2007.4547609⟩
Communication dans un congrès lirmm-00275258v1
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Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA

Alin Razafindraibe , Michel Robert , Philippe Maurine
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.340-351, ⟨10.1007/978-3-540-74442-9_33⟩
Communication dans un congrès lirmm-00175100v1
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Security Evaluation of Dual Rail Logic Against DPA Attacks

Hanitriniaina Razafindraibe , Philippe Maurine , Michel Robert , Marc Renaudin
VLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration, Oct 2006, Nice, France. pp.181-186, ⟨10.1109/VLSISOC.2006.313230⟩
Communication dans un congrès lirmm-00109692v1

Design of Compact Dual Rail Asynchronous Primitives

Alin Razafindraibe , Michel Robert , Philippe Maurine
DCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, 2005, Lisbonne, Portugal
Communication dans un congrès lirmm-00106434v1
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A Method to Design Compact Dual-rail Asynchronous Primitives

Alin Razafindraibe , Michel Robert , Marc Renaudin , Philippe Maurine
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.571-580, ⟨10.1007/11556930_58⟩
Communication dans un congrès hal-00105846v1

Asynchronous Dual rail Cells to Secure Cryptosystem Against Side Channel Attacks

Alin Razafindraibe , Michel Robert , Marc Renaudin , Philippe Maurine
SAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia-Antipolis
Communication dans un congrès lirmm-00106539v1

La Technologie Asynchrone QDI pour la Sécurité des Cryptosystèmes

Alin Razafindraibe , Philippe Maurine , Michel Robert
JNRDM 2005 - 8e Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France. pp.461-463
Communication dans un congrès lirmm-00106530v1

Méthode de Conception de Primitives Asynchrones Double Rail

Alin Razafindraibe , Michel Robert , Philippe Maurine
FTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.23-27
Communication dans un congrès lirmm-00106003v1

Automatic Layout Synthesis Based Performance Optimization

Alexis Landrault , Nadine Azemard , Philippe Maurine , Michel Robert , Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85
Communication dans un congrès lirmm-00108654v1

Conception et Modélisation de Briques Elémentaires CMOS

Guy Cathébras , S. Dussausay , Michel Robert , Philippe Maurine
CNFM'04 : 8ème Journées Pédagogiques du Comité National de Formation en Microélectronique, 2004, Saint-Malo, France. pp.35-37
Communication dans un congrès lirmm-00108672v1
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Design Optimization with Automated Cell Generation

Alexis Landrault , Nadine Azemard , Philippe Maurine , Michel Robert , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.722-731, ⟨10.1007/978-3-540-30205-6_74⟩
Communication dans un congrès lirmm-00108894v1

Secured Structures for Secured Asynchronous QDI Circuits

Alin Razafindraibe , Michel Robert , Bertrand Folco , Philippe Maurine , Ghislain Fraidy Bouesse
DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France
Communication dans un congrès hal-01393250v1
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Towards Autonomous Scalable Integrated Systems

Pascal Benoit , Gilles Sassatelli , Philippe Maurine , Lionel Torres , Nadine Azemard
Design Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. ⟨10.1007/978-94-007-1125-9_4⟩
Chapitre d'ouvrage lirmm-01399454v1
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Side Channel Attacks

Victor Lomné , Amine Dehbaoui , Philippe Maurine , Michel Robert , Lionel Torres
Security Trends for FPGAS
From Secured to Secure Reconfigurable Systems
, Springer, pp.47-72, 2011, 978-94-007-1337-6. ⟨10.1007/978-94-007-1338-3_3⟩
Chapitre d'ouvrage lirmm-00809329v1

Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks

Hanitriniaina Razafindraibe , Michel Robert , Philippe Maurine
Nadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.634-644, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. ⟨10.1007/11847083_44⟩
Chapitre d'ouvrage lirmm-00109844v1