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    26

    Publications of Michel Renovell


    Jean-Marc Galliere   

    Journal articles9 documents

    • Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell. Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies. Journal of Electronic Testing, Springer Verlag, 2019, 35 (1), pp.59-75. ⟨10.1007/s10836-019-05776-1⟩. ⟨lirmm-02075690⟩
    • Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell. Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. Journal of Electronic Testing, Springer Verlag, 2017, 33 (4), pp.515-527. ⟨10.1007/s10836-017-5674-9⟩. ⟨hal-01709587⟩
    • Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell. Influence of Body-Biasing, Supply Voltage, and Temperature on the Detection of Resistive Short Defects in FDSOI Technology. IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers, 2017, 16 (3), pp.417-430. ⟨10.1109/TNANO.2017.2664895⟩. ⟨hal-01709588⟩
    • Jean-Marc Galliere, Florence Azaïs, Mariane Comte, Michel Renovell. Testing for Gate Oxide Short Defects using the Detectability Interval Paradigm. Information Technology, Oldenbourg Verlag, 2014, 56 (4), pp.173-181. ⟨10.1515/itit-2013-1040⟩. ⟨hal-01167054⟩
    • Jean-Marc Galliere, Michel Renovell, Florence Azaïs, Yves Bertrand. Delay Testing Viability of Gate Oxide Short Defect. Journal of Computer Science and Technology, Iberoamerican Science & Technology Education Consortium, 2005, 20 (2), pp.195-200. ⟨10.1007/s11390-005-0195-x⟩. ⟨lirmm-00105323⟩
    • Jean-Marc Galliere, Michel Renovell, Florence Azaïs, Yves Bertrand. Viability of a Delay Testing of Gate Oxide Short Transistors. Journal of Computer Science and Technology, Iberoamerican Science & Technology Education Consortium, 2005, 20 (2), pp.6. ⟨lirmm-00370370⟩
    • Rachid Bouchakour, Jean-Michel Portal, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand, et al.. A Compact DC Model of Gate Oxide Short Defect. Microelectronic Engineering, Elsevier, 2004, 72 (1-4), pp.140-148. ⟨10.1016/j.mee.2003.12.051⟩. ⟨lirmm-00108564⟩
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Modeling the Random Parameter Effects in a Non-Split Model of Gate Oxide Short. Journal of Electronic Testing, Springer Verlag, 2003, 19 (4), pp. 377-386. ⟨lirmm-00269754⟩
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. Journal of Electronic Testing, Springer Verlag, 2003, 19 (4), pp.10. ⟨lirmm-00370365⟩

    Conference papers16 documents

    • Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell. Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. LATS: Latin-American Test Symposium, Mar 2018, Sao Paulo, Brazil. ⟨10.1109/LATW.2018.8349696⟩. ⟨lirmm-02064921⟩
    • Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell, et al.. Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2017, Bochum, Germany. pp.320-325, ⟨10.1109/ISVLSI.2017.63⟩. ⟨hal-01709614⟩
    • Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell, et al.. Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. ETS: European Test Symposium, May 2017, Limassol, Cyprus. ⟨10.1109/ETS.2017.7968208⟩. ⟨hal-01709615⟩
    • Freddy Forero, Jean-Marc Galliere, Michel Renovell, Víctor Champac. Analysis of short defects in FinFET based logic cells. LATS: Latin American Test Symposium, Mar 2017, Bogota, Colombia. ⟨10.1109/LATW.2017.7906755⟩. ⟨hal-01709620⟩
    • Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell. Impact of VT and Body-Biasing on Resistive short detection in 28nm UTBB FDSOI – LVT and RVT configurations. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, PA, United States. pp.164-169, ⟨10.1109/ISVLSI.2016.102⟩. ⟨lirmm-01374292⟩
    • Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell. Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect. LATS: Latin-American Test Symposium, Mar 2016, Foz do Iguacu, Brazil. pp.129-134, ⟨10.1109/LATW.2016.7483352⟩. ⟨lirmm-01374300⟩
    • Jean-Marc Galliere, Florence Azaïs, Michel Renovell, Luigi Dilillo. Influence of Gate Oxide Short Defects on the Stability of Minimal Sized SRAM Core-Cell by Applying Non-Split Models. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2009, Cairo, Egypt. pp.225-229. ⟨lirmm-00370798⟩
    • I. Polian, Kundu Sandip, Jean-Marc Galliere, P. Engelke, Michel Renovell, et al.. Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron Technologies. VTS'05: 23rd IEEE VLSI Test Symposium, May 2005, Palm Springs, CA (USA), pp.343-348. ⟨lirmm-00105997⟩
    • S. Bernardini, P. Masson, Jean-Michel Portal, Jean-Marc Galliere, Michel Renovell. Impact of Gate Oxide Reduction Failure on Analog Applications: Example of the Current Mirror. LATW: Latin American Test Workshop, Mar 2004, Cartagena, Spain. pp.12-17. ⟨lirmm-00108659⟩
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand, Jean-Michel Portal, et al.. GOSMOS: A Gate Oxide Short Defect Embedded in a MOS Compact Model. LATW: Latin American Test Workshop, Feb 2003, Natal, Brazil. ⟨lirmm-00269604⟩
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Delay Testing of MOS Transistor with Gate Oxide Short. ATS: Asian Test Symposium, Nov 2003, Xian, China. pp.168-173. ⟨lirmm-00269641⟩
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. A Non-Split Model for Realistic Gate Oxide Short in CMOS Technology. DCIS: Design of Circuits and Integrated Systems, 2002, Santander, Spain. pp.197-204. ⟨lirmm-00268432⟩
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Low Voltage Testing of Gate Oxide Short in CMOS Technology. DDECS: Design and Diagnostics of Electronic Circuits and Systems, 2002, Brno, Czech Republic. pp.168-174. ⟨lirmm-00268526⟩
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Non-Linear and Non-Split Transistor MOS Model for Gate Oxyde Short. DBT: Defect Based Testing, Apr 2002, Monterey, CA, United States. pp.11-16. ⟨lirmm-00269333⟩
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Modeling Gate Oxide Short Defects in CMOS Minimum Transistors. ETW: European Test Workshop, 2002, Corfu, Greece. pp.15-20. ⟨lirmm-00268527⟩
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Boolean and Current Detection of MOS Transistor with Gate Oxide Short. IEEE International Test Conference, Oct 2001, Baltimore, USA, pp.10. ⟨lirmm-00370400⟩

    Reports1 document

    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand, Jean-Michel Portal. A Compact Model for Electrical Simulation of MOS Transistor with Gate Oxide Short Defect. [Research Report] 04080, Lirmm, University of Montpellier. 2004. ⟨lirmm-00109221⟩