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    179

    Publications of Michel Renovell


    Article dans une revue33 documents

    • Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell. Influence of Body-Biasing, Supply Voltage, and Temperature on the Detection of Resistive Short Defects in FDSOI Technology. IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers, 2017, 16 (3), pp.417-430. 〈10.1109/TNANO.2017.2664895〉. 〈hal-01709588〉
    • Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell. Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. Journal of Electronic Testing, Springer Verlag, 2017, 33 (4), pp.515-527. 〈10.1007/s10836-017-5674-9〉. 〈hal-01709587〉
    • Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, et al.. Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies. Microelectronics Journal, Elsevier, 2015, 46 (11), pp.1091-1102. 〈10.1016/j.mejo.2015.09.014〉. 〈lirmm-01232890〉
    • Jean-Marc Galliere, Florence Azaïs, Mariane Comte, Michel Renovell. Testing for Gate Oxide Short Defects using the Detectability Interval Paradigm. Information Technology, Oldenbourg Verlag, 2014, 56 (4), pp.173-181. 〈http://www.degruyter.com/view/j/itit〉. 〈10.1515/itit-2013-1040〉. 〈hal-01167054〉
    • Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, et al.. Enhancing Confidence in Indirect Analog/RF Testing against the Lack of Correlation between Regular Parameters and Indirect Measurements. Microelectronics Journal, Elsevier, 2014, 45 (3), pp.336-344. 〈10.1016/j.mejo.2013.12.006〉. 〈lirmm-00936443〉
    • Vincent Kerzérho, Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, et al.. A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC. Microelectronics Journal, Elsevier, 2013, 44 (9), pp.840-843. 〈http://www.sciencedirect.com/science/article/pii/S0026269213001468〉. 〈10.1016/j.mejo.2013.06.009〉. 〈lirmm-00875985〉
    • Vincent Kerzérho, Mariane Comte, Florence Azaïs, Philippe Cauvet, Serge Bernard, et al.. Digital Test Method for Embedded Converters with Unknown-Phase Harmonics. Journal of Electronic Testing, Springer Verlag, 2011, 27 (3), pp.335-350. 〈10.1007/s10836-011-5194-y〉. 〈lirmm-00609243〉
    • Vincent Kerzérho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Michel Renovell, et al.. ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator. VLSI Design, Hindawi Publishing Corporation, 2008, 2008 (Article ID 482159), pp.8. 〈10.1155/2008/482159〉. 〈lirmm-00346722〉
    • Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, et al.. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2008, 27 (2), pp.327-338. 〈lirmm-00375007〉
    • Vincent Kerzérho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, et al.. Fully Digital Test Solution for a Set of ADCs and DACs embedded in a SiP or SoC. IET Computers & Digital Techniques, Institution of Engineering and Technology, 2007, 1 (3), pp.146-153. 〈lirmm-00195172〉
    • Serge Bernard, Vincent Kerzérho, Philippe Cauvet, Florence Azaïs, Mariane Comte, et al.. A Novel DFT Technique to Test a Complete Set of ADC's and DAC's Embedded in a Complex SiP. IEEE Design & Test, IEEE, 2006, 23 (3), pp.237-243. 〈lirmm-00115131〉
    • Piet Engelke, Michel Renovell, Bernd Becker. Automatic Test Pattern Generation for Resistive Bridging Faults. Journal of Electronic Testing, Springer Verlag, 2006, 22 (1), pp.61-69. 〈lirmm-00375014〉
    • Patrick Girard, Serge Pravossoudovitch, Olivier Héron, Michel Renovell. An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. Journal of Electronic Testing, Springer Verlag, 2006, 22 (2), pp.161-172. 〈lirmm-00135456〉
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker. Simulating Resistive-Bridging and Stuck-At Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2006, 25 (10), pp.2181-2192. 〈lirmm-00375012〉
    • Jean-Marc Galliere, Michel Renovell, Florence Azaïs, Yves Bertrand. Delay Testing Viability of Gate Oxide Short Defect. Journal of Computer Science and Technology, Iberoamerican Science & Technology Education Consortium, 2005, 20 (2), pp.195-200. 〈10.1007/s11390-005-0195-x〉. 〈lirmm-00105323〉
    • Jean-Marc Galliere, Michel Renovell, Florence Azaïs, Yves Bertrand. Viability of a Delay Testing of Gate Oxide Short Transistors. Journal of Computer Science and Technology, Iberoamerican Science & Technology Education Consortium, 2005, 20 (2), pp.6. 〈lirmm-00370370〉
    • I. Polian, P. Engelke, Michel Renovell, P. Becker. Modeling Feedback Bridging Faults with Non-Zero Resistance. Journal of Electronic Testing, Springer Verlag, 2005, 21 (1), pp.57-69. 〈lirmm-00105327〉
    • Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. Journal of Electronic Testing, Springer Verlag, 2005, 21 (1), pp.43-55. 〈lirmm-00105329〉
    • Florence Azaïs, Serge Bernard, Mariane Comte, Yves Bertrand, Michel Renovell. Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. Journal of Electronic Testing, Springer Verlag, 2005, 21 (3), pp.291-298. 〈lirmm-00105322〉
    • Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell. Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. Journal of Electronic Testing, Springer Verlag, 2005, 21 (2), pp.135-146. 〈10.1007/s10836-005-6143-4〉. 〈lirmm-00105334〉
    • Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell. A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. Journal of Electronic Testing, Springer Verlag, 2005, 21 (1), pp.9-16. 〈lirmm-00105328〉
    • Antonio Andrade, Gustavo Vieira, Tiago Balen, Marcelo Lubaszewski, Florence Azaïs, et al.. Built-In Self-Test of Global Interconnects of Field Programmable Analog Arrays. Microelectronics Journal, Elsevier, 2005, 36 (12), pp.1112-1123. 〈lirmm-00367974〉
    • Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell. Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure. Journal of Electronic Testing, Springer Verlag, 2004, 20 (4), pp.375-387. 〈lirmm-00108545〉
    • Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell. Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors. Journal of Electronic Testing, Springer Verlag, 2004, Vol. 20 n°3, pp. 257-267. 〈hal-00004514〉
    • R. Bouchakour, J.M. Portal, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand, et al.. A Compact DC Model of Gate Oxide Short Defect. Microelectronic Engineering, Elsevier, 2004, 72 (1-4), pp.140-148. 〈lirmm-00108564〉
    • Uroš Kač, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell. Extending IEEE Std. 1149.4 analog boundary modules to enhance mixed-signal test. IEEE Design & Test, IEEE, 2003, 20 (2), pp.32-39. 〈10.1109/MDT.2003.1188260〉. 〈lirmm-00269600〉
    • Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei. An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. IEEE Design & Test, IEEE, 2003, 20 (1), pp.60-67. 〈lirmm-00269822〉
    • Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell. On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. Journal of Electronic Testing, Springer Verlag, 2003, 19 (4), pp. 469-479. 〈lirmm-00269602〉
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Modeling the Random Parameter Effects in a Non-Split Model of Gate Oxide Short. Journal of Electronic Testing, Springer Verlag, 2003, 19 (4), pp. 377-386. 〈lirmm-00269754〉
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. Journal of Electronic Testing, Springer Verlag, 2003, 19 (4), pp.10. 〈lirmm-00370365〉
    • Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell. A-to-D Converter Static Error Detection from Dynamic Parameter Measurements. Microelectronics Journal, Elsevier, 2003, 34 (10), pp. 945-953. 〈lirmm-00269601〉
    • Michel Renovell, Florence Azaïs, Yves Bertrand. Improving Defect Detection in Static-Voltage Testing. IEEE Design & Test, IEEE, 2002, 17 (6), pp.83-89. 〈lirmm-00268605〉
    • Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell. Analog Built-In Saw-Tooth Generator for ADC Histogram Test. Microelectronics Journal, Elsevier, 2002, 33 (10), pp.781-789. 〈lirmm-00268587〉

    Communication dans un congrès118 documents

    • Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell, et al.. Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2017, Bochum, Germany. IEEE, IEEE International Symposium on Very Large Scale Integration, 2017, 〈10.1109/ISVLSI.2017.63〉. 〈hal-01709614〉
    • Freddy Forero, Jean-Marc Galliere, Michel Renovell, Victor Champac. Analysis of short defects in FinFET based logic cells. LATS: Latin American Test Symposium, Mar 2017, Bogota, Colombia. IEEE, 18th IEEE Latin American Test Symposium, 2017, 〈10.1109/LATW.2017.7906755〉. 〈hal-01709620〉
    • Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell, et al.. Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. ETS: European Test Symposium, May 2017, Limassol, Cyprus. IEEE, 22nd IEEE European Test Symposium, 2017, 〈10.1109/ETS.2017.7968208〉. 〈hal-01709615〉
    • Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras. Mitigating Read & Write Errors in STT-MRAM Memories under DVS. ETS: European Test Symposium, May 2017, Limassol, Cyprus. IEEE, 22nd IEEE European Test Symposium, 2017, 〈10.1109/ETS.2017.7968209〉. 〈hal-01525720〉
    • Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell. Impact of VT and Body-Biasing on Resistive short detection in 28nm UTBB FDSOI – LVT and RVT configurations. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, United States. Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI’16), 2016, 〈http://www.eng.ucy.ac.cy/theocharides/isvlsi16/cfp.html〉. 〈10.1109/ISVLSI.2016.102〉. 〈lirmm-01374292〉
    • Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell. Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect. LATS: Latin-American Test Symposium, Mar 2016, Foz do Iguacu, Brazil. 17th IEEE Latin-American Test Symposium, pp.129-134, 2016, 〈10.1109/LATW.2016.7483352〉. 〈lirmm-01374300〉
    • Achraf Lamlih, Vincent Kerzérho, Serge Bernard, Fabien Soulier, Mariane Comte, et al.. Mixed-level simulation tool for design optimization of electrical impedance spectroscopy systems. IWIS: International Workshop on Impedance Spectroscopy, Sep 2016, Chemnitz, Germany. Session: Bioimpedance Spectroscopy II (N012). 〈https://www.tu-chemnitz.de/etit/messtech/iwis/openconf/modules/request.php?module=oc_program&action=program.php〉. 〈lirmm-01457544〉
    • Vincent Kerzérho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, et al.. Toward adaptation of ADCs to operating conditions through on-chip correction. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI’15), pp.634-639, 2015, 〈10.1109/ISVLSI.2015.62〉. 〈lirmm-01233117〉
    • Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, et al.. A generic methodology for building efficient prediction models in the context of alternate testing. IMSTW: International Mixed-Signals Test Workshop, Jun 2015, Paris, France. IEEE, 2015, Mixed-Signal Testing Workshop (IMSTW), 2015 20th International. 〈10.1109/IMS3TW.2015.7177873〉. 〈lirmm-01233150〉
    • Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, et al.. A framework for efficient implementation of analog/RF alternate test with model redundancy. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. IEEE, Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI’15), pp.621-626, 2015, 〈10.1109/ISVLSI.2015.30〉. 〈lirmm-01233104〉
    • Vincent Kerzérho, Florence Azaïs, Mouhamadou Dieng, Mariane Comte, Serge Bernard, et al.. Self-Adaptive NFC Systems. IOLTS'14: 20th International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Spain. IEEE, 2014, Special Session 4 – Solutions for the self-adaptation of communicating systems in operation. 〈lirmm-01084355〉
    • Mouhamadou Dieng, Florence Azaïs, Mariane Comte, Serge Bernard, Vincent Kerzérho, et al.. Study of adaptive tuning strategies for Near Field Communication (NFC) transmitter module. IMS3TW'14: International Mixed-Signals, Sensors, and Systems Test Workshop, Sep 2014, Porto ALegre, Brazil. IEEE, pp.1-6, 〈10.1109/IMS3TW.2014.6997401〉. 〈lirmm-01119365〉
    • Haithem Ayari, Florence Azaïs, Serge Bernard, Vincent Kerzérho, Syhem Larguech, et al.. Investigations on alternate analog/RF test with model redundancy. STEM'14: 1st Workshop on Statistical Test Methods, 2014, Paderborn, Germany. 〈lirmm-01119374〉
    • Syhem Larguech, Florence Azaïs, Serge Bernard, Vincent Kerzérho, Mariane Comte, et al.. Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing. LATW: Latin American Test Workshop, Mar 2014, Fortaleza, Brazil. 15th IEEE Latin American Test Workshop, pp.1-6, 2014, 〈10.1109/LATW.2014.6841930〉. 〈lirmm-01119361〉
    • Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, et al.. New implementions of predictive alternate analog/RF test with augmented model redundancy. DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. 2014, 〈http://www.date-conference.com/〉. 〈10.7873/DATE2014.144〉. 〈lirmm-00994714〉
    • Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, et al.. Solutions for the self-adaptation of communicating systems in operation. IOLTS: International International On-line Test Symposium, Jul 2014, Platja d’Aro, Spain. IEEE Computer Society, 20th International International On-line Test Symposium, pp.234-239, 2014, 〈10.1109/IOLTS.2014.6873705〉. 〈hal-01118068〉
    • Mouhamadou Dieng, Mariane Comte, Serge Bernard, Vincent Kerzérho, Florence Azaïs, et al.. Accurate and Efficient Analytical Electrical Model of Antenna for NFC Applications. NEWCAS: International New Circuits and Systems Conference, Jun 2013, Paris, France. IEEE, 11th International NEWCAS Conference (NEWCAS), pp.137-141, 2013, 〈http://newcas2013.org/〉. 〈lirmm-00839190〉
    • Jie Jiang, Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, et al.. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. ATS: Asian Test Symposium, Nov 2013, Jiaosi Township, Taiwan. 22nd Asian Test Symposium, pp.177-182, 2013, 〈10.1109/ATS.2013.41〉. 〈lirmm-00932357〉
    • Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Jie Jiang, et al.. Pre-characterization Procedure for a Mixed Mode Simulation of IR-Drop Induced Delays. LATW: Latin American Test Workshop, Apr 2013, Cordoba, Argentina. 14th Latin American Test Workshop, 2013, 〈http://tima.imag.fr/conferences/latw2013/〉. 〈10.1109/LATW.2013.6562657〉. 〈lirmm-00820067〉
    • Syhem Larguech, Florence Azaïs, Serge Bernard, Vincent Kerzérho, Mariane Comte, et al.. A Comparative Analysis of Indirect Measurement Selection Strategies for Analog/RF Alternate Testing. 3rd IEEE International Workshop on Test and Validation of High Speed Analog Circuits, Sep 2013, Anaheim, CA, United States. 2013. 〈lirmm-00985422〉
    • Marina Aparicio, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell, et al.. An IR-Drop Simulation Principle Oriented to Delay Testing. DCIS'12: 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.404-409, 2012, 〈http://www.lirmm.fr/dcis2012/index.php〉. 〈lirmm-00804254〉
    • Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, et al.. On the use of redundancy to reduce prediction error in alternate analog/RF test. IMS3TW: International Mixed-Signals, Sensors, and Systems Test Workshop, May 2012, Taipei, Taiwan. 18th Annual IEEE International Mixed-Signals, Sensors, and Systems Test Workshop, pp.34-39, 2012, 〈10.1109/IMS3TW.2012.17〉. 〈lirmm-00803556〉
    • Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, et al.. Making predictive analog/RF alternate test strategy independent of training set size. ITC'2012: International Test Conference, Nov 2012, Anaheim, CA, United States. IEEE, pp.9, 2012, 〈10.1109/TEST.2012.6401560〉. 〈lirmm-00803564〉
    • Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Michel Renovell, et al.. Smart selection of indirect parameters for DC-based alternate RF IC testing. VTS: VLSI Test Symposium, Apr 2012, Hyatt Maui, HI, United States. IEEE, pp.19-24, 2012, 〈10.1109/VTS.2012.6231074〉. 〈lirmm-00803453〉
    • Vincent Kerzérho, Florence Azaïs, Mariane Comte, Philippe Cauvet, Serge Bernard, et al.. ANC-Based Method for Testing Converters with Random-Phase Harmonics. IMS3TW'10: 16th International Mixed-Signals, Sensors and Systems Test Workshop, La Grande Motte, Montpellier, France. pp.N/A, 2010. 〈lirmm-00494578〉
    • Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, Vincent Kerzérho, et al.. Adaptive LUT-Based System for In Situ ADC Auto-correction. IMS3TW'10: 16th IEEE International Mixed-Signals, Sensors and Systems Test Workshop, La Grande Motte, Montpellier, France. pp.N/A, 2010. 〈lirmm-00494424〉
    • Florence Azaïs, Yves Bertrand, Michel Renovell. An Analysis of the Timing Behavior of CMOS Digital Blocks under Simultaneous Switching Noise Conditions. DDECS'09: IEEE Design and Diagnostics of Electronic Circuits and Systems, Apr 2009, Liberec, Czech Republic. pp.158-163, 2009. 〈lirmm-00386906〉
    • Vincent Kerzérho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, et al.. A Multi-Converter DFT Technique for Complex SIP: Concepts and Validation. ECCTD: European Conference on Circuit Theory and Design, Aug 2009, Antalya, Turkey. IEEE, pp.747-750, 2009, New Trends in A/D Converters Design & Testing. 〈http://ecctd09.dogus.edu.tr/〉. 〈lirmm-00448863〉
    • Serge Bernard, Florence Azaïs, Mariane Comte, Yves Bertrand, Michel Renovell. LH-BIST for Digital Correction of ADC Offset. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2009, Cairo, Egypt. 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, pp.199-203, 2009. 〈lirmm-00375659〉
    • Jean-Marc Galliere, Florence Azaïs, Michel Renovell, Luigi Dilillo. Influence of Gate Oxide Short Defects on the Stability of Minimal Sized SRAM Core-Cell by Applying Non-Split Models. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2009, Cairo, Egypt. 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, pp.225-229, 2009. 〈lirmm-00370798〉
    • Florence Azaïs, Yves Bertrand, Michel Renovell. Analyzing the Impact of Simultaneous Switching Noise on the Timing Behavior of CMOS Digital Blocks. LATW'09: 10th Latin-American Test Workshop, Mar 2009, Armaçao dos Buzios, Brazil, pp.N/A, 2009. 〈lirmm-00367718〉
    • Nicolas Houarche, Alejandro Czutro, Mariane Comte, Piet Engelke, Ilia Polian, et al.. Deriving an Electrical Model for Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. LATW'09: 10th Latin-American Test Workshop, Mar 2009, Armaçao dos Buzios, Brazil, pp.N/A, 2009. 〈lirmm-00367708〉
    • Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, et al.. An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. VTS'09: 27th VLSI Test Symposium, May 2009, Santa Cruz, Californie, United States. IEEE, pp.21-26, 2009, 〈http://www.tttc-vts.org/public_html/new/2009/index.php〉. 〈10.1109/VTS.2009.57〉. 〈lirmm-00374941〉
    • Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell. On the Detection of SSN-Induced Logic Errors Through On-Chip Monitoring. IOLTS'08: 14th IEEE International On-Line Testing Symposium, Jul 2008, Rhodes, Greece, IEEE, pp.233-238, 2008. 〈lirmm-00294767〉
    • Michel Renovell, Mariane Comte, Nicolas Houarche, Ilia Polian, Piet Engelke, et al.. A Model for Resistive Open Recursivity in CMOS Random Logic. EWDTS'08: IEEE East-West Design & Test Symposium, Oct 2008, Ukraine. pp.21-24, 2008, 〈http://ewdtest.com/conf/〉. 〈lirmm-00381465〉
    • Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell. On-Chip Monitor for the Detection of Logic Errors due to Simultaneous Switching Noise. LATW'08: 9th Latin-American Test Workshop, Puebla, Mexico, IEEE, pp.11-16, 2008. 〈lirmm-00260194〉
    • Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, et al.. A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. ETS: European Test Symposium, May 2008, Verbania, Italy. 13th IEEE European Test Symposium, pp.113-118, 2008. 〈lirmm-00285886〉
    • Vincent Kerzérho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Michel Renovell, et al.. Fully-Efficient ADC Test Technique for ATE with Low Resolution Arbitrary Wave Generators. IMSTW'07: International Mixed-Signals Testing Workshop and 3rd International GHz/Gbps Test Workshop, Jun 2007, Povoa de Varzim, Portugal. pp.196-201, 2007. 〈lirmm-00161708〉
    • Philippe Cauvet, Serge Bernard, Michel Renovell. System-in-Package, a Combination of Challenges and Solutions. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.193-199, 2007. 〈lirmm-00158123〉
    • Vincent Kerzérho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, et al.. "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.211-216, 2007, 〈10.1109/ETS.2007.1〉. 〈lirmm-00158527〉
    • Rahebeh Niaraki Asli, Zainalabedin Navabi, Sattar Mirzakuchaki, Michel Renovell. Accessibility to Embedded A/MS Cores: An Oscillation-Based S-R DFT. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.77-81, 2007. 〈lirmm-00158961〉
    • Florence Azaïs, Laurent Larguier, Michel Renovell. Analyzing the Logic Behavior of Digital CMOS Circuits in Presence of Simultaneous Switching Noise. LATW: Latin American Test Workshop, Mar 2007, Cuzco, Peru. 8th IEEE Latin American Test Workshop, 2007. 〈lirmm-00199261〉
    • Florence Azaïs, Laurent Larguier, Michel Renovell. Impact of Simultaneous Switching Noise on the Static Behavior of Digital CMOS Circuits. ATS: Asian Test Symposium, Oct 2007, Beijing, China. 16th IEEE Asian Test Symposium, pp.239-244, 2007. 〈lirmm-00179262〉
    • Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker. SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges. ATS: Asian Test Symposium, Oct 2007, Beijing, China. 16th IEEE Asian Test Symposium, pp.433-438, 2007. 〈lirmm-00179272〉
    • Serge Bernard, Michel Renovell. State of the art in soc testing: The analog challenge. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2006, Tunis, Tunisia. Design and Technology of Integrated Systems in Nanoscale Era, 2006, 〈http://www.proceedings.com/00639.html〉. 〈lirmm-00407019〉
    • Serge Bernard, Florence Azaïs, Philippe Cauvet, Mariane Comte, Vincent Kerzérho, et al.. Experimental Validation of the "Analogue Network of Converters" Technique to Test Complex SiP/SoC. IEEE International Mixed-Signal Testing Workshop, Jun 2006, Paris, France. pp.84-88, 2006. 〈lirmm-00119266〉
    • Michel Renovell. Testing for Realistic Spot Defects in CMOS Technology: a Unified View. IEEE. EWDTW'06: Proceedings of IEEE East-West Design & Test Workshop, Sep 2006, Sochi (Russia), pp.482, 2006. 〈lirmm-00096254〉
    • Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker. Analysing the Memory Effect of Resistive Open in CMOS Random Logic. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2006, Tunis, Tunisia. Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on, pp.251-256, 2006. 〈lirmm-00093383〉
    • Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Vincent Kerzérho, et al.. “Analogue Network of Converters”: A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. ETS: European Test Symposium, May 2006, Southampton, United Kingdom. 11th IEEE European Test Symposium, pp.159-164, 2006. 〈lirmm-00115676〉
    • Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker. Delta-Iddq Testing of Resistive Short Defects. ATS: Asian Test Symposium, Nov 2006, Fukuoka, Japan. 15th IEEE Asian Test Symposium, pp.63-68, 2006. 〈lirmm-00117020〉
    • Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker. A Specific ATPG Technique for Resistive Open with Sequence Recursive Dependency. ATS: Asian Test Symposium, Nov 2006, Fukuoka, Japan. 15th IEEE Asian Test Symposium, pp.273-278, 2006, 〈10.1109/ATS.2006.261031〉. 〈lirmm-00117022〉
    • Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell. Electrical Behavior of GOS Fault Affected Domino Logic Cell. DELTA'06: IEEE International Workshop on Electronics DesignTest & Applications, Jan 2006, Kuala Lumpur, Malaysia, IEEE, pp.183-189, 2006. 〈lirmm-00102703〉
    • Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell. Electrical Behavior of GOS Faults in Domino Logic. DDECS'05: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2005, Sopron, Hungary, IEEE, pp.210-215, 2005. 〈lirmm-00105991〉
    • I. Polian, Kundu Sandip, Jean-Marc Galliere, P. Engelke, Michel Renovell, et al.. Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron Technologies. VTS'05: 23rd IEEE VLSI Test Symposium, May 2005, Palm Springs, CA (USA), IEEE Computer Society, pp.343-348, 2005. 〈lirmm-00105997〉
    • Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, et al.. Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. VTS: VLSI Test Symposium, May 2005, Palm Springs, CA, United States. 23rd IEEE VLSI Test Symposium, pp.389-400, 2005, 〈10.1109/VTS.2005.85〉. 〈lirmm-00105998〉
    • Michel Renovell, S. Tanguy. A Set of Test Configurations for the Global Routing of Hierarchical SRAM-Based FPGA. IBERCHIP'05, 2005, Salvador, Bahia, Bahamas. pp.277-280, 2005. 〈lirmm-00106512〉
    • Arnaud Regnier, Jean-Michel Portal, Rachid Bouchakour, Michel Renovell. Modeling Halo Implant Failures in MOS Sub-Micron Technology. LATW: Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. 6th IEEE Latin American Test Workshop, pp.29-33, 2005. 〈lirmm-00106513〉
    • Antonio Zenteno, Victor Champac, Michel Renovell, Florence Azaïs. Analysis and Attenuation Proposal in Ground Bounce: II. LATW: Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. 6th IEEE Latin American Test Workshop, pp.34-39, 2005. 〈lirmm-00106514〉
    • Tiago R. Balen, Tiago Jost, Jose Vicente Calvano, Marcelo Lubaszewski, Michel Renovell. The Transient Reponse Analysis Method Applied to the Test of Field Programmable Analog Arrays: Feasibility Study. LATW: Latin American Test Workshop, Mar 2005, Salvador, Brazil. 6th IEEE Latin American Test Workshop, pp.252-257, 2005. 〈lirmm-00106518〉
    • Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell. Fast and Fully-Efficient Test Flow for ADCs. IMSTW'05: 11th IEEE International Mixed-Signal Testing Workshop, Jun 2005, Cannes, pp.244-249, 2005. 〈lirmm-00106523〉
    • Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell. Electrical Analysis of a Domino Logic Cell with GOS Faults. DBT'05: International Workshop on Current & Defect Based Testing, May 2005, Palm Springs, CA, United States. 2005, 〈http://www.cs.colostate.edu/~malaiya/dbt05.html〉. 〈lirmm-00374937〉
    • Antonio Zenteno, Victor Champac, Michel Renovell, Florence Azaïs. Analysis and Attenuation Proposal in Ground Bounce. ATS: Asian Test Symposium, Nov 2004, Kenting Taiwan. 13th IEEE Asian Test Symposium, pp.460-463, 2004, 〈10.1109/ATS.2004.25〉. 〈lirmm-00108931〉
    • Antonio Andrade Jr, Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, et al.. Testing Global Interconnects of Field Programmable Analog Arrays . IMSTW'04: 10th International Mixed-Signal Testing Workshop, Jun 2004, Portland, Oregon, United States. 2004. 〈lirmm-00108657〉
    • S. Bernardini, P. Masson, J.M. Portal, Jean-Marc Galliere, Michel Renovell. Impact of Gate Oxide Reduction Failure on Analog Applications: Example of the Current Mirror. LATW'04: 5th IEEE Latin American Test Workshop, Mar 2004, Cartagena, pp.12-17, 2004. 〈lirmm-00108659〉
    • P. Engelke, I. Polian, Michel Renovell, B. Seshadri, P. Becker. The Pros and Cons of Very-Low-Voltage Testing: An Analysis Based on Resistive Bridging Faults. GI/ITG Workshop Testmethoden und Zuverlassigkeit von Schaltungen und Systemen, Feb 2004, Dresden, Germany. pp.149-153, 2004. 〈lirmm-00108660〉
    • Michel Renovell. Digital and Analog System Testing: Fundamentals and New Challenges. ICM'04: 16th International Conference on Microelectronics, Dec 2004, Tunis (Tunisia), IEEE, pp.8-10, 2004. 〈lirmm-00108936〉
    • Michel Renovell. Principe et Problèmatique pour le Test des System-0n-Chip. SCS'04: SignauxCircuits et Systèmes, Mar 2004, Monastir (Tunisie), pp.1-3, 2004. 〈lirmm-00108842〉
    • Mehdi Tahoori, Edward Mccluskey, Michel Renovell, Philippe Faure. A Multi-Configuration Strategy for an Application Dependant Testing of FPGAs. VTS: VLSI Test Symposium, Apr 2004, Napa Valley, CA, United States. 22nd IEEE VLSI Test Symposium, pp.154-159, 2004, 〈10.1109/VTEST.2004.1299239〉. 〈lirmm-00108844〉
    • Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell. Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. ITC: International Test Conference, Oct 2004, Charlotte, United States. pp.893-902, 2004. 〈lirmm-00108897〉
    • Piet Engelke, I. Polian, Michel Renovell, P. Becker. Automatic Test Pattern Generation for Resistive Bridging Faults. ETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. 9th IEEE European Test Symposium, pp.160-165, 2004. 〈lirmm-00108902〉
    • Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell. An Approach to the Built-in-Self of Field Programmable Analog Arrays. VTS: VLSI Test Symposium, Apr 2004, Napa Valley, CA, United States. 22nd IEEE VLSI Test Symposium, pp.383-388, 2004. 〈lirmm-00108908〉
    • David Hely, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Berard, et al.. Scan Design and Secure Chip. IOLTS'04: 10th International On-Line Testing Symposium, Jul 2004, Madeira Island, Portugal. IEEE, pp.219-224, 2004. 〈lirmm-00108909〉
    • Michel Renovell. Realistic Fault Models for Defects in Electronic Circuits. BEC'04: International Baltic Electronic Conference, Oct 2004, pp.33-37, 2004. 〈lirmm-00109134〉
    • P. Engelke, I. Polian, Michel Renovell, P. Becker. Automatic Test Pattern Generation for Resistive Bridging Faults. IEEE International Workshop on Current and Defect-Based Testing, May 2004, Napa Valley, CA, pp.89-94, 2004. 〈lirmm-00108661〉
    • Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS'04: 10th International On-Line Testing Symposium, Jul 2004, Madeira Island (Portugal), IEEE Computer Society, pp.187-192, 2004. 〈lirmm-00108824〉
    • Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA'04: 2nd International Workshop on Electronic DesignTest and Applications, Jan 2004, Perth (Australia), IEEE Computer Society, pp.83-88, 2004. 〈lirmm-00108830〉
    • P. Engelke, I. Polian, Michel Renovell, B. Seshadri, P. Becker. The Pros and Cons of Very-Low-Voltage Testing: An Analysis Based on Resistive Bridging Faults. VTS'04: 22nd IEEE VLSI Test Symposium, Apr 2004, Napa Valley, CA (USA), pp.171-178, 2004. 〈lirmm-00108845〉
    • Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. Manufacturing-Oriented Testing of Delay Faults in the Logic Architecture of Symmetrical FPGAs. ETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. 9th IEEE European Test Symposium, pp.117-122, 2004. 〈lirmm-00108905〉
    • Michel Renovell. Fundamentals of System Testing: Challenges for System-On-Chips. ICM'04: 16th International Conference on Microelectronics, Dec 2004, P., France. pp.176-180, 2004. 〈lirmm-00109135〉
    • Michel Renovell. Structural Testing of Modern Reconfigurable Chips. EWDTC: East-West Design & Test Conference, Sep 2003, Moscou, Russia. pp.5-9, 2003. 〈lirmm-00269648〉
    • M. Zottino, Alfredo Benso, Michel Renovell, Yves Bertrand, Luz Maria Balado Suarez, et al.. Hard to Detect Bridging Defects in a Cross-Point Digital Switch. LATW: Latin American Test Workshop, Feb 2003, Natal, Brazil. 4th IEEE Latin-American Test Workshop, pp.12-18, 2003, DIGEST OF PAPERS. 〈lirmm-00269496〉
    • Michel Renovell, Tiago R. Balen, M. Schreiber, Florence Azaïs, Marcelo Lubaszewski. OBIST Applied to FPAAs: A Case Study. LATW: Latin American Test Workshop, Feb 2003, Natal, Brazil. 4th IEEE Latin American Test Workshop, pp.238-243, 2003. 〈lirmm-00269501〉
    • Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell. A New Methodology for ADC Test FLow Optimization. ITC'03: International Test Conference, Sep 2003, Charlotte, NC, United States. pp.201-209, 2003. 〈lirmm-00269610〉
    • Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. Timing Defect Analysis in Look-Up Tables of SRAM-Based FPGAs. LATW: Latin American Test Workshop, Feb 2003, Natal, Brazil. 4th IEEE Latin American Test Workshop, pp.26-31, 2003. 〈lirmm-00269497〉
    • Mariane Comte, Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell. On the Efficiency of Measuring ADC Dynamic Parameters to Detect ADC Static Errors. LATW: Latin American Test Workshop, Feb 2003, Natal, Brazil. 4th IEEE Latin American Test Workshop, pp.198-203, 2003. 〈lirmm-00269498〉
    • Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell. On the Synthesis of Analog Cascaded Filters with Optimal Test Point Insertion. LATW: Latin American Test Workshop, Feb 2003, Natal, Brazil. 4th IEEE Latin American Test Workshop, pp.212-216, 2003. 〈lirmm-00269499〉
    • Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. Requirements for Delay Testing of Look-Up Tables in SRAM-Based FPGAs. ETW: European Test Workshop, May 2003, Maastricht, Netherlands. 8th IEEE European Test Workshop, pp.147-152, 2003. 〈lirmm-00269530〉
    • Serge Bernard, Florence Azaïs, Mariane Comte, Yves Bertrand, Michel Renovell. An Automatic Tool for Generation of ADC BIST Architecture. IMSTW: International Mixed-Signal Testing Workshop, Jun 2003, Sevilla, Spain. 9th IEEE International Mixed-Signal Testing Workshop, pp.79-84, 2003. 〈lirmm-00269580〉
    • Mariane Comte, Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell. Analysis of the Specification Influence on the Efficiency of an Optimized Test Flow for ADCs. IMSTW: International Mixed-Signal Testing Workshop, Jun 2003, Sevilla, Spain. 9th IEEE International Mixed-Signal Testing Workshop, pp.185-190, 2003. 〈lirmm-00269583〉
    • Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. Conditions pour le Test de Pannes de Délai des Look-Up Table dans les FPGA à Base de SRAM. JNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2003, Toulouse, France. 6ièmes Journées Nationales du Réseau Doctoral de Microélectronique, pp.381-383, 2003. 〈lirmm-00269544〉
    • Michel Renovell. Testing Challenges for Modern FPGAs. ECS: Electronic Circuits and Systems, Sep 2003, Bratislava, Slovenia. 4th Electronic Circuits and Systems, pp.1-9, 2003. 〈lirmm-00269565〉
    • Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS: International On-Line Testing Symposium, Jul 2003, Kos, Greece. 9th IEEE On-Line Testing Symposium, pp.124-128, 2003. 〈lirmm-00269553〉
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand, Jean-Michel Portal, et al.. GOSMOS: A Gate Oxide Short Defect Embedded in a MOS Compact Model. LATW: Latin American Test Workshop, Feb 2003, Natal, Brazil. 4th IEEE Latin American Test Workshop, 2003. 〈lirmm-00269604〉
    • Serge Bernard, Florence Azaïs, Mariane Comte, Yves Bertrand, Michel Renovell. Automatic Generation of LH-BIST Architecture for ADC Testing. IWADC'03: IEEE International Workshop on ADC Modelling and Testing, Sep 2003, Perugia, Italy. pp.7-12, 2003. 〈lirmm-00269683〉
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Delay Testing of MOS Transistor with Gate Oxide Short. ATS: Asian Test Symposium, Nov 2003, Xian, China. 12th IEEE AsianTest Symposium, pp.168-173, 2003. 〈lirmm-00269641〉
    • Mariane Comte, Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell. A New Methodology for ADC Test Flow Optimization. ITC: International Test Conference, Sep 2003, Charlotte, NC, United States. pp.201-209, 2003, 〈10.1109/TEST.2003.1270841〉. 〈lirmm-00269527〉
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker. Simulating Resistive Bridging and Stuck-At Faults. ITC: International Test Conference, Sep 2003, Charlotte, NC, United States. International Test Conference, pp.1051-1059, 2003. 〈lirmm-00269611〉
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. A Non-Split Model for Realistic Gate Oxide Short in CMOS Technology. DCIS: Design of Circuits and Integrated Systems, 2002, Santander, Spain. 17th International Conference on Design of Circuits and Integrated Systems, pp.197-204, 2002. 〈lirmm-00268432〉
    • Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell. On-Chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. VLSI-SoC: Very Large Scale Integration of Systems-on-Chips, 2002, Montpellier, France. Kluwer Academic Publishers, 11th International Conference on Very Large Scale Integration of Systems-on-Chips, pp.425-436, 2002. 〈lirmm-00268477〉
    • Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell. A High Accuracy Triangle-Wave Signal Generator for On-Chip ADC Testing. ETW: European Test Workshop, 2002, Corfu, Greece. pp.89-94, 2002. 〈lirmm-00268483〉
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Low Voltage Testing of Gate Oxide Short in CMOS Technology. DDECS: Design and Diagnostics of Electronic Circuits and Systems, 2002, Brno, Czech Republic. 5th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp.168-174, 2002. 〈lirmm-00268526〉
    • Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell. Evaluation of ADC Static Parameters via Frequency Domain. IMSTW'02: 8th IEEE International Mixed-Signal Testing Workshop, Jun 2002, Montreux, Switzerland. pp.165-169, 2002. 〈lirmm-00269347〉
    • Mariane Comte, Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell. Mesure des Paramètres Statiques des Convertisseurs A/N par une Analyse Spectrale. Colloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.47-50, 2002. 〈lirmm-00269325〉
    • Florence Azaïs, Yves Bertrand, Jose Vicente Calvano, Marcelo Lubaszewski, Pascal Nouet, et al.. Designing Testable Analog Filters with Optimal DFT Insertion. IMSTW: International Mixed-Signal Testing Workshop, Jun 2002, Montreux, Switzerland. 8th International Mixed-Signal Testing Workshop, pp.201-203, 2002. 〈lirmm-00269341〉
    • Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell, et al.. Estimating Static Parameters of A-to-D Converters from Spectral Analysis. LATW: Latin American Test Workshop, Feb 2002, Montevideo, Uruguay. 3rd IEEE Latin American Test Workshop, pp.174-179, 2002. 〈lirmm-00269320〉
    • Mariane Comte, Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell. On the Evaluation of ADC Static Parameters Through Dynamic Testing. ADDA & EWADC, Jun 2002, Prague, Czech Republic. 4th International Conference on Advanced A/D and D/A Conversion Techniques and their Applications & 7th Workshop on ADC Modelling and Testing, pp.95-98, 2002. 〈lirmm-00269338〉
    • Michel Renovell, Philippe Faure, Paolo Prinetto, Yervant Zorian. Testing the Unidimensionnal Interconnect Architecture of Symmetrical SRAM-based FPGA. DELTA: Electronic Design, Test and Applications, Jan 2002, Christchurch, New Zealand. 1st IEEE International Workshop on Electronic Design, Test and Applications, pp.297-301, 2002, 〈10.1109/DELTA.2002.994634〉. 〈lirmm-00268528〉
    • Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. Pannes Temporelles dans les FPGA. Colloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.43-46, 2002. 〈lirmm-00269327〉
    • Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell. A New FPGA for DSP Applications Integrating BIST Capabilities. LATW'02: 3rd IEEE Latin American Test Workshop, Feb 2002, Montevideo, Uruguay. pp.76-81, 2002. 〈lirmm-00269328〉
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Non-Linear and Non-Split Transistor MOS Model for Gate Oxyde Short. DBT: Defect Based Testing, Apr 2002, Monterey, CA, United States. IEEE International Workshop on Defect Based Testing, pp.11-16, 2002. 〈lirmm-00269333〉
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Modeling Gate Oxide Short Defects in CMOS Minimum Transistors. ETW: European Test Workshop, 2002, Corfu, Greece. 7th IEEE European Test Workshop, pp.15-20, 2002. 〈lirmm-00268527〉
    • Uroš Kač, Franc Novak, Jozef Stefan, Florence Azaïs, Pascal Nouet, et al.. Experimental test infrastructure supporting IEEE 11494 Standard. ETW: European Test Workshop, 2002, Corfou, Greece. 7th IEEE European Test Workshop, 2002. 〈lirmm-00268606〉
    • Uroš Kač, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell. Implementation of an Experimental IEEE 1149.4 Mixed-Signal Test Chip. BTW: Board Test Workshop, Oct 2002, Baltimore, United States. paper 4.2, 2002. 〈lirmm-00269342〉
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Boolean and Current Detection of MOS Transistor with Gate Oxide Short. IEEE International Test Conference, Oct 2001, Baltimore, USA, pp.10, 2001. 〈lirmm-00370400〉
    • Marcelo Lubaszewski, Michel Renovell, Florence Azaïs, Yves Bertrand. A multi-mode stimuli generator for analogue and mixed-signal built-in-self-test. IMSTW: International Mixed Signal Testing Workshop, Jun 1998, The Hague, Pays-Bas. 4th IEEE International Mixed Signal Testing Workshop, pp.100-106, 1998. 〈hal-01384740〉
    • Karl-Erwin Großpietsch, Jacob Abraham, Jürgen Maier, Hans-Dieter Kochs, Michael Nicolaidis, et al.. From dependable computing systems to computing for integrated dependable systems?. FTCS: Fault-Tolerant Computing Symposium, Jun 1998, Munich, Germany. IEEE Comput. Soc, Los Alamitos, CA, USA, 18th Annual International Symposium on Fault-Tolerant Computing, pp.296-301, 1998, Digest of Papers. 〈10.1109/FTCS.1998.689480〉. 〈hal-00013844〉
    • Marcelo Lubaszewski, Michel Renovell, Salvador Mir, Florence Azaïs, Yves Bertrand. A built-in multi-mode stimuli generator for analogue and mixed-signal testing. Brazilian Symposium on Integrated Circuit Design, 1998, Rio de Janeiro, Brazil. IEEE Computer Society, XI Brazilian Symposium on Integrated Circuit Design, pp.175-178, 1998, 〈10.1109/SBCCI.1998.715435〉. 〈hal-00005876〉
    • Michel Renovell, Marcelo Lubaszewski, S. Mir, Florence Azaïs, Yves Bertrand. A multi-mode signature analyzer for analog and mixed circuits. VLSI: Very Large Scale Integration, Aug 1997, Gramado, Brazil. IEEE, 9th IFIP International Conference on Very Large Scale Integration, pp.65-76, 1997. 〈hal-01399998〉

    Poster3 documents

    • Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, et al.. Implementing model redundancy in predictive alternate test to improve test confidence. ETS: European Test Symposium, May 2013, Avignon, France. 18th IEEE European Test Symposium, 2013, 〈10.1109/ETS.2013.6569386〉. 〈lirmm-00820077〉
    • Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell. Influence of Parasitic Memory Effect on Single-Cell Faults in SRAMs. DDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Germany. pp.159-162, 2011. 〈lirmm-00591995〉
    • Florence Azaïs, Laurent Larguier, Michel Renovell. Logic Errors in CMOS Circuits due to Simultaneous Switching Noise. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.59-64, 2007. 〈lirmm-00154744〉

    Ouvrage (y compris édition critique et traduction)1 document

    • Florence Azaïs, Serge Bernard, Yves Bertrand, Marie-Lise Flottes, Patrick Girard, et al.. Test de Circuits et de Systèmes Intégrés. Collection EGEM, Ed.Hermès, 2004, 2-7462-0864-4. 〈lirmm-00109158〉

    Chapitre d'ouvrage2 documents

    • Michel Renovell, Florence Azaïs, Joan Figueras, Rosa Rodríguez-Montañés, Daniel Arumi. Models for Bridging Defects. Models in Hardware Testing, 43, Springer Netherlands, pp.33-70, 2010, Frontiers in Electronic Testing, 978-90-481-3281-2. 〈lirmm-00371365〉
    • Serge Bernard, Philippe Cauvet, Michel Renovell. SIP Test Architectures. Morgan Kaufmann Publishers. System-on-chip Test Architectures: Nanometer Design for Testability, Elsevier, pp.405-441, 2007, 978-0-12-373973-5. 〈lirmm-00195243〉

    Direction d'ouvrage, Proceedings, Dossier4 documents

    • Michel Robert, Michel Renovell, Samir Ben Ahmed, Slim Ben Saoud. First International Conference on Embedded Systems and Critical Applications (ICESCA 2008). May 2008, Tunis, Tunisia. 2008. 〈lirmm-00342663〉
    • Patrick Girard, Michel Renovell, Mohamed Masmoudi, Jaouhar Mouine. International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS 2006). Tunis, Tunisia. IEEE, 447 p., 2006, 0-7803-9726-6. 〈10.1109/DTIS.2006.1708761〉. 〈lirmm-00136926〉
    • Michel Renovell, Seiji Kajihara, Ibrahim Ai-Bahadly, Serge Demidenko. The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002): 29-31 January 2002 Christchurch, New Zealand. Jan 2002, Christchurch, New Zealand. IEEE Computer Society, 2002, 0-7695-1453-7. 〈lirmm-00268664〉
    • Manfred Glesner, Peter Zipf, Michel Renovell. Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream: 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002 Proceedings. France. Springer, 2002, Lecture Notes in Computer Science, 978-3-540-44108-3. 〈10.1007/3-540-46117-5〉. 〈lirmm-00268656〉

    Autre publication15 documents

    • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Rapport Technique intermédiaire, Contrat TOETS CT 302, Programme CEE CATRENE. 2011. 〈lirmm-00679018〉
    • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Rapport Technique de fin d'année, Contrat TOETS CT 302, Programme CEE CATRENE. 2011. 〈lirmm-00679022〉
    • Patrick Girard, Florence Azaïs, Serge Bernard, Alberto Bosio, Luigi Dilillo, et al.. TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année. 2010. 〈lirmm-00461745〉
    • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Contrat TOETS CT 302 - Programme CEE CATRENE (Rapport Intermédiaire). 2010. 〈lirmm-00504873〉
    • Patrick Girard, Serge Bernard, Alberto Bosio, Luigi Dilillo, Marie-Lise Flottes, et al.. Rapport Technique de fin de Contrat NanoTEST 2A702, Programme CEE MEDEA+. 2009. 〈lirmm-00406974〉
    • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA - Rapport Technique intermédiaire. 2007. 〈lirmm-00199966〉
    • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA - Rapport Technique de fin d'année. 2007. 〈lirmm-00199958〉
    • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702, Programme CEE MEDEA +. 2006. 〈lirmm-00130759〉
    • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA+. 12927. 2006. 〈lirmm-00102699〉
    • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702, Programme CEE MEDEA+. 2006. 〈lirmm-00130758〉
    • Patrick Girard, Michel Renovell, Serge Bernard, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Advanced Solutions for Innovative SOC Testing in Europe. 12702. 2004. 〈lirmm-00109190〉
    • Patrick Girard, Michel Renovell, Florence Azaïs, Yves Bertrand, Marie-Lise Flottes, et al.. Advanced Solutions for Innovative SOC Testing in Europe, Contrat CEE ASSOCIATE A503, Programme MEDEA+ (Rapport Technique Intermédiaire). 10042. 2003, pp.P nd. 〈lirmm-00269720〉
    • Patrick Girard, Michel Renovell, Florence Azaïs, Serge Bernard, Marie-Lise Flottes, et al.. Advanced Solutions for Innovative SOC Testing in Europe, Contrat CEE ASSOCIATE A503, Programme MEDEA+ (Rapport Technique de Fin d'Année). 10072. 2003, pp.P nd. 〈lirmm-00269749〉
    • Patrick Girard, Florence Azaïs, Serge Bernard, Yves Bertrand, Marie-Lise Flottes, et al.. Advanced Solutions for Innovative SOC Testing in Europe. 7724. 2002. 〈lirmm-00268586〉
    • Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell. Mixed-Signal BISR. 9566. 2002. 〈lirmm-00268607〉

    Rapport3 documents

    • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat Nano TEST 2A702, Programme CEE MEDEA (Rapport Intermédiaire). 08027, 2008. 〈lirmm-00344415〉
    • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat Nano TEST 2A702, Programme CEE MEDEA (Rapport Technique de fin d'année). 08026, 2008. 〈lirmm-00344408〉
    • Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand, J.M. Portal. A Compact Model for Electrical Simulation of MOS Transistor with Gate Oxide Short Defect. 04080, 2004. 〈lirmm-00109221〉