Mots-clés

Identifiants chercheur

  • IdHAL : mfaverge
Nombre de documents

63

Mathieu Faverge


Je suis actuellement maître de conférence à l'ENSEIRB-MatMeca.


Article dans une revue7 documents

  • Grégoire Pichon, Mathieu Faverge, Pierre Ramet, Jean Roman. Reordering Strategy for Blocking Optimization in Sparse Linear Solvers. SIAM Journal on Matrix Analysis and Applications, Society for Industrial and Applied Mathematics, 2017, SIAM Journal on Matrix Analysis and Applications, 38 (1), pp.226 - 248. <http://epubs.siam.org/toc/sjmael/38/1>. <10.1137/16M1062454>. <hal-01485507v2>
  • Mathieu Faverge, Julien Herrmann, Julien Langou, Bradley Lowery, Yves Robert, et al.. Mixing LU and QR factorization algorithms to design high-performance dense linear algebra solvers. Journal of Parallel and Distributed Computing, Elsevier, 2015, IPDPS 2014 Selected Papers on Numerical and Combinatorial Algorithms, 85, pp.15. <10.1016/j.jpdc.2015.06.007>. <hal-01107457>
  • Simplice Donfack, Jack Dongarra, Mathieu Faverge, Mark Gates, Jakub Kurzak, et al.. A Survey of Recent Developments in Parallel Implementations of Gaussian Elimination. Concurrency and Computation: Practice and Experience, Wiley, 2014, 27 (5), pp.1292-1309. <10.1002/cpe.3306>. <hal-00986948>
  • Jack Dongarra, Mathieu Faverge, Thomas Hérault, Mathias Jacquelin, Julien Langou, et al.. Hierarchical QR factorization algorithms for multi-core clusters. Parallel Computing, Elsevier, 2013, 39 (4-5), pp.212-232. <10.1016/j.parco.2013.01.003>. <hal-00809770>
  • George Bosilca, Aurélien Bouteiller, Anthony Danalis, Mathieu Faverge, Thomas Hérault, et al.. PaRSEC: A programming paradigm exploiting heterogeneity for enhancing scalability. Computing in Science and Engineering, Institute of Electrical and Electronics Engineers, 2013, 15 (6), pp.36-45. <10.1109/MCSE.2013.98>. <hal-00930217>
  • Jack J. Dongarra, Mathieu Faverge, Hatem Ltaief, Piotr Luszczek. Achieving Numerical Accuracy and High Performance using Recursive Tile LU Factorization. Concurrency and Computation: Practice and Experience, Wiley, 2013, 26 (6), pp.1408-1431. <http://onlinelibrary.wiley.com/doi/10.1002/cpe.3110/pdf>. <10.1002/cpe.3110>. <hal-00865472>
  • Jakub Kurzak, Piotr Luszczek, Mathieu Faverge, Jack J. Dongarra. LU Factorization with Partial Pivoting for a Multicore System with Accelerators. IEEE Transactions on Parallel and Distributed Systems, Institute of Electrical and Electronics Engineers, 2012, 99 (PrePrints), pp.1. <10.1109/TPDS.2012.242>. <hal-00809657>

Communication dans un congrès40 documents

  • Mathieu Faverge, Julien Langou, Yves Robert, Jack Dongarra. Bidiagonalization and R-Bidiagonalization: Parallel Tiled Algorithms, Critical Paths and Distributed-Memory Implementation. IPDPS'17 - 31st IEEE International Parallel and Distributed Processing Symposium , May 2017, Orlando, United States. 2017, <http://ipdps.org/>. <hal-01484113>
  • Grégoire Pichon, Mathieu Faverge, Pierre Ramet, Jean Roman. Impact of Blocking Strategies for Sparse Direct Solvers on Top of Generic Runtimes. SIAM Conference on Computation Science and Engineering (CSE'17), Feb 2017, Atlanta, United States. <http://www.siam.org/meetings/cse17/>. <hal-01421384>
  • Grégoire Pichon, Eric Darve, Mathieu Faverge, Pierre Ramet, Jean Roman. Sparse Supernodal Solver Using Hierarchical Compression over Runtime System. SIAM Conference on Computation Science and Engineering (CSE'17), Feb 2017, Atlanta, United States. <http://www.siam.org/meetings/cse17/>. <hal-01421379>
  • Grégoire Pichon, Mathieu Faverge, Pierre Ramet. Exploiting Modern Manycore Architecture in Sparse Direct Solver with Runtime Systems. SIAM Conference on Computation Science and Engineering (CSE'17), Feb 2017, Atlanta, United States. <http://www.siam.org/meetings/cse17/>. <hal-01421383>
  • Grégoire Pichon, Eric Darve, Mathieu Faverge, Pierre Ramet, Jean Roman. Sparse Supernodal Solver Using Block Low-Rank Compression. 18th IEEE International Workshop on Parallel and Distributed Scientific and Engineering Computing (PDSEC 2017), Jun 2017, Orlando, United States. <hal-01502215>
  • Grégoire Pichon, Mathieu Faverge, Pierre Ramet, Jean Roman. Impact of Blocking Strategies for Sparse Direct Solvers on Top of Generic Runtimes. SIAM Conference on Parallel Processing for Scientific Computing (SIAM PP 2016), Apr 2016, Paris, France. 2016, <http://www.siam.org/meetings/pp16/>. <hal-01251808>
  • Grégoire Pichon, Eric Darve, Mathieu Faverge, Pierre Ramet, Jean Roman. Exploiting H-Matrices in Sparse Direct Solvers. SIAM Conference on Parallel Processing for Scientific Computing (SIAM PP 2016), Apr 2016, Paris, France. 2016, <http://www.siam.org/meetings/pp16/>. <hal-01251812>
  • Mathieu Faverge, Grégoire Pichon, Pierre Ramet. Exploiting Kepler architecture in sparse direct solver with runtime systems. 9th International Workshop on Parallel Matrix Algorithms and Applications (PMAA'2016), Jul 2016, Bordeaux, France. <https://pmaa16.sciencesconf.org/>. <hal-01421372>
  • Grégoire Pichon, Eric Darve, Mathieu Faverge, Pierre Ramet, Jean Roman. On the use of low rank approximations for sparse direct solvers. SIAM Annual Meeting (AN'16), Jul 2016, Boston, United States. <http://www.siam.org/meetings/an16/>. <hal-01421376>
  • Grégoire Pichon, Eric Darve, Mathieu Faverge, Pierre Ramet, Jean Roman. Sparse Supernodal Solver Using Hierarchical Compression. Workshop on Fast Direct Solvers, Nov 2016, Purdue, United States. <http://www.math.purdue.edu/~xiaj/FastSolvers2016/index.html>. <hal-01421368>
  • Mathieu Faverge, Grégoire Pichon, Pierre Ramet, Jean Roman. On the use of H-Matrix Arithmetic in PaStiX: a Preliminary Study. Workshop on Fast Direct Solvers, Jun 2015, Toulouse, France. <hal-01187882>
  • Mathieu Faverge, Grégoire Pichon, Pierre Ramet, Jean Roman. Blocking strategy optimizations for sparse direct linear solver on heterogeneous architectures. Sparse Days, Jun 2015, Saint Girons, France. <hal-01187881>
  • Xavier Lacoste, Mathieu Faverge, Pierre Ramet. On the design of parallel linear solvers for large scale problems. Mini-Symposium on Recent advances in matrix computations for extreme-scale computers at ICIAM'15 conference, Aug 2015, Beijing, China. <hal-01100987>
  • Xavier Lacoste, Mathieu Faverge, Pierre Ramet. A task-based sparse direct solver suited for large scale hierarchical/heterogeneous architectures. SIAM Conference on Computational Science and Engineering (SIAM CSE 2015), Mar 2015, Salt Lake City, United States. <hal-01100979>
  • Wei Wu, Aurelien Bouteiller, George Bosilca, Mathieu Faverge, Jack Dongarra. Hierarchical DAG Scheduling for Hybrid Distributed Systems. IEEE International Parallel & Distributed Processing Symposium (IPDPS 2015), May 2015, Hyderabad, India. <hal-01078359>
  • Salli Moustafa, Mathieu Faverge, Laurent Plagne, Pierre Ramet. 3D Cartesian Transport Sweep for Massively Parallel Architectures with PARSEC. IEEE International Parallel & Distributed Processing Symposium (IPDPS 2015), May 2015, Hyderabad, India. pp.581-590, <10.1109/IPDPS.2015.75>. <hal-01078362>
  • Grégoire Pichon, Azzam Haidar, Mathieu Faverge, Jakub Kurzak. Divide and Conquer Symmetric Tridiagonal Eigensolver for Multicore Architectures. IEEE International Parallel & Distributed Processing Symposium (IPDPS 2015), May 2015, Hyderabad, India. <hal-01078356v3>
  • Emmanuel Agullo, Olivier Aumage, Mathieu Faverge, Nathalie Furmento, Florent Pruvost, et al.. Overview of Distributed Linear Algebra on Hybrid Nodes over the StarPU Runtime. SIAM Conference on Parallel Processing for Scientific Computing (SIAM PP 2014), Feb 2014, Portland, Oregon, United States. 2014. <hal-00978602>
  • Salli Moustafa, Mathieu Faverge, Laurent Plagne, Pierre Ramet. Parallel 3D Sweep Kernel with PARSEC. HPCC Workshop on HPC-CFD in Energy/Transport Domains, Aug 2014, Paris, France. <hal-01078364>
  • Emmanuel Agullo, Olivier Aumage, Mathieu Faverge, Nathalie Furmento, Florent Pruvost, et al.. Harnessing clusters of hybrid nodes with a sequential task-based programming model. International Workshop on Parallel Matrix Algorithms and Applications (PMAA 2014), Jul 2014, Lugano, Switzerland. 2014. <hal-01283949>
  • Emmanuel Agullo, Mathieu Faverge, Luc Giraud, Abdou Guermouche, Pierre Ramet, et al.. Toward parallel scalable linear solvers suited for large scale hierarchical parallel platforms. World Congress on Computational Mechanics, Jul 2014, Barcelona, Spain. 2014. <hal-00987110>
  • Xavier Lacoste, Mathieu Faverge, Pierre Ramet, Samuel Thibault, George Bosilca. Taking advantage of hybrid systems for sparse direct solvers via task-based runtimes. HCW'2014 workshop of IPDPS, May 2014, Phoenix, United States. IEEE, pp.29-38, 2014, <10.1109/IPDPSW.2014.9>. <hal-00987094>
  • Mathieu Faverge, Julien Herrmann, Julien Langou, Bradley Lowery, Yves Robert, et al.. Designing LU-QR hybrid solvers for performance and stability. IEEE International Parallel & Distributed Processing Symposium (IPDPS 2014), May 2014, Phoenix, United States. 2013. <hal-00930238>
  • Guillaume Aupy, Mathieu Faverge, Yves Robert, Jakub Kurzak, Piotr Luszczek, et al.. Implementing a systolic algorithm for QR factorization on multicore clusters with PaRSEC. PROPER 2013 - 6th Workshop on Productivity and Performance, Aug 2013, Aachen, Germany. 2013. <hal-00844492>
  • George Bosilca, Aurélien Bouteiller, Mathieu Faverge, Thomas Hérault. Linear Algebra Libraries with DAG Runtimes on GPUs. SIAM Conference on Computational Science and Engineering (SIAM CSE 2013), Feb 2013, Boston, United States. 2013. <hal-00934573>
  • Jakub Kurzak, P. Luszczek, Mathieu Faverge, Jack J. Dongarra. LU Factorization with Partial Pivoting for a Multi-CPU, Multi-GPU Shared Memory System. VECPAR 2012 - 10th International Meeting on High-Performance Computing for Computational Science, Jul 2012, Kobe, Japan. 2012. <hal-00809654>
  • Mathieu Faverge, Pierre Ramet. Fine Grain Scheduling for Sparse Solver on Manycore Architectures. SIAM Conference on Parallel Processing for Scientific Computing (SIAM PP 2012), Feb 2012, Savannah, United States. 2012. <hal-00769026>
  • George Bosilca, Mathieu Faverge, Xavier Lacoste, Ichitaro Yamazaki, Pierre Ramet. Toward a supernodal sparse direct solver over DAG runtimes. Parallel Matrix Algorithms and Applications, Jun 2012, Londres, United Kingdom. 2012. <hal-00769030>
  • Jack Dongarra, Mathieu Faverge, Thomas Hérault, Julien Langou, Yves Robert. Hierarchical QR factorization algorithms for multi-core cluster systems. IPDPS'2012, the 26th IEEE International Parallel and Distributed Processing Symposium, May 2012, Shanghai, China. IEEE Computer Society Press, 2012, <10.1109/IPDPS.2012.62>. <hal-00764022>
  • Jack J. Dongarra, Mathieu Faverge, Hatem Ltaief, Piotr Luszczek. Exploiting Fine-Grain Parallelism in Recursive LU Factorization. Proceedings of ParCo 2011, Aug 2011, Ghent, Belgium. 2011. <hal-00809755>
  • Emmanuel Agullo, Cédric Augonnet, Jack Dongarra, Mathieu Faverge, Julien Langou, et al.. LU Factorization for Accelerator-based Systems. 9th ACS/IEEE International Conference on Computer Systems and Applications (AICCSA 11), Jun 2011, Sharm El-Sheikh, Egypt. 2011. <hal-00654193>
  • Emmanuel Agullo, Cédric Augonnet, Jack Dongarra, Mathieu Faverge, Hatem Ltaief, et al.. QR Factorization on a Multicore Node Enhanced with Multiple GPU Accelerators. 25th IEEE International Parallel & Distributed Processing Symposium, May 2011, Anchorage, United States. 2011. <inria-00547614>
  • François Trahay, François Rue, Mathieu Faverge, Yutaka Ishikawa, Raymond Namyst, et al.. EZTrace: a generic framework for performance analysis. IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid), May 2011, Newport Beach, CA, United States. 2011. <inria-00587216>
  • George Bosilca, Aurélien Bouteiller, Anthony Danalis, Mathieu Faverge, Azzam Haidar, et al.. Distibuted Dense Numerical Linear Algebra Algorithms on massively parallel architectures: DPLASMA. Proceedings of the 25th IEEE International Symposium on Parallel \& Distributed Processing Workshops and Phd Forum (IPDPSW'11), PDSEC 2011, May 2011, Anchorage, United States. pp.1432--1441, 2011. <hal-00809680>
  • Jack J. Dongarra, Mathieu Faverge, Hatem Ltaief, Piotr Luszczek. High Performance Matrix Inversion Based on LU Factorization for Multicore Architectures. Proceedings of MTAGS11, Nov 2011, Seattle, United States. 2011. <hal-00809750>
  • Kevin Coulomb, Augustin Degomme, Mathieu Faverge, François Trahay. An open source tool chain for performance analysis. 5th Parallel Tools Workshop, Sep 2011, Dresden, Germany. <hal-00707236>
  • Mathieu Faverge. Vers un solveur de systèmes linéaires creux adapté aux machines NUMA. RenPar'19, Sep 2009, Toulouse, France. 2009. <inria-00416496>
  • Mathieu Faverge, Pierre Ramet. A NUMA Aware Scheduler for a Parallel Sparse Direct Solver. Workshop on Massively Multiprocessor and Multicore Computers, Feb 2009, Rocquencourt, France. 5p., 2008. <inria-00416502>
  • Mathieu Faverge, Xavier Lacoste, Pierre Ramet. A NUMA Aware Scheduler for a Parallel Sparse Direct Solver. PMAA'08, 2008, Neuchâtel, Switzerland. 2008. <inria-00344709>
  • Mathieu Faverge, Pierre Ramet. Dynamic Scheduling for sparse direct Solver on NUMA architectures. PARA'08, May 2008, Trondheim, Norway. 2008, LNCS. <inria-00344026>

Chapitre d'ouvrage1 document

  • Jakub Kurzak, Piotr Luszczek, Asym Yarkhan, Mathieu Faverge, Julien Langou, et al.. Multithreading in the PLASMA Library. Mohamed Ahmed, Reda A. Ammar, Sanguthevar Rajasekaran. "Handbook of Multi and Many-Core Processing: Architecture, Algorithms, Programming, and Applications, Chapman and Hall/CRC, 2014. <hal-00809774>

Rapport14 documents

  • Grégoire Pichon, Eric Darve, Mathieu Faverge, Pierre Ramet, Jean Roman. Sparse Supernodal Solver Using Block Low-Rank Compression. [Research Report] RR-9022, Inria Bordeaux Sud-Ouest. 2017, pp.24. <hal-01450732v3>
  • Grégoire Pichon, Mathieu Faverge, Pierre Ramet, Jean Roman. Reordering strategy for blocking optimization in sparse linear solvers. [Research Report] RR-8860, Inria Bordeaux Sud-Ouest; LaBRI - Laboratoire Bordelais de Recherche en Informatique; Bordeaux INP; Université de Bordeaux. 2016, pp.26. <hal-01276746v2>
  • Dalal Sukkari, Hatem Ltaief, Mathieu Faverge, David Keyes. Asynchronous Task-Based Polar Decomposition on Manycore Architectures. [Research Report] KAUST. 2016. <hal-01387575>
  • Emmanuel Agullo, Olivier Aumage, Mathieu Faverge, Nathalie Furmento, Florent Pruvost, et al.. Achieving High Performance on Supercomputers with a Sequential Task-based Programming Model. [Research Report] RR-8927, Inria Bordeaux Sud-Ouest; Bordeaux INP; CNRS; Université de Bordeaux; CEA. 2016, pp.27. <hal-01332774>
  • Mathieu Faverge, Julien Langou, Yves Robert, Jack Dongarra. Bidiagonalization with Parallel Tiled Algorithms. [Research Report] RR-8969, INRIA. 2016. <hal-01389232v2>
  • Maher Alaya, Mathieu Faverge, Xavier Lacoste, Alexandre Péré-Laperne, Jacques Péré-Laperne, et al.. Simul'Elec and PASTIX interface specifications. [Rapport Technique] RT-0458, INRIA Bordeaux; AlgoTech; INRIA. 2015. <hal-01142204>
  • Xavier Lacoste, Mathieu Faverge, Pierre Ramet, Samuel Thibault, George Bosilca. Taking advantage of hybrid systems for sparse direct solvers via task-based runtimes. [Research Report] RR-8446, INRIA. 2014, pp.25. <hal-00925017v2>
  • Simplice Donfack, Jack Dongarra, Mathieu Faverge, Mark Gates, Jakub Kurzak, et al.. On Algorithmic Variants of Parallel Gaussian Elimination: Comparison of Implementations in Terms of Performance and Numerical Properties. [Research Report] 2013. <hal-00867837>
  • Guillaume Aupy, Mathieu Faverge, Yves Robert, Jakub Kurzak, Piotr Luszczek, et al.. Implementing a Systolic Algorithm for QR Factorization on Multicore Clusters with PaRSEC. [Research Report] RR-8390, INRIA. 2013, pp.16. <hal-00879248>
  • Xavier Lacoste, Pierre Ramet, Mathieu Faverge, Yamazaki Ichitaro, Jack Dongarra. Sparse direct solvers with accelerators over DAG runtimes. [Research Report] RR-7972, INRIA. 2012, pp.11. <hal-00700066v2>
  • Dulceneia Becker, Mathieu Faverge, Jack J. Dongarra. Towards a Parallel Tile LDL Factorization for Multicore Architectures. [Research Report] 2011. <hal-00809663>
  • Jack J. Dongarra, Mathieu Faverge, Hatem Ltaief, Piotr Luszczek. Achieving Numerical Accuracy and High Performance using Recursive Tile LU Factorization. [Research Report] 2011. <hal-00809765>
  • Mathieu Faverge, Xavier Lacoste, Pierre Ramet. A NUMA Aware Scheduler for a Parallel Sparse Direct Solver. [Research Report] RR-7498, INRIA. 2010, pp.22. <inria-00549827>
  • George Bosilca, Aurélien Bouteiller, Anthony Danalis, Mathieu Faverge, Azzam Haidar, et al.. Distibuted Dense Numerical Linear Algebra Algorithms on Massively Parallel Architectures: DPLASMA. [Research Report] 2010. <hal-00809712>

Thèse1 document

  • Mathieu Faverge. Ordonnancement hybride statique-dynamique en algèbre linéaire creuse pour de grands clusters de machines NUMA et multi-cœurs. Modélisation et simulation. Université Sciences et Technologies - Bordeaux I, 2009. Français. <tel-00453997>