MD
Maxime Darnon
6
Documents
Identifiants chercheurs
maxime-darnon-
0000-0002-6188-7157
- Google Scholar : https://scholar.google.fr/citations?user=ZRXEV4AAAAAJ&hl=fr
- IdRef : 124051758
Présentation
Publications
- 6
- 4
- 3
- 3
- 3
- 3
- 3
- 3
- 2
- 2
- 2
- 1
- 1
- 1
- 1
- 2
Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH3F/O2/He plasmasJournal of Vacuum Science and Technology, 2014, B 32 ,, pp.021807. ⟨10.1116/1.4867357⟩
Article dans une revue
hal-00968799v1
|
|
Silicon recess minimization during gate patterning using synchronous plasma pulsingJournal of Vacuum Science and Technology, 2012, pp.B 30, 040604. ⟨10.1116/1.4737125⟩
Article dans une revue
hal-00777317v1
|
Self assembly patterning using block copolymer for advanced CMOS Technology : optimisation of plasma etching processesSPIE, 2012, United States. pp.83280M, ⟨10.1117/12.916399⟩
Communication dans un congrès
hal-00944979v1
|
|
Investigation of synchronized pulsed plasmas for highly selective etching of Si3N4 spacersPacific Rim Meeting of the Electrochemical and Solid State Society (PRiME), 2012, Hawai, United States
Communication dans un congrès
hal-00808854v1
|
|
Self-assembly patterning using block copolymer for advanced CMOS technology: optimisation of plasma etching processSPIE-AL, 2012, San Jose, CA, United States
Communication dans un congrès
hal-00808863v1
|
|
Self-assembly patterning using block copolymer for advanced CMOS technology: optimisation of plasma etching processSPIE, 2012, United States. Volume: 8328 Pages: 83280M (6 pp.), ⟨10.1117/12.91639⟩
Communication dans un congrès
hal-00808850v1
|