Skip to Main content
Number of documents

6

Matthieu Moy


https://matthieu-moy.fr/


Laboratoire de l'Informatique du Parallélisme   

Conference papers6 documents

  • Gabriel Busnot, Tanguy Sassolas, Nicolas Ventroux, Matthieu Moy. Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models. ASP-DAC 2020 - 25th Asia and South Pacific Design Automation Conference, Jan 2020, Beijing, China. pp.1-6. ⟨hal-02416253⟩
  • Maximilien Dupont de Dinechin, Matheus Schuh, Matthieu Moy, Claire Maïza. Scaling Up the Memory Interference Analysis for Hard Real-Time Many-Core Systems. DATE 2020 - Design, Automation and Test in Europe Conference, Mar 2020, Grenoble, France. pp.1-4. ⟨hal-02431273⟩
  • Amaury Graillat, Claire Maiza, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin. Response Time Analysis of Dataflow Applications on a Many-Core Processor with Shared-Memory and Network-on-Chip. RTNS 2019 - 27th International Conference on Real-Time Networks and Systems, Nov 2019, Toulouse, France. pp.61-69, ⟨10.1145/3356401.3356416⟩. ⟨hal-02320463⟩
  • Tristan Delizy, Stéphane Gros, Kevin Marquet, Matthieu Moy, Tanguy Risset, et al.. Estimating the Impact of Architectural and Software Design Choices on Dynamic Allocation of Heterogeneous Memories. RSP 2018 - 29th International Symposium on Rapid System Prototyping, Oct 2018, Turin, Italy. pp.1-7. ⟨hal-01891599⟩
  • Tristan Delizy, Stéphane Gros, Kevin Marquet, Matthieu Moy, Tanguy Risset, et al.. Quels objets en NVRAM ? Placement en mémoires de travail hétérogènes. Compas 2018 - Conférence d’informatique en Parallélisme, Architecture et Système, Jul 2018, Toulouse, France. pp.1-8. ⟨hal-01891398⟩
  • Amaury Graillat, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin. Parallel Code Generation of Synchronous Programs for a Many-core Architecture. DATE 2018 - Design, Automation and Test in Europe, Mar 2018, Dresden, Germany. pp.1139-1142, ⟨10.23919/DATE.2018.8342182⟩. ⟨hal-01667594v2⟩